Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/1.2/patches/2235166/?format=api
{ "id": 2235166, "url": "http://patchwork.ozlabs.org/api/1.2/patches/2235166/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260508183717.193630-7-tdave@nvidia.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.2/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260508183717.193630-7-tdave@nvidia.com>", "list_archive_url": null, "date": "2026-05-08T18:37:15", "name": "[RFC,6/8] hw/pci: finalize bridge prefetch windows after BAR allocation", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "687dbe9e7be6dadc7b6943bab56bb28080b5d276", "submitter": { "id": 89928, "url": "http://patchwork.ozlabs.org/api/1.2/people/89928/?format=api", "name": "Tushar Dave", "email": "tdave@nvidia.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260508183717.193630-7-tdave@nvidia.com/mbox/", "series": [ { "id": 503429, "url": "http://patchwork.ozlabs.org/api/1.2/series/503429/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=503429", "date": "2026-05-08T18:37:09", "name": "hw/arm/virt, hw/pci: PCI pre-enumeration and fixed BAR allocation", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/503429/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2235166/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2235166/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=pxEOEInb;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)", "dkim=none (message not signed)\n header.d=none;dmarc=none action=none header.from=nvidia.com;" ], "Received": [ "from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4gByYx41p4z1yCg\n\tfor <incoming@patchwork.ozlabs.org>; Sat, 09 May 2026 04:38:45 +1000 (AEST)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1wLQ5Y-0006jP-In; Fri, 08 May 2026 14:38:16 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <tdave@nvidia.com>)\n id 1wLQ5Q-0006h5-KZ; Fri, 08 May 2026 14:38:08 -0400", "from\n mail-northcentralusazlp170100001.outbound.protection.outlook.com\n ([2a01:111:f403:c105::1] helo=CH1PR05CU001.outbound.protection.outlook.com)\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <tdave@nvidia.com>)\n id 1wLQ5P-0002b2-4Q; Fri, 08 May 2026 14:38:08 -0400", "from BY5PR12MB4179.namprd12.prod.outlook.com (2603:10b6:a03:211::8)\n by DM4PR12MB6205.namprd12.prod.outlook.com (2603:10b6:8:a8::19) with\n Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9891.15; Fri, 8 May\n 2026 18:37:53 +0000", "from BY5PR12MB4179.namprd12.prod.outlook.com\n ([fe80::2036:e8b:9b3:f325]) by BY5PR12MB4179.namprd12.prod.outlook.com\n ([fe80::2036:e8b:9b3:f325%4]) with mapi id 15.20.9891.019; Fri, 8 May 2026\n 18:37:53 +0000" ], "ARC-Seal": "i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none;\n b=eT0FLiYrrnD8zhY2JlBq7gdL/O7SGz2cEQdyK1GniyjalQrxrOOZtsaBfR19//6eUU3Cw8eHtTcQwrQ+zD6/5nwjXNtRwMnnMUDqJQnW8tub5FSRHIzfaCT63DR6uSv/4vxskd+J58i8D0DT6dg/k8topfu+sIDwny9AYBCFRFOD3LYaV/zwZ/Gt5qCp2LSzXcn8yGZT+29eOn+5srUoGC6g3klj7ABqaZPZQ8IyFtFDW6Prllru8e9ceY4VLey8ZFOdhHtAGNpWQx7kJz6IkmuBUyMr6AYVB5HNhUTbR6RA3+aqBdgSq2Ih6AboQPOPgeL6cfIDShx7lkBIMn4o7Q==", "ARC-Message-Signature": "i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com;\n s=arcselector10001;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1;\n bh=cj57KYpH+U+ZkBnHApaa/HFz/IbHpgaR9J4GKr3XX24=;\n b=FOQXXh8F1xVQwOONNfqCvPbge9lCxQZCIoiGoYYESfzBXyqtN6ckMgr7nXf0XvLBWwWHk4YoKU2x0CLzrkwtH+jDDJ8285Yctijbg216Yf3W2c9rjdsonV43ipVsgFBq6ekiHG/DoRnrI0JUukixTMaW+QcsUshY44xXr3G88wLfNPXj/rdD1LpqLDS6osaE7j/dI8+ipDoGmdcJUEmzFWfwh3eEnfOp7WDITC0pG2U9uN6AxPx9+RyPfAnA5t7IxPyzh5KrYKOnIcTd/9J9bvtZ1fuozYGsWkppg5XILf1Ig24+BXEE4r6Y6xmH6F/E3g3BvkQvvpcmDxP5J68FXQ==", "ARC-Authentication-Results": "i=1; mx.microsoft.com 1; spf=pass\n smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com;\n dkim=pass header.d=nvidia.com; arc=none", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com;\n s=selector2;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=cj57KYpH+U+ZkBnHApaa/HFz/IbHpgaR9J4GKr3XX24=;\n b=pxEOEInbgSZ+oQ4NwA6FzN1NUNEqfQ9gc2a7FI5qklh4aVSZEEcvGRicQSAfhCCwInKZ04cYHXYyZuZJ3rvqauAhLRabPia5caFc2p9o168H570nwMAEAWg3ZS9zn7oDZ19XUT6dWhhnunxdPSkECy3CHpf69+FIlyMWqiqYL3yTRr3Um1R9lb9/qVG+4EGu41o5jfP64qidPBDrEFUWBZxlaQYQXl5ODoWLLhEtxEhI5x1HvhaNb4uivm95jsYz0g/J5Jf2+qj7wxwpQQKLZmp1hk6d5rGmL4phSZPnIVVaP0rs6V9GyX5zjJqjbIy5m4ZafdJNE7tzIvfObuRX9A==", "From": "Tushar Dave <tdave@nvidia.com>", "To": "qemu-devel@nongnu.org", "Cc": "alwilliamson@nvidia.com, jgg@nvidia.com, skolothumtho@nvidia.com,\n qemu-arm@nongnu.org, peter.maydell@linaro.org, mst@redhat.com,\n marcel.apfelbaum@gmail.com, devel@edk2.groups.io", "Subject": "[RFC PATCH 6/8] hw/pci: finalize bridge prefetch windows after BAR\n allocation", "Date": "Fri, 8 May 2026 13:37:15 -0500", "Message-Id": "<20260508183717.193630-7-tdave@nvidia.com>", "X-Mailer": "git-send-email 2.34.1", "In-Reply-To": "<20260508183717.193630-1-tdave@nvidia.com>", "References": "<20260508183717.193630-1-tdave@nvidia.com>", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-ClientProxiedBy": "BN9PR03CA0939.namprd03.prod.outlook.com\n (2603:10b6:408:108::14) To BY5PR12MB4179.namprd12.prod.outlook.com\n (2603:10b6:a03:211::8)", "MIME-Version": "1.0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "BY5PR12MB4179:EE_|DM4PR12MB6205:EE_", "X-MS-Office365-Filtering-Correlation-Id": "929ce5f3-2add-4657-8224-08dead30ea64", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;\n ARA:13230040|366016|1800799024|376014|22082099003|18002099003|56012099003;", "X-Microsoft-Antispam-Message-Info": "\n h50peUehNe2TI53gNJnMaKv9Gb8kzNXGt30xVoVnLLinerphPhHRRSegMh56AYjdYOY/Kg9y9OeFao+cvcx2GqTeDQPSBkpQTkgDtmjIViuA+8/OzHMmT5kQObL7vk/mTUSaMMLI+PmcH2k31PPGoCGp5zDpCU8t2pz614feTF5oV79hKn5HyUgeSqoU+pHTUsnGSkHzlIh8hQO16aCgg2HaMIhkwtCBnsXQvfUEo9BCfOkYkz7ZClIJxKLaQXsfbcn+ffLtuFWEdC50Rb5ecGTZO0yLgPcoP+0u34Ye3liX2I0/ed7V2FOFSWcrU7fPh2yJZN++htn97fjQ+hmxXsoqiI0gbTI3Zz7u7oZYHl2Paih3CEwXFh/u/jutd46Zl1hZ/GEc/sw0F0Ri8ZhXCF2O5qygL058ZeFm0MAlbmfJbSJZTmhvRCYmgTNri4wJ5XtM0mwUMqHuCRbut5OGH7MBUJmrffG9m1NejN/ldezVKU3zk4qrs2gPxksrrrvg4kkVk/d/azOghxZzbpmFSz2+Ot1A7bm9PizRAA+22ZBIc1c46ZqnhagWK279oaOd5XVxFlQdrKfZEukmfjG1dlGjd6M1x2q8OE/6HOBJmXBQ4Z4LHVFuB92/aYMQyfpdj0CIeBuxkYWFDnpZg1UWHg5femBMAZ6KrUi5oN1KsU5EiqwoYhmc+xqIhrqjxvJd", "X-Forefront-Antispam-Report": "CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:;\n IPV:NLI; SFV:NSPM; H:BY5PR12MB4179.namprd12.prod.outlook.com; PTR:; CAT:NONE;\n SFS:(13230040)(366016)(1800799024)(376014)(22082099003)(18002099003)(56012099003);\n DIR:OUT; SFP:1101;", "X-MS-Exchange-AntiSpam-MessageData-ChunkCount": "1", "X-MS-Exchange-AntiSpam-MessageData-0": "\n xHXZRtrlz4OQ0TfPI23YJrURC4EVzZMqQuErw/qWe0pa5NcwH8NGM44SozClq394xXWYiFTrjD8tqU6X7eXOT5xgTuMp1uIygOXwjJPN9aHs/f0VraH7eR+rbYdueMwYYn/EoCf7kMHKrmpEELvkNFegYU5XTS5TCJf/bqoRu+KchWlvIrylA4GBsXN+w3OsoxZn74uT6ky06uUTNuEd7LJ1GiFmAaVatwb8rDZweLT/A3uxLGQj2Ih6kRBVlOORgzOhUsrYHw0BIMX6SdkiXSxZkbigdFG+/keTZrkxnFezrK/njA3QsoQJd+rj8HJoAoo7TIiVJKOy/RpzCIX9+1obBQlAexR3syOaVu0Nk+j9l4n0Hf1+E9QeS6f3OOgcGDwGm73kI3X3LNXWua9nWO6YNiv3wCBUysD1pUlIl2AhHL4835mjesUmRIIAcRC+gMpwIUWzdmTxOmghXwqSa3TbNQ9e4lhWSzSIEcrzqFfSsbZSVAtEbcEsPSJP4qE5O9GDMa1UJUekaXvgTE1oF/38cpFChGT5MhLMyJJ8YUa9xCLGmhWrOwuD/RF6U+NAsXpUMAxHo/sHbjUku21ZNAx0cFxEH6fCAzT3RYlOLWs9EXM7gxxFNjinC9/ziLjuzS6EqOhK7sFlZIh+8bEmXw6pNCpXr/z5NCY1H3jc+tY1ad8WeNV6wKheRnWFRaY92MLDqww+FM6Dg/8zz0unudIZ6u1UAIAjvkjD680qqqL2jDHJG7Px1OlQXGkYI3mM8k/VztAq47SkQVZU/uSJjBMtjkynTmDD0eWKN8bhyO38eG6UvD4y5sE8WY4S1mGJalduCmLgKiUTJjn63QxjxD3FKLIovoAzZuh63illGaNmMq0QIqq3Ci340TrNvkfMtUJ40m+TaVIYjjaRlzgvEddjCna0EFdiWG9qsXFODhM+LfNcarQJejrTimq2WwiPRH3tpKVFea4FbYfCaS2ROddFApYRrp5M4BwC4oI3a4kZyRilY2qpDFE0b/QuWsUJ0+dH9+//Ep1zgKbTBK3ZKKev9yphtzMV0WUrhefK/imzU+PfcIH+dOa6q+c7M+rPww8Jj1iYuqO72OxwQJCHT4YgaF7ZLCk4B1v3IW83WYR+4BY5B83Co2+Z7aUg/TTnN/+Hur8z+AmjzoIrvihi+ctvEgWOiajwNCMhUObmtSGYh2OzmMgeLapNzmOZ3rbfmvmAYOdB2dYlF8MAeMw3xDnOjzDX5687JQeQwOYt/NOaMQTqjunDDyzfVsUKSoyRnjvlwmGWmmoahRDEVEVSO2d0sbEN8GgyT1MkQ95DPcLkrSobQB1o33h2wMaCpF2l3rsGXNp0WRPR+blAMKmYoKO6n5SwNHVLR3TQOz953Bpp5WydCBcoSclc0B3K9j0s+6cgrqn4j1Lgv84krdagZ3TMC28J56N6uB49MigSt4RDSPzlpuiLQyEnLxnCVcqSBYaxC8HJQCZgybkUhWdcFUh+X4M0J9m8eW6EoMPiLesyQRxxrF1I6ugJLoYtdtrw+8BSjmwtyBGx1lscKCYQ/8mI/Fz3EGM30LRYxIEgT/reKo3je28Ae2JeHVo+4FBaT8Rw1rvU2EwDsxyVDX48J20XJjYkvO0o5bSUMLTfQRs4QZRqjk2YGv76E1KRuVFxci3RLkqbLIBJdT/X/xdG3CtGxBvYudKf4UfE1BjQtyIducVpkdImoP35oamPWChH75KwyIFv61d1Yx96MY3+YA==", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 929ce5f3-2add-4657-8224-08dead30ea64", "X-MS-Exchange-CrossTenant-AuthSource": "BY5PR12MB4179.namprd12.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Internal", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "08 May 2026 18:37:53.7701 (UTC)", "X-MS-Exchange-CrossTenant-FromEntityHeader": "Hosted", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-MailboxType": "HOSTED", "X-MS-Exchange-CrossTenant-UserPrincipalName": "\n qNznszFYscpEfsMg7ZUlRvbzYEJvYkhdvTvvEifwQTvU0KbwX9Em9W+admZWEsJQcienTFTQKfnDkHcVMYMq3w==", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "DM4PR12MB6205", "Received-SPF": "permerror client-ip=2a01:111:f403:c105::1;\n envelope-from=tdave@nvidia.com;\n helo=CH1PR05CU001.outbound.protection.outlook.com", "X-Spam_score_int": "-14", "X-Spam_score": "-1.5", "X-Spam_bar": "-", "X-Spam_report": "(-1.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.44,\n DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n FORGED_SPF_HELO=1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_PASS=-0.001,\n SPF_NONE=0.001 autolearn=no autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "Add a final reconciliation pass to update bridge prefetch windows\nafter all BARs have been assigned across all phases.\n\nThis ensures bridge windows accurately reflect final BAR placement\nacross all buses.\n\nSR-IOV virtual functions are not included when sizing bridge prefetch\napertures and may require additional work.\n\nSigned-off-by: Tushar Dave <tdave@nvidia.com>\n---\n hw/pci/pci-resource.c | 89 +++++++++++++++++++++++++++++++++++++++++++\n 1 file changed, 89 insertions(+)", "diff": "diff --git a/hw/pci/pci-resource.c b/hw/pci/pci-resource.c\nindex e2d2adc7de..01db59c4af 100644\n--- a/hw/pci/pci-resource.c\n+++ b/hw/pci/pci-resource.c\n@@ -190,6 +190,76 @@ static void pci_update_prefetch_window(PCIBus *bus, uint64_t base, uint64_t limi\n 4);\n }\n \n+static void pci_get_bridge_window(PCIBus *bus, void *opaque)\n+{\n+ PCIDevice *bridge = pci_bridge_get_device(bus);\n+ PciAllocCfg *pci_res = (PciAllocCfg *)opaque;\n+\n+ if (!bridge) {\n+ pci_res->wbase = pci_res->mmio32_base;\n+ pci_res->wlimit = pci_res->mmio32_base + pci_res->mmio32_size - 1;\n+ pci_res->wbase64 = pci_res->mmio64_base;\n+ pci_res->wlimit64 = pci_res->mmio64_base + pci_res->mmio64_size - 1;\n+ } else {\n+ pci_res->wbase = pci_bridge_get_base(bridge, PCI_BASE_ADDRESS_MEM_TYPE_32);\n+ pci_res->wlimit = pci_bridge_get_limit(bridge, PCI_BASE_ADDRESS_MEM_TYPE_32);\n+ pci_res->wbase64 = pci_bridge_get_base(bridge, PCI_BASE_ADDRESS_MEM_PREFETCH);\n+ pci_res->wlimit64 = pci_bridge_get_limit(bridge, PCI_BASE_ADDRESS_MEM_PREFETCH);\n+ }\n+}\n+\n+static void pci_collect_mmio64_window(PCIBus *bus, PCIDevice *dev, void *opaque)\n+{\n+ PciAllocCfg *pci_res = (PciAllocCfg *)opaque;\n+ uint64_t rbase, rlimit;\n+ uint32_t idx;\n+\n+ for (idx = 0; idx < PCI_ROM_SLOT; idx++) {\n+ PCIIORegion *res = &dev->io_regions[idx];\n+\n+ if (!res->size) {\n+ continue;\n+ }\n+ rbase = res->addr;\n+ rlimit = res->addr + res->size - 1;\n+ /* Entire BAR must lie in the window; do not count partial overlap. */\n+ if (rbase < pci_res->wbase64 || rlimit > pci_res->wlimit64) {\n+ continue;\n+ }\n+ pci_res->rbase = MIN(pci_res->rbase, rbase);\n+ pci_res->rlimit = MAX(pci_res->rlimit, rlimit);\n+ }\n+\n+ if (IS_PCI_BRIDGE(dev)) {\n+ rbase = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);\n+ rlimit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);\n+\n+ if ((rbase < pci_res->wbase64) ||\n+ (rbase > pci_res->wlimit64) ||\n+ (rlimit < pci_res->wbase64) ||\n+ (rlimit > pci_res->wlimit64)) {\n+ return;\n+ }\n+\n+ pci_res->rbase = MIN(pci_res->rbase, rbase);\n+ pci_res->rlimit = MAX(pci_res->rlimit, rlimit);\n+ }\n+}\n+\n+static void pci_bus_update_prefetch_window(PCIBus *bus, void *opaque)\n+{\n+ PciAllocCfg *pci_res = (PciAllocCfg *)opaque;\n+ pci_res->rbase = ~0;\n+ pci_res->rlimit = 0;\n+\n+ assert(pci_bridge_get_device(bus));\n+ pci_for_each_device_under_bus(bus, pci_collect_mmio64_window, pci_res);\n+\n+ if (pci_res->rlimit > pci_res->rbase) {\n+ pci_update_prefetch_window(bus, pci_res->rbase, pci_res->rlimit);\n+ }\n+}\n+\n static inline bool is_64bit_pref_bar(PCIIORegion *r)\n {\n if (!r->size) {\n@@ -1004,6 +1074,25 @@ void pci_fixed_bar_allocator(PCIBus *root, const PciFixedBarMmioParams *mmio)\n /* Phase 3: allocate BARs for buses that have no fixed-BAR devices */\n pci_for_each_bus(bus, pci_bus_phase3_allocate_no_fixed_bars, &pctx);\n \n+ memset(pci_res, 0, sizeof(PciAllocCfg));\n+ pci_resource_init_from_mmio(pci_res, mmio);\n+\n+ /* TODO: 32-bit MMIO/ROM adjustment */\n+ /* TODO: PIO assignment */\n+ /* TODO: 64-bit non-prefetchable */\n+\n+ /* Align bridge prefetch window with assigned BAR ranges */\n+ pci_get_bridge_window(bus, pci_res);\n+\n+ QLIST_FOREACH(bus, &bus->child, sibling) {\n+ pci_res->bus = bus;\n+ /* Use the full mmio64 window */\n+ pci_res->wbase64 = pci_res->mmio64_base;\n+ pci_res->wlimit64 = pci_res->mmio64_base + pci_res->mmio64_size - 1;\n+\n+ pci_for_each_bus(bus, pci_bus_update_prefetch_window, pci_res);\n+ }\n+\n /* Cleanup */\n g_hash_table_destroy(pctx.had_fixed);\n fixed_claim_regions_reset();\n", "prefixes": [ "RFC", "6/8" ] }