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GET /api/1.2/patches/2235165/?format=api
{ "id": 2235165, "url": "http://patchwork.ozlabs.org/api/1.2/patches/2235165/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260508183717.193630-4-tdave@nvidia.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.2/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260508183717.193630-4-tdave@nvidia.com>", "list_archive_url": null, "date": "2026-05-08T18:37:12", "name": "[RFC,3/8] hw/pci: introduce allocator for fixed BAR placement", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "cfdf28120b6951ef029c7172d4b44745bd72a6c7", "submitter": { "id": 89928, "url": "http://patchwork.ozlabs.org/api/1.2/people/89928/?format=api", "name": "Tushar Dave", "email": "tdave@nvidia.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260508183717.193630-4-tdave@nvidia.com/mbox/", "series": [ { "id": 503429, "url": "http://patchwork.ozlabs.org/api/1.2/series/503429/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=503429", "date": "2026-05-08T18:37:09", "name": "hw/arm/virt, hw/pci: PCI pre-enumeration and fixed BAR allocation", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/503429/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2235165/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2235165/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=uqoaK8TA;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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Overlapping fixed BARs within a device are\nalso detected, and any conflict results in an error.\n\nThis patch implements the initial phase of fixed BAR handling and\nreservation tracking. Allocation of remaining resources and bridge\nwindow setup will be added in follow-up patches.\n\nLimitations:\n\nOnly 64-bit prefetchable MMIO BARs within the MMIO64 window are\nhandled. This covers devices that use large prefetchable MMIO regions.\n32-bit MMIO, PIO, and 64-bit non-prefetchable BARs are not supported\nand will be addressed in future work.\n\nSigned-off-by: Tushar Dave <tdave@nvidia.com>\n---\n hw/pci/meson.build | 1 +\n hw/pci/pci-resource.c | 255 ++++++++++++++++++++++++++++++++++++++++++\n hw/pci/pci-resource.h | 65 +++++++++++\n 3 files changed, 321 insertions(+)\n create mode 100644 hw/pci/pci-resource.c\n create mode 100644 hw/pci/pci-resource.h", "diff": "diff --git a/hw/pci/meson.build b/hw/pci/meson.build\nindex 7e8f5bb87d..d26695414f 100644\n--- a/hw/pci/meson.build\n+++ b/hw/pci/meson.build\n@@ -6,6 +6,7 @@ pci_ss.add(files(\n 'pci_bridge.c',\n 'pci_host.c',\n 'pci-enumerate.c',\n+ 'pci-resource.c',\n 'pci-hmp-cmds.c',\n 'pci-qmp-cmds.c',\n 'pcie_sriov.c',\ndiff --git a/hw/pci/pci-resource.c b/hw/pci/pci-resource.c\nnew file mode 100644\nindex 0000000000..5e9a78ec16\n--- /dev/null\n+++ b/hw/pci/pci-resource.c\n@@ -0,0 +1,255 @@\n+/*\n+ * Copyright (C) 2026 NVIDIA\n+ * Written by Tushar Dave\n+ *\n+ * SPDX-License-Identifier: GPL-2.0-or-later\n+ */\n+\n+#include \"qemu/osdep.h\"\n+#include \"qemu/error-report.h\"\n+#include \"qemu/range.h\"\n+#include \"hw/pci/pci.h\"\n+#include \"hw/pci/pci_bridge.h\"\n+#include \"hw/pci/pci_bus.h\"\n+#include \"hw/pci/pci_host.h\"\n+#include \"hw/pci/pci-resource.h\"\n+\n+/* Global list of claimed fixed 64-bit prefetchable BAR ranges */\n+static GArray *fixed_claim_regions;\n+\n+static void fixed_claim_regions_reset(void)\n+{\n+ if (fixed_claim_regions) {\n+ g_array_free(fixed_claim_regions, true);\n+ fixed_claim_regions = NULL;\n+ }\n+ fixed_claim_regions = g_array_new(false, true, sizeof(FixedClaim));\n+}\n+\n+static bool fixed_claim_regions_conflicts(uint64_t start, uint64_t end,\n+ uint64_t wbase64, uint64_t wlimit64,\n+ uint64_t *conflict_end)\n+{\n+ /* Hard guard: out-of-window ranges are invalid input */\n+ if (start < wbase64 || end > wlimit64) {\n+ error_report(\"placement [0x%\"PRIx64\"..0x%\"PRIx64\"] out of window \"\n+ \"[0x%\"PRIx64\"..0x%\"PRIx64\"]\",\n+ start, end, wbase64, wlimit64);\n+ exit(1);\n+ }\n+ if (!fixed_claim_regions) {\n+ return false;\n+ }\n+ for (guint i = 0; i < fixed_claim_regions->len; i++) {\n+ FixedClaim *c = &g_array_index(fixed_claim_regions, FixedClaim, i);\n+ if (ranges_overlap(start, end - start + 1, c->start, c->end - c->start + 1)) {\n+ if (conflict_end) {\n+ *conflict_end = c->end;\n+ }\n+ return true;\n+ }\n+ }\n+ return false;\n+}\n+\n+static void fixed_claim_regions_add(uint64_t start, uint64_t end, PCIDevice *dev, int bar)\n+{\n+ FixedClaim cl = { .start = start, .end = end, .owner = dev, .bar = bar };\n+ g_array_append_val(fixed_claim_regions, cl);\n+}\n+\n+static void pci_validate_fixed_bar(PCIDevice *dev, int bar_index,\n+ uint64_t addr, uint64_t size,\n+ uint64_t wbase64, uint64_t wlimit64)\n+{\n+ PCIIORegion *r = &dev->io_regions[bar_index];\n+ uint64_t end;\n+\n+ if (!r->size || !(r->type & PCI_BASE_ADDRESS_MEM_TYPE_64)) {\n+ error_report(\"Invalid fixed-bars for %s [%02x:%02x.%x] BAR%d: \"\n+ \"BAR not 64-bit or size=0 (type=0x%x size=0x%\"PRIx64\")\",\n+ dev->name, pci_dev_bus_num(dev),\n+ PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn),\n+ bar_index, r->type, (uint64_t)r->size);\n+ exit(1);\n+ }\n+ /* This path only programs 64-bit prefetchable MMIO in the MMIO64 window. */\n+ if (!(r->type & PCI_BASE_ADDRESS_MEM_PREFETCH) &&\n+ !pci_bus_is_root(pci_get_bus(dev))) {\n+ error_report(\"Invalid fixed-bars for %s [%02x:%02x.%x] BAR%d: \"\n+ \"this allocator only supports 64-bit prefetchable MMIO; \"\n+ \"64-bit non-prefetchable is not supported\",\n+ dev->name, pci_dev_bus_num(dev),\n+ PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn), bar_index);\n+ exit(1);\n+ }\n+ end = addr + size - 1;\n+ if (addr & (size - 1)) {\n+ error_report(\"Invalid fixed-bars alignment for %s [%02x:%02x.%x] \"\n+ \"BAR%d: addr=0x%\"PRIx64\" size=0x%\"PRIx64,\n+ dev->name, pci_dev_bus_num(dev),\n+ PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn),\n+ bar_index, addr, size);\n+ exit(1);\n+ }\n+ if (addr < wbase64 || end > wlimit64) {\n+ error_report(\"fixed-bars out of window for %s [%02x:%02x.%x] BAR%d \"\n+ \"range=[0x%\"PRIx64\"..0x%\"PRIx64\"] window=[0x%\"PRIx64\"..0x%\"PRIx64\"]\",\n+ dev->name, pci_dev_bus_num(dev),\n+ PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn),\n+ bar_index, addr, end, wbase64, wlimit64);\n+ exit(1);\n+ }\n+}\n+\n+static void pci_check_fixed_bar_overlap(PCIDevice *dev, PhysBAR *pbars)\n+{\n+ for (int i = 0; i < PCI_ROM_SLOT; i++) {\n+ if (!(pbars[i].flags & IORESOURCE_PREFETCH)) {\n+ continue;\n+ }\n+ for (int j = i + 1; j < PCI_ROM_SLOT; j++) {\n+ if (!(pbars[j].flags & IORESOURCE_PREFETCH)) {\n+ continue;\n+ }\n+ if (ranges_overlap(pbars[i].addr, dev->io_regions[i].size,\n+ pbars[j].addr, dev->io_regions[j].size)) {\n+ error_report(\"Invalid fixed-bars — fixed BAR overlap on %s [%02x:%02x.%x]: \"\n+ \"BAR%d [0x%lx..0x%lx] vs BAR%d [0x%lx..0x%lx]\",\n+ dev->name, pci_dev_bus_num(dev),\n+ PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn),\n+ i, pbars[i].addr, pbars[i].addr + dev->io_regions[i].size - 1,\n+ j, pbars[j].addr, pbars[j].addr + dev->io_regions[j].size - 1);\n+ exit(1);\n+ }\n+ }\n+ }\n+}\n+\n+/* Program 64-bit prefetchable BARs */\n+static void pci_program_prefetch_bars(PCIDevice *dev, PhysBAR *pbars)\n+{\n+ int idx;\n+ uint32_t laddr;\n+\n+ for (idx = 0; idx < PCI_ROM_SLOT; idx++) {\n+ PhysBAR *pbar = &pbars[idx];\n+\n+ if (!(pbar->flags & IORESOURCE_PREFETCH)) {\n+ continue;\n+ }\n+ laddr = pbar->addr & PCI_BASE_ADDRESS_MEM_MASK;\n+ laddr |= PCI_BASE_ADDRESS_MEM_TYPE_64;\n+ /* Set PREFETCH bit only if the BAR itself is prefetchable */\n+ if (dev->io_regions[idx].type & PCI_BASE_ADDRESS_MEM_PREFETCH) {\n+ laddr |= PCI_BASE_ADDRESS_MEM_PREFETCH;\n+ }\n+\n+ pci_host_config_write_common(dev,\n+ PCI_BASE_ADDRESS_0 + (idx * 4),\n+ pci_config_size(dev),\n+ laddr,\n+ 4);\n+ pci_host_config_write_common(dev,\n+ PCI_BASE_ADDRESS_0 + (idx * 4) + 4,\n+ pci_config_size(dev),\n+ (uint32_t)(pbar->addr >> 32),\n+ 4);\n+ }\n+}\n+\n+/* Phase 1: claim and program fixed BARs for one device (per-device callback) */\n+static void pci_dev_claim_and_program_fixed_bars(PCIBus *bus, PCIDevice *dev, void *opaque)\n+{\n+ PciProgramCtx *pctx = (PciProgramCtx *)opaque;\n+ PhysBAR *pbar, pbars[PCI_ROM_SLOT];\n+ bool had_any_fixed = false;\n+ uint64_t start;\n+ uint64_t end;\n+ int idx;\n+\n+ pbar = pbars;\n+ memset(pbar, 0, sizeof(pbars));\n+\n+ if (!dev->fixed_bar_addrs) {\n+ return;\n+ }\n+ for (idx = 0; idx < PCI_ROM_SLOT; idx++) {\n+ PCIIORegion *r = &dev->io_regions[idx];\n+ if (dev->fixed_bar_addrs[idx] == PCI_BAR_UNMAPPED) {\n+ continue;\n+ }\n+ pci_validate_fixed_bar(dev, idx,\n+ dev->fixed_bar_addrs[idx],\n+ r->size,\n+ pctx->mmio64_base,\n+ pctx->mmio64_base + pctx->mmio64_size - 1);\n+\n+ start = dev->fixed_bar_addrs[idx];\n+ end = start + r->size - 1;\n+ if (fixed_claim_regions_conflicts(start, end,\n+ pctx->mmio64_base,\n+ pctx->mmio64_base + pctx->mmio64_size - 1,\n+ NULL)) {\n+ error_report(\"Invalid fixed-bars — fixed BAR for %s [%02x:%02x.%x] \"\n+ \"BAR%d [0x%\"PRIx64\"..0x%\"PRIx64\"] overlaps an existing fixed range\",\n+ dev->name, pci_dev_bus_num(dev),\n+ PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn),\n+ idx, start, end);\n+ exit(1);\n+ }\n+ fixed_claim_regions_add(start, end, dev, idx);\n+ pbars[idx].addr = dev->fixed_bar_addrs[idx];\n+ pbars[idx].end = pbars[idx].addr + r->size - 1;\n+ pbars[idx].flags = IORESOURCE_PREFETCH;\n+ had_any_fixed = true;\n+ }\n+ if (had_any_fixed) {\n+ g_hash_table_insert(pctx->had_fixed, dev, dev);\n+ }\n+ /* Abort if intra-device fixed overlap */\n+ pci_check_fixed_bar_overlap(dev, pbars);\n+ /* Program fixed BARs now */\n+ pci_program_prefetch_bars(dev, pbars);\n+}\n+\n+static void pci_bus_claim_and_program_fixed_bars(PCIBus *bus, void *opaque)\n+{\n+ pci_for_each_device_under_bus(bus, pci_dev_claim_and_program_fixed_bars, opaque);\n+}\n+\n+static void pci_resource_init_from_mmio(PciAllocCfg *pci_res,\n+ const PciFixedBarMmioParams *mmio)\n+{\n+ pci_res->mmio32_base = mmio->mmio32_base;\n+ pci_res->mmio32_size = mmio->mmio32_size;\n+ pci_res->mmio64_base = mmio->mmio64_base;\n+ pci_res->mmio64_size = mmio->mmio64_size;\n+}\n+\n+void pci_fixed_bar_allocator(PCIBus *root, const PciFixedBarMmioParams *mmio)\n+{\n+ PciAllocCfg pci_res_buf, *pci_res = &pci_res_buf;\n+ PCIBus *bus = root;\n+\n+ /* Fill allocator MMIO window once from machine memmap */\n+ pci_resource_init_from_mmio(pci_res, mmio);\n+\n+ /* Reset fixed-claims tracking */\n+ fixed_claim_regions_reset();\n+\n+ PciProgramCtx pctx = {\n+ .mmio64_base = pci_res->mmio64_base,\n+ .mmio64_size = pci_res->mmio64_size,\n+ .had_fixed = g_hash_table_new(NULL, NULL),\n+ };\n+\n+ /* Phase 1: program all fixed BARs and claim them */\n+ pci_for_each_bus(bus, pci_bus_claim_and_program_fixed_bars, &pctx);\n+\n+ /* TODOs: Phases 2–3, program remaining BARs, bridge window refresh etc,. */\n+\n+ /* Cleanup */\n+ g_hash_table_destroy(pctx.had_fixed);\n+ fixed_claim_regions_reset();\n+}\ndiff --git a/hw/pci/pci-resource.h b/hw/pci/pci-resource.h\nnew file mode 100644\nindex 0000000000..cc4d6f71cb\n--- /dev/null\n+++ b/hw/pci/pci-resource.h\n@@ -0,0 +1,65 @@\n+/*\n+ * Copyright (C) 2026 NVIDIA\n+ * Written by Tushar Dave\n+ *\n+ * SPDX-License-Identifier: GPL-2.0-or-later\n+ */\n+\n+#ifndef HW_PCI_PCI_RESOURCE_H\n+#define HW_PCI_PCI_RESOURCE_H\n+\n+#include \"exec/hwaddr.h\"\n+#include \"hw/pci/pci.h\"\n+#include <glib.h>\n+\n+#define IORESOURCE_PREFETCH 0x00002000\n+\n+typedef struct {\n+ uint64_t addr;\n+ uint64_t end;\n+ uint64_t flags;\n+} PhysBAR;\n+\n+typedef struct {\n+ uint64_t wbase;\n+ uint64_t wlimit;\n+ uint64_t wbase64;\n+ uint64_t wlimit64;\n+ uint64_t rbase;\n+ uint64_t rlimit;\n+ uint64_t rsize;\n+ uint64_t piobase;\n+ bool available;\n+ bool search_mmio64;\n+ PCIDevice *dev;\n+ PCIBus *bus;\n+ /* Allocator window (filled once from machine memmap) */\n+ hwaddr mmio32_base;\n+ hwaddr mmio32_size;\n+ hwaddr mmio64_base;\n+ hwaddr mmio64_size;\n+} PciAllocCfg;\n+\n+typedef struct FixedClaim {\n+ uint64_t start;\n+ uint64_t end;\n+ PCIDevice *owner;\n+ int bar;\n+} FixedClaim;\n+\n+typedef struct {\n+ hwaddr mmio64_base;\n+ hwaddr mmio64_size;\n+ GHashTable *had_fixed; /* set of PCIDevice* that had at least one fixed BAR */\n+} PciProgramCtx;\n+\n+typedef struct PciFixedBarMmioParams {\n+ hwaddr mmio32_base;\n+ hwaddr mmio32_size;\n+ hwaddr mmio64_base;\n+ hwaddr mmio64_size;\n+} PciFixedBarMmioParams;\n+\n+void pci_fixed_bar_allocator(PCIBus *root, const PciFixedBarMmioParams *mmio);\n+\n+#endif\n", "prefixes": [ "RFC", "3/8" ] }