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GET /api/1.2/patches/2235104/?format=api
{ "id": 2235104, "url": "http://patchwork.ozlabs.org/api/1.2/patches/2235104/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260508-mips-octeon-missing-insns-v2-v3-22-bcbec96357d9@gmail.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.2/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260508-mips-octeon-missing-insns-v2-v3-22-bcbec96357d9@gmail.com>", "list_archive_url": null, "date": "2026-05-08T15:12:22", "name": "[v3,22/32] target/mips: add Octeon VMM0 instruction", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "49c41793e111767ff53bb7e498cbc633b529ca14", "submitter": { "id": 66301, "url": "http://patchwork.ozlabs.org/api/1.2/people/66301/?format=api", "name": "James Hilliard", "email": "james.hilliard1@gmail.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260508-mips-octeon-missing-insns-v2-v3-22-bcbec96357d9@gmail.com/mbox/", "series": [ { "id": 503407, "url": "http://patchwork.ozlabs.org/api/1.2/series/503407/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=503407", "date": "2026-05-08T15:12:00", "name": "target/mips: add missing Octeon user-mode support", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/503407/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2235104/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2235104/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=Jx1xQu2r;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4gBt3y1kHTz1yKm\n\tfor <incoming@patchwork.ozlabs.org>; Sat, 09 May 2026 01:15:58 +1000 (AEST)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1wLMuM-0005CD-DS; Fri, 08 May 2026 11:14:30 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <james.hilliard1@gmail.com>)\n id 1wLMtH-0002hS-KS\n for qemu-devel@nongnu.org; Fri, 08 May 2026 11:13:26 -0400", "from mail-oa1-x32.google.com ([2001:4860:4864:20::32])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from <james.hilliard1@gmail.com>)\n id 1wLMtF-0001km-5I\n for qemu-devel@nongnu.org; Fri, 08 May 2026 11:13:23 -0400", "by mail-oa1-x32.google.com with SMTP id\n 586e51a60fabf-42ff0576868so987731fac.1\n for <qemu-devel@nongnu.org>; Fri, 08 May 2026 08:13:20 -0700 (PDT)", "from\n 1.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.ip6.arpa\n (71-218-113-237.hlrn.qwest.net. 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charset=\"utf-8\"", "Content-Transfer-Encoding": "7bit", "Message-Id": "\n <20260508-mips-octeon-missing-insns-v2-v3-22-bcbec96357d9@gmail.com>", "References": "\n <20260508-mips-octeon-missing-insns-v2-v3-0-bcbec96357d9@gmail.com>", "In-Reply-To": "\n <20260508-mips-octeon-missing-insns-v2-v3-0-bcbec96357d9@gmail.com>", "To": "qemu-devel@nongnu.org", "Cc": "Laurent Vivier <laurent@vivier.eu>, =?utf-8?q?Philippe_Mathieu-Daud?=\n\t=?utf-8?q?=C3=A9?= <philmd@linaro.org>,\n Aurelien Jarno <aurelien@aurel32.net>,\n Jiaxun Yang <jiaxun.yang@flygoat.com>,\n Aleksandar Rikalo <arikalo@gmail.com>, Huacai Chen <chenhuacai@kernel.org>,\n James Hilliard <james.hilliard1@gmail.com>, Helge Deller <deller@gmx.de>,\n Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>,\n Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>", "X-Mailer": "b4 0.15.2", "Received-SPF": "pass client-ip=2001:4860:4864:20::32;\n envelope-from=james.hilliard1@gmail.com; helo=mail-oa1-x32.google.com", "X-Spam_score_int": "-17", "X-Spam_score": "-1.8", "X-Spam_bar": "-", "X-Spam_report": "(-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "VMM0 performs the VMULU accumulation, returns the low result, then feeds\nthat result back into the MTM0 multiplier state with a zero high operand\nand clears partial products.\n\nAdd helper and translator support for this multiplier chain-update\noperation.\n\nSigned-off-by: James Hilliard <james.hilliard1@gmail.com>\n---\nChanges v2 -> v3:\n - Split VMM0 out of the combined Octeon arithmetic and memory\n instruction patch. (requested by Richard Henderson)\n---\n target/mips/helper.h | 1 +\n target/mips/tcg/octeon.decode | 1 +\n target/mips/tcg/octeon_translate.c | 1 +\n target/mips/tcg/op_helper.c | 16 ++++++++++++++++\n 4 files changed, 19 insertions(+)", "diff": "diff --git a/target/mips/helper.h b/target/mips/helper.h\nindex f1e78ae329..46ccad95c3 100644\n--- a/target/mips/helper.h\n+++ b/target/mips/helper.h\n@@ -25,6 +25,7 @@ DEF_HELPER_3(crc32, tl, tl, tl, i32)\n DEF_HELPER_3(crc32c, tl, tl, tl, i32)\n DEF_HELPER_FLAGS_4(rotx, TCG_CALL_NO_RWG_SE, tl, tl, i32, i32, i32)\n DEF_HELPER_3(octeon_vmulu, i64, env, i64, i64)\n+DEF_HELPER_3(octeon_vmm0, i64, env, i64, i64)\n \n /* microMIPS functions */\n DEF_HELPER_4(lwm, void, env, tl, tl, i32)\ndiff --git a/target/mips/tcg/octeon.decode b/target/mips/tcg/octeon.decode\nindex 1c3dbb4a33..8a909ffcee 100644\n--- a/target/mips/tcg/octeon.decode\n+++ b/target/mips/tcg/octeon.decode\n@@ -51,6 +51,7 @@ MTP2 011100 rs:5 rt:5 00000 00000 001011 &r2\n MTM1 011100 rs:5 rt:5 00000 00000 001100 &r2\n MTM2 011100 rs:5 rt:5 00000 00000 001101 &r2\n VMULU 011100 ..... ..... ..... 00000 001111 @r3\n+VMM0 011100 ..... ..... ..... 00000 010000 @r3\n \n &saa base rt\n @saa ...... base:5 rt:5 ................ &saa\ndiff --git a/target/mips/tcg/octeon_translate.c b/target/mips/tcg/octeon_translate.c\nindex bcbf73c052..c1dd03debd 100644\n--- a/target/mips/tcg/octeon_translate.c\n+++ b/target/mips/tcg/octeon_translate.c\n@@ -313,3 +313,4 @@ TRANS(MTP0, trans_mtp, 0);\n TRANS(MTP1, trans_mtp, 1);\n TRANS(MTP2, trans_mtp, 2);\n TRANS(VMULU, trans_vmul, gen_helper_octeon_vmulu);\n+TRANS(VMM0, trans_vmul, gen_helper_octeon_vmm0);\ndiff --git a/target/mips/tcg/op_helper.c b/target/mips/tcg/op_helper.c\nindex ab3fb06a16..a1465068af 100644\n--- a/target/mips/tcg/op_helper.c\n+++ b/target/mips/tcg/op_helper.c\n@@ -176,6 +176,22 @@ uint64_t helper_octeon_vmulu(CPUMIPSState *env, uint64_t rs, uint64_t rt)\n return sum[0];\n }\n \n+uint64_t helper_octeon_vmm0(CPUMIPSState *env, uint64_t rs, uint64_t rt)\n+{\n+ uint64_t lo = helper_octeon_vmulu(env, rs, rt);\n+\n+ /*\n+ * Complete the VMULU accumulation, then apply the MTM0-style state\n+ * update with the low result and a zero high operand.\n+ */\n+ env->active_tc.octeon.MPL[0] = lo;\n+ env->active_tc.octeon.MPL[3] = 0;\n+ for (int i = 0; i < 2 * 3; i++) {\n+ env->active_tc.octeon.P[i] = 0;\n+ }\n+ return lo;\n+}\n+\n /* these crc32 functions are based on target/loongarch/tcg/op_helper.c */\n target_ulong helper_crc32(target_ulong val, target_ulong m, uint32_t sz)\n {\n", "prefixes": [ "v3", "22/32" ] }