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GET /api/1.2/patches/2235095/?format=api
{ "id": 2235095, "url": "http://patchwork.ozlabs.org/api/1.2/patches/2235095/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260508-mips-octeon-missing-insns-v2-v3-27-bcbec96357d9@gmail.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.2/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260508-mips-octeon-missing-insns-v2-v3-27-bcbec96357d9@gmail.com>", "list_archive_url": null, "date": "2026-05-08T15:12:27", "name": "[v3,27/32] target/mips: add Octeon SMS4 crypto support", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "40ecb262563a8018c9b1eb609aa2343c2f46ffcb", "submitter": { "id": 66301, "url": "http://patchwork.ozlabs.org/api/1.2/people/66301/?format=api", "name": "James Hilliard", "email": "james.hilliard1@gmail.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260508-mips-octeon-missing-insns-v2-v3-27-bcbec96357d9@gmail.com/mbox/", "series": [ { "id": 503407, "url": "http://patchwork.ozlabs.org/api/1.2/series/503407/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=503407", "date": "2026-05-08T15:12:00", "name": "target/mips: add missing Octeon user-mode support", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/503407/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2235095/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2235095/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=UAb3HPPG;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4gBt2k24w3z1yKd\n\tfor <incoming@patchwork.ozlabs.org>; Sat, 09 May 2026 01:14:54 +1000 (AEST)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1wLMuF-0004Ww-Sr; Fri, 08 May 2026 11:14:23 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <james.hilliard1@gmail.com>)\n id 1wLMtL-0002iJ-W3\n for qemu-devel@nongnu.org; Fri, 08 May 2026 11:13:28 -0400", "from mail-oa1-x34.google.com ([2001:4860:4864:20::34])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from <james.hilliard1@gmail.com>)\n id 1wLMtK-0001mY-0q\n for qemu-devel@nongnu.org; Fri, 08 May 2026 11:13:27 -0400", "by mail-oa1-x34.google.com with SMTP id\n 586e51a60fabf-435153d9b68so1271747fac.3\n for <qemu-devel@nongnu.org>; Fri, 08 May 2026 08:13:25 -0700 (PDT)", "from\n 1.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.ip6.arpa\n (71-218-113-237.hlrn.qwest.net. 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charset=\"utf-8\"", "Content-Transfer-Encoding": "8bit", "Message-Id": "\n <20260508-mips-octeon-missing-insns-v2-v3-27-bcbec96357d9@gmail.com>", "References": "\n <20260508-mips-octeon-missing-insns-v2-v3-0-bcbec96357d9@gmail.com>", "In-Reply-To": "\n <20260508-mips-octeon-missing-insns-v2-v3-0-bcbec96357d9@gmail.com>", "To": "qemu-devel@nongnu.org", "Cc": "Laurent Vivier <laurent@vivier.eu>, =?utf-8?q?Philippe_Mathieu-Daud?=\n\t=?utf-8?q?=C3=A9?= <philmd@linaro.org>,\n Aurelien Jarno <aurelien@aurel32.net>,\n Jiaxun Yang <jiaxun.yang@flygoat.com>,\n Aleksandar Rikalo <arikalo@gmail.com>, Huacai Chen <chenhuacai@kernel.org>,\n James Hilliard <james.hilliard1@gmail.com>, Helge Deller <deller@gmx.de>,\n Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>,\n Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>", "X-Mailer": "b4 0.15.2", "Received-SPF": "pass client-ip=2001:4860:4864:20::34;\n envelope-from=james.hilliard1@gmail.com; helo=mail-oa1-x34.google.com", "X-Spam_score_int": "-17", "X-Spam_score": "-1.8", "X-Spam_bar": "-", "X-Spam_report": "(-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "On Octeon, the SMS4 engine is exposed through selectors that alias the\nAES register bank. Add the missing selectors and model the shared\nRESULT, IV, and key state so the hardware interface matches the\nprocessor behaviour.\n\nUse the in-tree SM4 tables to implement the block operation without\nadding a host crypto dependency.\n\nSigned-off-by: James Hilliard <james.hilliard1@gmail.com>\n---\nChanges v1 -> v2:\n - Add selector dispatch updates in octeon_translate.c after moving\n COP2 decode out of translate.c. (suggested by Philippe\n Mathieu-Daudé)\n---\n target/mips/cpu.h | 18 ++++++\n target/mips/tcg/octeon_crypto.c | 109 +++++++++++++++++++++++++++++++++++++\n target/mips/tcg/octeon_translate.c | 4 ++\n 3 files changed, 131 insertions(+)", "diff": "diff --git a/target/mips/cpu.h b/target/mips/cpu.h\nindex 2712b882db..2457b253ae 100644\n--- a/target/mips/cpu.h\n+++ b/target/mips/cpu.h\n@@ -585,6 +585,20 @@ typedef enum MIPSOcteonCop2Sel {\n OCTEON_COP2_SEL_AES_DEC0 = 0x010e,\n OCTEON_COP2_SEL_AES_KEYLENGTH = 0x0110,\n OCTEON_COP2_SEL_AES_DAT0 = 0x0111,\n+ /*\n+ * SMS4 reuses the AES result/input, IV, and key banks and only adds\n+ * operation selectors for ECB/CBC encrypt/decrypt.\n+ */\n+ OCTEON_COP2_SEL_SMS4_RESINP0 = OCTEON_COP2_SEL_AES_RESULT0,\n+ OCTEON_COP2_SEL_SMS4_RESINP1 = OCTEON_COP2_SEL_AES_RESULT1,\n+ OCTEON_COP2_SEL_SMS4_IV0 = OCTEON_COP2_SEL_AES_IV0,\n+ OCTEON_COP2_SEL_SMS4_IV1 = OCTEON_COP2_SEL_AES_IV1,\n+ OCTEON_COP2_SEL_SMS4_KEY0 = OCTEON_COP2_SEL_AES_KEY0,\n+ OCTEON_COP2_SEL_SMS4_KEY1 = OCTEON_COP2_SEL_AES_KEY1,\n+ OCTEON_COP2_SEL_SMS4_ENC_CBC0 = OCTEON_COP2_SEL_AES_ENC_CBC0,\n+ OCTEON_COP2_SEL_SMS4_ENC0 = OCTEON_COP2_SEL_AES_ENC0,\n+ OCTEON_COP2_SEL_SMS4_DEC_CBC0 = OCTEON_COP2_SEL_AES_DEC_CBC0,\n+ OCTEON_COP2_SEL_SMS4_DEC0 = OCTEON_COP2_SEL_AES_DEC0,\n OCTEON_COP2_SEL_CRC_POLYNOMIAL = 0x0200,\n OCTEON_COP2_SEL_CRC_IV = 0x0201,\n OCTEON_COP2_SEL_CRC_LEN = 0x0202,\n@@ -653,6 +667,10 @@ typedef enum MIPSOcteonCop2Sel {\n OCTEON_COP2_SEL_AES_ENC1 = 0x310b,\n OCTEON_COP2_SEL_AES_DEC_CBC1 = 0x310d,\n OCTEON_COP2_SEL_AES_DEC1 = 0x310f,\n+ OCTEON_COP2_SEL_SMS4_ENC_CBC1 = 0x3119,\n+ OCTEON_COP2_SEL_SMS4_ENC1 = 0x311b,\n+ OCTEON_COP2_SEL_SMS4_DEC_CBC1 = 0x311d,\n+ OCTEON_COP2_SEL_SMS4_DEC1 = 0x311f,\n OCTEON_COP2_SEL_HSH_STARTMD5 = 0x4047,\n OCTEON_COP2_SEL_SNOW3G_START = 0x404d,\n OCTEON_COP2_SEL_SNOW3G_MORE = 0x404e,\ndiff --git a/target/mips/tcg/octeon_crypto.c b/target/mips/tcg/octeon_crypto.c\nindex 43012ff027..177d112483 100644\n--- a/target/mips/tcg/octeon_crypto.c\n+++ b/target/mips/tcg/octeon_crypto.c\n@@ -12,6 +12,7 @@\n #include \"exec/helper-proto.h\"\n #include \"crypto/aes.h\"\n #include \"crypto/clmul.h\"\n+#include \"crypto/sm4.h\"\n #include \"qemu/bitops.h\"\n #include \"qemu/host-utils.h\"\n \n@@ -745,6 +746,57 @@ static int octeon_aes_key_bits(const MIPSOcteonCryptoState *crypto)\n }\n }\n \n+static inline uint32_t octeon_sms4_t(uint32_t x)\n+{\n+ x = sm4_subword(x);\n+ return x ^ rol32(x, 2) ^ rol32(x, 10) ^\n+ rol32(x, 18) ^ rol32(x, 24);\n+}\n+\n+static inline uint32_t octeon_sms4_t_key(uint32_t x)\n+{\n+ x = sm4_subword(x);\n+ return x ^ rol32(x, 13) ^ rol32(x, 23);\n+}\n+\n+static void octeon_sms4_expand_key(const uint8_t *key, uint32_t round_keys[32])\n+{\n+ static const uint32_t fk[4] = {\n+ 0xa3b1bac6U, 0x56aa3350U, 0x677d9197U, 0xb27022dcU,\n+ };\n+ uint32_t k[36];\n+\n+ for (int i = 0; i < 4; i++) {\n+ k[i] = ldl_be_p(key + i * 4) ^ fk[i];\n+ }\n+ for (int i = 0; i < 32; i++) {\n+ k[i + 4] = k[i] ^ octeon_sms4_t_key(k[i + 1] ^ k[i + 2] ^\n+ k[i + 3] ^ sm4_ck[i]);\n+ round_keys[i] = k[i + 4];\n+ }\n+}\n+\n+static void octeon_sms4_crypt_block(const uint8_t *in, uint8_t *out,\n+ const uint32_t round_keys[32],\n+ bool encrypt)\n+{\n+ uint32_t x[36];\n+\n+ for (int i = 0; i < 4; i++) {\n+ x[i] = ldl_be_p(in + i * 4);\n+ }\n+ for (int i = 0; i < 32; i++) {\n+ uint32_t rk = round_keys[encrypt ? i : 31 - i];\n+\n+ x[i + 4] = x[i] ^ octeon_sms4_t(x[i + 1] ^ x[i + 2] ^\n+ x[i + 3] ^ rk);\n+ }\n+ stl_be_p(out, x[35]);\n+ stl_be_p(out + 4, x[34]);\n+ stl_be_p(out + 8, x[33]);\n+ stl_be_p(out + 12, x[32]);\n+}\n+\n static const uint8_t octeon_des_ip[64] = {\n 58, 50, 42, 34, 26, 18, 10, 2,\n 60, 52, 44, 36, 28, 20, 12, 4,\n@@ -1198,6 +1250,47 @@ static void octeon_aes_store_block(uint64_t regs[2], const uint8_t *block)\n regs[1] = ldq_be_p(block + 8);\n }\n \n+static void octeon_sms4_crypt_common(MIPSOcteonCryptoState *crypto,\n+ bool encrypt, bool cbc)\n+{\n+ uint8_t key[16];\n+ uint8_t in[16];\n+ uint8_t out[16];\n+ uint8_t iv[16];\n+ uint8_t next_iv[16];\n+ uint32_t round_keys[32];\n+\n+ /*\n+ * SMS4 aliases the AES state onto the RESULT/RESINP, IV, and KEY banks,\n+ * with only the operation selectors remaining distinct.\n+ */\n+ octeon_aes_load_key(crypto, key, sizeof(key));\n+ octeon_aes_load_block(crypto->aes_input, in);\n+ if (cbc) {\n+ octeon_aes_load_block(crypto->aes_iv, iv);\n+ if (encrypt) {\n+ for (int i = 0; i < sizeof(in); i++) {\n+ in[i] ^= iv[i];\n+ }\n+ } else {\n+ memcpy(next_iv, in, sizeof(next_iv));\n+ }\n+ }\n+\n+ octeon_sms4_expand_key(key, round_keys);\n+ octeon_sms4_crypt_block(in, out, round_keys, encrypt);\n+ if (cbc && !encrypt) {\n+ for (int i = 0; i < sizeof(out); i++) {\n+ out[i] ^= iv[i];\n+ }\n+ }\n+\n+ octeon_aes_store_block(crypto->aes_result, out);\n+ if (cbc) {\n+ octeon_aes_store_block(crypto->aes_iv, encrypt ? out : next_iv);\n+ }\n+}\n+\n static void octeon_aes_encrypt_common(MIPSOcteonCryptoState *crypto, bool cbc)\n {\n AES_KEY key;\n@@ -1614,6 +1707,22 @@ void helper_octeon_cop2_dmtc2(CPUMIPSState *env, uint64_t value,\n crypto->aes_input[1] = q;\n octeon_aes_decrypt_common(crypto, false);\n break;\n+ case OCTEON_COP2_SEL_SMS4_ENC_CBC1:\n+ crypto->aes_input[1] = q;\n+ octeon_sms4_crypt_common(crypto, true, true);\n+ break;\n+ case OCTEON_COP2_SEL_SMS4_ENC1:\n+ crypto->aes_input[1] = q;\n+ octeon_sms4_crypt_common(crypto, true, false);\n+ break;\n+ case OCTEON_COP2_SEL_SMS4_DEC_CBC1:\n+ crypto->aes_input[1] = q;\n+ octeon_sms4_crypt_common(crypto, false, true);\n+ break;\n+ case OCTEON_COP2_SEL_SMS4_DEC1:\n+ crypto->aes_input[1] = q;\n+ octeon_sms4_crypt_common(crypto, false, false);\n+ break;\n case OCTEON_COP2_SEL_GFM_XORMUL1: {\n uint64_t in[2] = {\n crypto->gfm_result[0] ^ crypto->gfm_xor0,\ndiff --git a/target/mips/tcg/octeon_translate.c b/target/mips/tcg/octeon_translate.c\nindex c75f04da63..6d123a4623 100644\n--- a/target/mips/tcg/octeon_translate.c\n+++ b/target/mips/tcg/octeon_translate.c\n@@ -180,6 +180,10 @@ static bool octeon_cop2_is_supported_dmtc2(uint16_t sel)\n case OCTEON_COP2_SEL_AES_ENC1:\n case OCTEON_COP2_SEL_AES_DEC_CBC1:\n case OCTEON_COP2_SEL_AES_DEC1:\n+ case OCTEON_COP2_SEL_SMS4_ENC_CBC1:\n+ case OCTEON_COP2_SEL_SMS4_ENC1:\n+ case OCTEON_COP2_SEL_SMS4_DEC_CBC1:\n+ case OCTEON_COP2_SEL_SMS4_DEC1:\n return true;\n default:\n return false;\n", "prefixes": [ "v3", "27/32" ] }