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GET /api/1.2/patches/2235089/?format=api
{ "id": 2235089, "url": "http://patchwork.ozlabs.org/api/1.2/patches/2235089/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260508-mips-octeon-missing-insns-v2-v3-15-bcbec96357d9@gmail.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.2/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260508-mips-octeon-missing-insns-v2-v3-15-bcbec96357d9@gmail.com>", "list_archive_url": null, "date": "2026-05-08T15:12:15", "name": "[v3,15/32] target/mips: add Octeon MTM0 instruction", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "42dbac87de0284756c6ece6cc636abe33bb6ec95", "submitter": { "id": 66301, "url": "http://patchwork.ozlabs.org/api/1.2/people/66301/?format=api", "name": "James Hilliard", "email": "james.hilliard1@gmail.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260508-mips-octeon-missing-insns-v2-v3-15-bcbec96357d9@gmail.com/mbox/", "series": [ { "id": 503407, "url": "http://patchwork.ozlabs.org/api/1.2/series/503407/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=503407", "date": "2026-05-08T15:12:00", "name": "target/mips: add missing Octeon user-mode support", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/503407/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2235089/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2235089/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=fN3omTMI;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4gBt2D5Rpzz1yM4\n\tfor <incoming@patchwork.ozlabs.org>; Sat, 09 May 2026 01:14:28 +1000 (AEST)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1wLMty-0003WC-0L; Fri, 08 May 2026 11:14:06 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <james.hilliard1@gmail.com>)\n id 1wLMtB-0002fl-05\n for qemu-devel@nongnu.org; Fri, 08 May 2026 11:13:18 -0400", "from mail-oo1-xc2b.google.com ([2607:f8b0:4864:20::c2b])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from <james.hilliard1@gmail.com>)\n id 1wLMt8-0001iH-TU\n for qemu-devel@nongnu.org; Fri, 08 May 2026 11:13:16 -0400", "by mail-oo1-xc2b.google.com with SMTP id\n 006d021491bc7-694891f8f62so1110542eaf.2\n for <qemu-devel@nongnu.org>; Fri, 08 May 2026 08:13:14 -0700 (PDT)", "from\n 1.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.ip6.arpa\n (71-218-113-237.hlrn.qwest.net. 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charset=\"utf-8\"", "Content-Transfer-Encoding": "7bit", "Message-Id": "\n <20260508-mips-octeon-missing-insns-v2-v3-15-bcbec96357d9@gmail.com>", "References": "\n <20260508-mips-octeon-missing-insns-v2-v3-0-bcbec96357d9@gmail.com>", "In-Reply-To": "\n <20260508-mips-octeon-missing-insns-v2-v3-0-bcbec96357d9@gmail.com>", "To": "qemu-devel@nongnu.org", "Cc": "Laurent Vivier <laurent@vivier.eu>, =?utf-8?q?Philippe_Mathieu-Daud?=\n\t=?utf-8?q?=C3=A9?= <philmd@linaro.org>,\n Aurelien Jarno <aurelien@aurel32.net>,\n Jiaxun Yang <jiaxun.yang@flygoat.com>,\n Aleksandar Rikalo <arikalo@gmail.com>, Huacai Chen <chenhuacai@kernel.org>,\n James Hilliard <james.hilliard1@gmail.com>, Helge Deller <deller@gmx.de>,\n Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>,\n Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>", "X-Mailer": "b4 0.15.2", "Received-SPF": "pass client-ip=2607:f8b0:4864:20::c2b;\n envelope-from=james.hilliard1@gmail.com; helo=mail-oo1-xc2b.google.com", "X-Spam_score_int": "-17", "X-Spam_score": "-1.8", "X-Spam_bar": "-", "X-Spam_report": "(-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "MTM0 loads the low multiplier operand pair from rs/rt, starts a new\nmultiplier chain, clears the upper multiplier limbs, and resets partial\nproducts.\n\nAdd the decode and translator path that writes MPL[0] and MPL[3].\n\nSigned-off-by: James Hilliard <james.hilliard1@gmail.com>\n---\nChanges v2 -> v3:\n - Split MTM0 out of the combined Octeon arithmetic and memory\n instruction patch. (requested by Richard Henderson)\n---\n target/mips/tcg/octeon.decode | 2 ++\n target/mips/tcg/octeon_translate.c | 55 ++++++++++++++++++++++++++++++++++++++\n 2 files changed, 57 insertions(+)", "diff": "diff --git a/target/mips/tcg/octeon.decode b/target/mips/tcg/octeon.decode\nindex 56c54e0973..2dadb13845 100644\n--- a/target/mips/tcg/octeon.decode\n+++ b/target/mips/tcg/octeon.decode\n@@ -43,6 +43,8 @@ SEQ 011100 ..... ..... ..... 00000 101010 @r3\n SNE 011100 ..... ..... ..... 00000 101011 @r3\n SEQI 011100 rs:5 rt:5 imm:s10 101110 &cmpi\n SNEI 011100 rs:5 rt:5 imm:s10 101111 &cmpi\n+&r2 rs rt\n+MTM0 011100 rs:5 rt:5 00000 00000 001000 &r2\n \n &saa base rt\n @saa ...... base:5 rt:5 ................ &saa\ndiff --git a/target/mips/tcg/octeon_translate.c b/target/mips/tcg/octeon_translate.c\nindex f94f765055..186200036e 100644\n--- a/target/mips/tcg/octeon_translate.c\n+++ b/target/mips/tcg/octeon_translate.c\n@@ -216,6 +216,60 @@ static bool trans_ZCBT(DisasContext *ctx, arg_zcb *a)\n return trans_ZCB(ctx, a);\n }\n \n+static ptrdiff_t octeon_tc_mpl_offset(unsigned int index)\n+{\n+ return offsetof(CPUMIPSState, active_tc.octeon.MPL[index]);\n+}\n+\n+static ptrdiff_t octeon_tc_p_offset(unsigned int index)\n+{\n+ return offsetof(CPUMIPSState, active_tc.octeon.P[index]);\n+}\n+\n+static void octeon_store_tc_field(ptrdiff_t offset, TCGv_i64 value)\n+{\n+ tcg_gen_st_i64(value, tcg_env, offset);\n+}\n+\n+static void octeon_zero_partial_product_state(void)\n+{\n+ TCGv_i64 zero = tcg_constant_i64(0);\n+\n+ for (int i = 0; i < 2 * 3; i++) {\n+ octeon_store_tc_field(octeon_tc_p_offset(i), zero);\n+ }\n+}\n+\n+static void octeon_clear_upper_multiplier_state(void)\n+{\n+ TCGv_i64 zero = tcg_constant_i64(0);\n+\n+ /*\n+ * MTM0 starts a new multiplier chain. Guest code relies on a single\n+ * MTM0 load making the remaining multiplier limbs zero unless later\n+ * MTM1/MTM2 instructions explicitly populate them.\n+ */\n+ octeon_store_tc_field(octeon_tc_mpl_offset(1), zero);\n+ octeon_store_tc_field(octeon_tc_mpl_offset(2), zero);\n+ octeon_store_tc_field(octeon_tc_mpl_offset(4), zero);\n+ octeon_store_tc_field(octeon_tc_mpl_offset(5), zero);\n+}\n+\n+static bool trans_mtm(DisasContext *ctx, arg_r2 *a, unsigned int index)\n+{\n+ TCGv_i64 value = tcg_temp_new_i64();\n+\n+ gen_load_gpr(value, a->rs);\n+ octeon_store_tc_field(octeon_tc_mpl_offset(index), value);\n+ gen_load_gpr(value, a->rt);\n+ octeon_store_tc_field(octeon_tc_mpl_offset(index + 3), value);\n+ if (index == 0) {\n+ octeon_clear_upper_multiplier_state();\n+ }\n+ octeon_zero_partial_product_state();\n+ return true;\n+}\n+\n TRANS(SAA, trans_saa, MO_UL);\n TRANS(SAAD, trans_saa, MO_UQ);\n TRANS(LBX, trans_lx, MO_SB);\n@@ -225,3 +279,4 @@ TRANS(LHUX, trans_lx, MO_UW);\n TRANS(LWX, trans_lx, MO_SL);\n TRANS(LWUX, trans_lx, MO_UL);\n TRANS(LDX, trans_lx, MO_UQ);\n+TRANS(MTM0, trans_mtm, 0);\n", "prefixes": [ "v3", "15/32" ] }