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GET /api/1.2/patches/2234976/?format=api
{ "id": 2234976, "url": "http://patchwork.ozlabs.org/api/1.2/patches/2234976/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20260508115315.252623-5-Max.Merchel@ew.tq-group.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/1.2/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260508115315.252623-5-Max.Merchel@ew.tq-group.com>", "list_archive_url": null, "date": "2026-05-08T11:53:09", "name": "[4/5] board: tq: add TQMa6UL[L]x[L] SOM and MBa6ULx baseboard", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "bac3c2e32f365bb0d22835b072a79f9792345ed0", "submitter": { "id": 89096, "url": "http://patchwork.ozlabs.org/api/1.2/people/89096/?format=api", "name": "Max Merchel", "email": "Max.Merchel@ew.tq-group.com" }, "delegate": { "id": 151988, "url": "http://patchwork.ozlabs.org/api/1.2/users/151988/?format=api", "username": "festevam", "first_name": "Fabio", "last_name": "Estevam", "email": "festevam@gmail.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20260508115315.252623-5-Max.Merchel@ew.tq-group.com/mbox/", "series": [ { "id": 503376, "url": "http://patchwork.ozlabs.org/api/1.2/series/503376/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=503376", "date": "2026-05-08T11:53:07", "name": "Add support for TQMa6UL[L]x on MBA6ULx", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/503376/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2234976/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2234976/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n unprotected) header.d=ew.tq-group.com header.i=@ew.tq-group.com\n header.a=rsa-sha256 header.s=default2602 header.b=gYowbBc8;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de;\n envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org)", "phobos.denx.de;\n dmarc=fail (p=quarantine dis=none) header.from=ew.tq-group.com", "phobos.denx.de;\n spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de", "phobos.denx.de;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n unprotected) header.d=ew.tq-group.com header.i=@ew.tq-group.com\n header.b=\"gYowbBc8\";\n\tdkim-atps=neutral", "phobos.denx.de; dmarc=pass (p=quarantine dis=none)\n header.from=ew.tq-group.com", "phobos.denx.de;\n spf=pass smtp.mailfrom=Max.Merchel@ew.tq-group.com" ], "Received": [ "from phobos.denx.de (phobos.denx.de\n [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4gBnbG3fxsz1yKd\n\tfor <incoming@patchwork.ozlabs.org>; Fri, 08 May 2026 21:54:18 +1000 (AEST)", "from h2850616.stratoserver.net (localhost [IPv6:::1])\n\tby phobos.denx.de (Postfix) with ESMTP id D1BBE84C9C;\n\tFri, 8 May 2026 13:53:34 +0200 (CEST)", "by phobos.denx.de (Postfix, from userid 109)\n id 3B60684C19; Fri, 8 May 2026 13:53:33 +0200 (CEST)", "from www537.your-server.de (www537.your-server.de [188.40.3.216])\n (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits))\n (No client certificate requested)\n by phobos.denx.de (Postfix) with ESMTPS id 6088284C7B\n for <u-boot@lists.denx.de>; Fri, 8 May 2026 13:53:28 +0200 (CEST)", "from sslproxy02.your-server.de ([78.47.166.47])\n by www537.your-server.de with esmtpsa (TLS1.3) tls TLS_AES_256_GCM_SHA384\n (Exim 4.96.2) (envelope-from <Max.Merchel@ew.tq-group.com>)\n id 1wLJln-000DVs-2l; Fri, 08 May 2026 13:53:27 +0200", "from localhost ([127.0.0.1])\n by sslproxy02.your-server.de with esmtpsa (TLS1.3) tls TLS_AES_256_GCM_SHA384\n (Exim 4.96) (envelope-from <Max.Merchel@ew.tq-group.com>)\n id 1wLJln-000PER-14; Fri, 08 May 2026 13:53:27 +0200" ], "X-Spam-Checker-Version": "SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de", "X-Spam-Level": "", "X-Spam-Status": "No, score=-2.0 required=5.0 tests=BAYES_00,DKIM_SIGNED,\n DKIM_VALID,DKIM_VALID_AU,RCVD_IN_DNSWL_BLOCKED,SPF_HELO_NONE,SPF_PASS\n autolearn=ham autolearn_force=no version=3.4.2", "DKIM-Signature": "v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed;\n d=ew.tq-group.com; s=default2602; h=Content-Transfer-Encoding:MIME-Version:\n References:In-Reply-To:Message-ID:Date:Subject:Cc:To:From:Sender:Reply-To:\n Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From:\n Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID;\n bh=OXB+RACmZC0n3isQcoYPZ3122PJMa0/UjRVj9jaWu3w=; b=gYowbBc8bsI4OAAnyfEBrcAtFg\n 8EqLCw5er23soe/sUb2E2riOeHSlGkbHfnHA4vgWdVwVOeBMUBz4GZ/oelgxREtDT2Zx7EUNjsT03\n VDaws1tORBf5lo4qli6dvntH7NN2zRuYtoZFogw3xqoJQTCjF+dd7IXW5ygtEMD3ctnpRb24yxz1A\n NoeWkKLHl+rBTH3MClZZ/srgOJQDpUfkVc/F/HtwKMhdVWIonjz16WFL//O3TfbDPKA5cWhHeD5xT\n mDBSPfHMOt4rmsBq7SlULf8wjr5gPhj4MxQLwt+Hsf/zzA6yH7lO+3Pay+lEQ9IOWH8DxF/pZqhaT\n 22AjLOdQ==;", "From": "Max Merchel <Max.Merchel@ew.tq-group.com>", "To": "Stefano Babic <sbabic@nabladev.com>, Fabio Estevam <festevam@gmail.com>,\n \"NXP i.MX U-Boot Team\" <uboot-imx@nxp.com>,\n Max Merchel <max.merchel@ew.tq-group.com>, Tom Rini <trini@konsulko.com>,\n Peng Fan <peng.fan@nxp.com>, Jaehoon Chung <jh80.chung@samsung.com>", "Cc": "Nora Schiffer <nora.schiffer@ew.tq-group.com>, u-boot@ew.tq-group.com,\n u-boot@lists.denx.de, Max Merchel <Max.Merchel@ew.tq-group.com>", "Subject": "[PATCH 4/5] board: tq: add TQMa6UL[L]x[L] SOM and MBa6ULx baseboard", "Date": "Fri, 8 May 2026 13:53:09 +0200", "Message-ID": "<20260508115315.252623-5-Max.Merchel@ew.tq-group.com>", "X-Mailer": "git-send-email 2.43.0", "In-Reply-To": "<20260508115315.252623-1-Max.Merchel@ew.tq-group.com>", "References": "<20260508115315.252623-1-Max.Merchel@ew.tq-group.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.39", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<https://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>", "X-Virus-Scanned": "clamav-milter 0.103.8 at phobos.denx.de", "X-Virus-Status": "Clean" }, "content": "From: Nora Schiffer <nora.schiffer@ew.tq-group.com>\n\nAdd Support for TQMa6UL SoM (imx6UL) Variants and MBa6ULx mainboard.\n\nSigned-off-by: Nora Schiffer <nora.schiffer@ew.tq-group.com>\nSigned-off-by: Max Merchel <Max.Merchel@ew.tq-group.com>\n---\n arch/arm/mach-imx/mx6/Kconfig | 21 +++\n board/tq/MAINTAINERS | 2 +-\n board/tq/tqma6ul/Kconfig | 114 ++++++++++++++++\n board/tq/tqma6ul/Makefile | 16 +++\n board/tq/tqma6ul/spl.c | 128 ++++++++++++++++++\n board/tq/tqma6ul/spl_mba6ul.c | 177 ++++++++++++++++++++++++\n board/tq/tqma6ul/spl_tqma6ul_ram.c | 208 +++++++++++++++++++++++++++++\n board/tq/tqma6ul/tqma6ul.c | 184 +++++++++++++++++++++++++\n board/tq/tqma6ul/tqma6ul.cfg | 23 ++++\n board/tq/tqma6ul/tqma6ul.env | 47 +++++++\n board/tq/tqma6ul/tqma6ul.h | 25 ++++\n board/tq/tqma6ul/tqma6ul_mba6ul.c | 138 +++++++++++++++++++\n doc/board/tq/index.rst | 1 +\n doc/board/tq/tqma6ul.rst | 105 +++++++++++++++\n include/configs/tqma6ul.h | 46 +++++++\n include/configs/tqma6ul_mba6ul.h | 19 +++\n 16 files changed, 1253 insertions(+), 1 deletion(-)\n create mode 100644 board/tq/tqma6ul/Kconfig\n create mode 100644 board/tq/tqma6ul/Makefile\n create mode 100644 board/tq/tqma6ul/spl.c\n create mode 100644 board/tq/tqma6ul/spl_mba6ul.c\n create mode 100644 board/tq/tqma6ul/spl_tqma6ul_ram.c\n create mode 100644 board/tq/tqma6ul/tqma6ul.c\n create mode 100644 board/tq/tqma6ul/tqma6ul.cfg\n create mode 100644 board/tq/tqma6ul/tqma6ul.env\n create mode 100644 board/tq/tqma6ul/tqma6ul.h\n create mode 100644 board/tq/tqma6ul/tqma6ul_mba6ul.c\n create mode 100644 doc/board/tq/tqma6ul.rst\n create mode 100644 include/configs/tqma6ul.h\n create mode 100644 include/configs/tqma6ul_mba6ul.h", "diff": "diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig\nindex d198d9932f4..7ed4b24b751 100644\n--- a/arch/arm/mach-imx/mx6/Kconfig\n+++ b/arch/arm/mach-imx/mx6/Kconfig\n@@ -633,6 +633,26 @@ config TARGET_TQMA6\n \timply CMD_SF\n \timply CMD_DM\n \n+config TARGET_TQMA6UL\n+\tbool \"TQ-Systems TQMa6UL[L]x\"\n+\tdepends on MX6UL || MX6ULL\n+\tselect TQ_COMMON_SOM\n+\tselect BOARD_EARLY_INIT_F\n+\tselect BOARD_LATE_INIT\n+\tselect OF_SYSTEM_SETUP\n+\tselect DM\n+\tselect DM_I2C\n+\tselect SUPPORT_SPL\n+\tselect SPL_SEPARATE_BSS if SPL\n+\timply DM_GPIO\n+\timply DM_MMC\n+\timply DM_SPI if SPI\n+\timply DM_SPI_FLASH if SPI\n+\timply SPI\n+\thelp\n+\t TQMa6UL[L]x is a TQ SoM with i.MX6UL/i.MX6ULL CPU\n+\t The SoM can be used on various baseboards.\n+\n config TARGET_UDOO\n \tbool \"udoo\"\n \tdepends on MX6QDL\n@@ -739,6 +759,7 @@ source \"board/technexion/pico-imx6/Kconfig\"\n source \"board/technexion/pico-imx6ul/Kconfig\"\n source \"board/tbs/tbs2910/Kconfig\"\n source \"board/tq/tqma6/Kconfig\"\n+source \"board/tq/tqma6ul/Kconfig\"\n source \"board/toradex/apalis_imx6/Kconfig\"\n source \"board/toradex/colibri_imx6/Kconfig\"\n source \"board/toradex/colibri-imx6ull/Kconfig\"\ndiff --git a/board/tq/MAINTAINERS b/board/tq/MAINTAINERS\nindex b31c5793432..a04a36ba415 100644\n--- a/board/tq/MAINTAINERS\n+++ b/board/tq/MAINTAINERS\n@@ -1,4 +1,4 @@\n-TQMA6\n+TQMA6 / TQMA6UL / TQMA6ULxL / TQMA6ULL / TQMA6ULLxL\n M:\tMax Merchel <max.merchel@ew.tq-group.com>\n L:\tu-boot@ew.tq-group.com\n S:\tMaintained\ndiff --git a/board/tq/tqma6ul/Kconfig b/board/tq/tqma6ul/Kconfig\nnew file mode 100644\nindex 00000000000..5d85c68b359\n--- /dev/null\n+++ b/board/tq/tqma6ul/Kconfig\n@@ -0,0 +1,114 @@\n+# SPDX-License-Identifier: GPL-2.0-or-later\n+#\n+# Copyright (c) 2016-2026 TQ-Systems GmbH <u-boot@ew.tq-group.com>,\n+# D-82229 Seefeld, Germany.\n+# Author: Marco Felsch, Markus Niebel, Max Merchel\n+#\n+\n+if TARGET_TQMA6UL\n+\n+config SYS_BOARD\n+\tdefault \"tqma6ul\"\n+\n+config SYS_VENDOR\n+\tdefault \"tq\"\n+\n+config SYS_CONFIG_NAME\n+\tdefault \"tqma6ul_mba6ul\" if MBA6UL\n+\n+choice\n+\tprompt \"TQMa6UL module variant\"\n+\tdefault TQMA6UL_VARIANT_STANDARD\n+\thelp\n+\t Select the variant of the TQMa6UL SoM module being used.\n+\t By default, the variant with board-to-board connectors is used.\n+\n+config TQMA6UL_VARIANT_STANDARD\n+\tbool \"standard module with board connector\"\n+\thelp\n+\t Select for SoM variant connector\n+\t with board to board connectors\n+\n+config TQMA6UL_VARIANT_LGA\n+\tbool \"LGA module with solder balls\"\n+\thelp\n+\t Select for SoM variant LGA\n+\t with solder balls\n+\n+endchoice\n+\n+config TQMA6UL_RAM_256M\n+\tbool\n+\n+config TQMA6UL_RAM_512M\n+\tbool\n+\n+choice\n+\tprompt \"TQMa6UL RAM configuration\"\n+\tdefault TQMA6UL_RAM_MULTI\n+\thelp\n+\t Select RAM configuration. Normally use default here but for\n+\t specific setup it is possible to use a single RAM size.\n+\n+config TQMA6UL_RAM_MULTI\n+\tbool \"TQMa6ULx with 256/512 MB RAM - Single image\"\n+\tselect TQMA6UL_RAM_256M\n+\tselect TQMA6UL_RAM_512M\n+\thelp\n+\t Build a single U-Boot solely for variants\n+\t with 256/512 MB RAM.\n+\n+config TQMA6UL_RAM_SINGLE_256M\n+\tbool \"TQMa6UL with 256 MB RAM\"\n+\tselect TQMA6UL_RAM_256M\n+\thelp\n+\t Build U-Boot solely for variants\n+\t with 256 MB RAM.\n+\n+config TQMA6UL_RAM_SINGLE_512M\n+\tbool \"TQMa6UL with 512 MB RAM\"\n+\tselect TQMA6UL_RAM_512M\n+\thelp\n+\t Build U-Boot solely for variants\n+\t with 512 MB RAM.\n+\n+endchoice\n+\n+choice\n+\tprompt \"TQMa6UL base board variant\"\n+\tdefault MBA6UL\n+\thelp\n+\t Select the baseboard variant for the TQMa6UL module.\n+\t By default the MBA6UL starterkit is used.\n+\n+config MBA6UL\n+\tbool \"TQMa6UL on MBa6ULx Starterkit\"\n+\tselect TQ_COMMON_BB\n+\tselect TQ_COMMON_SDMMC\n+\tselect SYSINFO\n+\tselect SYSINFO_TQ_EEPROM\n+\tselect I2C_EEPROM\n+\tselect MISC\n+\tselect MXC_UART\n+\timply DM_ETH\n+\timply DM_GPIO\n+\timply DM_MMC\n+\timply DM_SERIAL\n+\timply DM_SPI\n+\timply OF_UPSTREAM\n+\timply PHYLIB\n+\timply PHY_SMSC\n+\timply USB\n+\timply USB_STORAGE\n+\thelp\n+\t Select the MBa6ULx starterkit.\n+\t This is the default base board.\n+\n+endchoice\n+\n+config IMX_CONFIG\n+\tdefault \"board/tq/tqma6ul/tqma6ul.cfg\"\n+\n+source \"board/tq/common/Kconfig\"\n+\n+endif\ndiff --git a/board/tq/tqma6ul/Makefile b/board/tq/tqma6ul/Makefile\nnew file mode 100644\nindex 00000000000..f45ed4a15f6\n--- /dev/null\n+++ b/board/tq/tqma6ul/Makefile\n@@ -0,0 +1,16 @@\n+# SPDX-License-Identifier: GPL-2.0-or-later\n+#\n+# Copyright (c) 2021-2026 TQ-Systems GmbH <u-boot@ew.tq-group.com>,\n+# D-82229 Seefeld, Germany.\n+# Author: Markus Niebel, Matthias Schiffer, Max Merchel\n+#\n+\n+obj-y := tqma6ul.o\n+\n+ifdef CONFIG_SPL_BUILD\n+obj-y += spl.o\n+obj-y += spl_tqma6ul_ram.o\n+obj-$(CONFIG_MBA6UL) += spl_mba6ul.o\n+else\n+obj-$(CONFIG_MBA6UL) += tqma6ul_mba6ul.o\n+endif\ndiff --git a/board/tq/tqma6ul/spl.c b/board/tq/tqma6ul/spl.c\nnew file mode 100644\nindex 00000000000..71c5134c4f6\n--- /dev/null\n+++ b/board/tq/tqma6ul/spl.c\n@@ -0,0 +1,128 @@\n+// SPDX-License-Identifier: GPL-2.0-or-later\n+/*\n+ * Copyright (c) 2023-2026 TQ-Systems GmbH <u-boot@ew.tq-group.com>,\n+ * D-82229 Seefeld, Germany.\n+ * Author: Max Merchel\n+ */\n+\n+#include <fsl_esdhc_imx.h>\n+#include <hang.h>\n+#include <init.h>\n+#include <mmc.h>\n+#include <spl.h>\n+#include <asm/arch/clock.h>\n+#include <asm/arch/crm_regs.h>\n+#include <asm/arch/mx6-ddr.h>\n+#include <asm/arch/mx6ul_pins.h>\n+#include <asm/arch/sys_proto.h>\n+#include <asm-generic/sections.h>\n+#include <linux/sizes.h>\n+\n+#include \"../common/tq_bb.h\"\n+#include \"../common/tq_som.h\"\n+\n+static void ccgr_init(void)\n+{\n+\tstruct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;\n+\n+\twritel(0xFFFFFFFF, &ccm->CCGR0);\n+\twritel(0xFFFFFFFF, &ccm->CCGR1);\n+\twritel(0xFFFFFFFF, &ccm->CCGR2);\n+\twritel(0xFFFFFFFF, &ccm->CCGR3);\n+\twritel(0xFFFFFFFF, &ccm->CCGR4);\n+\twritel(0xFFFFFFFF, &ccm->CCGR5);\n+\twritel(0xFFFFFFFF, &ccm->CCGR6);\n+}\n+\n+#define USDHC_CLK_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \\\n+\tPAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)\n+\n+#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |\t\t\\\n+\tPAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW |\t\t\\\n+\tPAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)\n+\n+/* eMMC on USDHC2 */\n+static const iomux_v3_cfg_t tqma6ul_usdhc2_pads[] = {\n+\tMX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),\n+\tMX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),\n+\tMX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),\n+\tMX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),\n+\tMX6_PAD_NAND_DATA04__USDHC2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),\n+\tMX6_PAD_NAND_DATA05__USDHC2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),\n+\tMX6_PAD_NAND_DATA06__USDHC2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),\n+\tMX6_PAD_NAND_DATA07__USDHC2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),\n+\tMX6_PAD_NAND_ALE__USDHC2_RESET_B | MUX_PAD_CTRL(USDHC_PAD_CTRL),\n+\tMX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),\n+\tMX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),\n+};\n+\n+static struct fsl_esdhc_cfg tqma6ul_usdhc2_cfg = {\n+\t.esdhc_base = USDHC2_BASE_ADDR,\n+\t.max_bus_width = 8,\n+};\n+\n+int board_mmc_getcd(struct mmc *mmc)\n+{\n+\tstruct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;\n+\tint ret = 0;\n+\n+\tif (cfg->esdhc_base == USDHC2_BASE_ADDR)\n+\t\t/* eMMC/uSDHC2 is always present */\n+\t\tret = 1;\n+\telse\n+\t\tret = tq_bb_board_mmc_getcd(mmc);\n+\n+\treturn ret;\n+}\n+\n+int board_mmc_getwp(struct mmc *mmc)\n+{\n+\tstruct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;\n+\tint ret = 0;\n+\n+\tif (cfg->esdhc_base == USDHC2_BASE_ADDR)\n+\t\t/* eMMC/uSDHC2 is never WP */\n+\t\tret = 0;\n+\telse\n+\t\tret = tq_bb_board_mmc_getwp(mmc);\n+\n+\treturn ret;\n+}\n+\n+int board_mmc_init(struct bd_info *bis)\n+{\n+\timx_iomux_v3_setup_multiple_pads(tqma6ul_usdhc2_pads,\n+\t\t\t\t\t ARRAY_SIZE(tqma6ul_usdhc2_pads));\n+\ttqma6ul_usdhc2_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);\n+\n+\tif (fsl_esdhc_initialize(bis, &tqma6ul_usdhc2_cfg))\n+\t\tprintf(\"Warning: failed to initialize eMMC dev\\n\");\n+\n+\ttq_bb_board_mmc_init(bis);\n+\n+\treturn 0;\n+}\n+\n+void board_init_f(ulong dummy)\n+{\n+\t/* setup clock gating */\n+\tccgr_init();\n+\n+\t/* setup AIPS and disable watchdog */\n+\tarch_cpu_init();\n+\n+\t/* setup AXI */\n+\tgpr_init();\n+\n+\t/* iomux and setup of i2c */\n+\tboard_early_init_f();\n+\n+\t/* Setup GP timer */\n+\ttimer_init();\n+\n+\t/* UART clocks enabled and gd valid - init serial console */\n+\tpreloader_console_init();\n+\n+\t/* DDR initialization */\n+\ttq_som_ram_init();\n+}\ndiff --git a/board/tq/tqma6ul/spl_mba6ul.c b/board/tq/tqma6ul/spl_mba6ul.c\nnew file mode 100644\nindex 00000000000..c6560e2e8b4\n--- /dev/null\n+++ b/board/tq/tqma6ul/spl_mba6ul.c\n@@ -0,0 +1,177 @@\n+// SPDX-License-Identifier: GPL-2.0-or-later\n+/*\n+ * Copyright (c) 2023-2026 TQ-Systems GmbH <u-boot@ew.tq-group.com>,\n+ * D-82229 Seefeld, Germany.\n+ * Author: Max Merchel\n+ */\n+\n+#include <fsl_esdhc_imx.h>\n+#include <malloc.h>\n+#include <spl.h>\n+#include <spl_gpio.h>\n+#include <asm/gpio.h>\n+#include <asm/arch/clock.h>\n+#include <asm/arch/imx-regs.h>\n+#include <asm/arch/mx6ul_pins.h>\n+#include <asm/mach-imx/sys_proto.h>\n+\n+#include \"../common/tq_bb.h\"\n+#include \"tqma6ul.h\"\n+\n+#define GPIO_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_LOW | \\\n+\t\t PAD_CTL_DSE_40ohm | PAD_CTL_HYS)\n+\n+#define USDHC_CLK_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \\\n+\t\t\t PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | \\\n+\t\t\t PAD_CTL_HYS)\n+\n+#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \\\n+\t\t\tPAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \\\n+\t\t\tPAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)\n+\n+#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \\\n+\t\t PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \\\n+\t\t PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)\n+\n+static const iomux_v3_cfg_t mba6ul_uart_pads[] = {\n+\tNEW_PAD_CTRL(MX6_PAD_UART1_TX_DATA__UART1_DCE_TX, UART_PAD_CTRL),\n+\tNEW_PAD_CTRL(MX6_PAD_UART1_RX_DATA__UART1_DCE_RX, UART_PAD_CTRL),\n+};\n+\n+static void mba6ul_setup_iomuxc_uart(void)\n+{\n+\timx_iomux_v3_setup_multiple_pads(mba6ul_uart_pads,\n+\t\t\t\t\t ARRAY_SIZE(mba6ul_uart_pads));\n+}\n+\n+/* SD card on USDHC1 */\n+static const iomux_v3_cfg_t mba6ul_usdhc1_pads[] = {\n+\tMX6_PAD_SD1_CLK__USDHC1_CLK |\tMUX_PAD_CTRL(USDHC_CLK_PAD_CTRL),\n+\tMX6_PAD_SD1_CMD__USDHC1_CMD |\tMUX_PAD_CTRL(USDHC_PAD_CTRL),\n+\tMX6_PAD_SD1_DATA0__USDHC1_DATA0 |\tMUX_PAD_CTRL(USDHC_PAD_CTRL),\n+\tMX6_PAD_SD1_DATA1__USDHC1_DATA1 |\tMUX_PAD_CTRL(USDHC_PAD_CTRL),\n+\tMX6_PAD_SD1_DATA2__USDHC1_DATA2 |\tMUX_PAD_CTRL(USDHC_PAD_CTRL),\n+\tMX6_PAD_SD1_DATA3__USDHC1_DATA3 |\tMUX_PAD_CTRL(USDHC_PAD_CTRL),\n+\t/* WP */\n+\tMX6_PAD_UART1_CTS_B__GPIO1_IO18 |\tMUX_PAD_CTRL(GPIO_PAD_CTRL),\n+\t/* CD */\n+\tMX6_PAD_UART1_RTS_B__GPIO1_IO19 |\tMUX_PAD_CTRL(GPIO_PAD_CTRL),\n+};\n+\n+#define USDHC1_CD_GPIO\tIMX_GPIO_NR(1, 19)\n+#define USDHC1_WP_GPIO\tIMX_GPIO_NR(1, 18)\n+\n+static struct fsl_esdhc_cfg mba6ul_usdhc1_cfg = {\n+\t.esdhc_base = USDHC1_BASE_ADDR,\n+\t.max_bus_width = 4,\n+};\n+\n+int tq_bb_board_mmc_getcd(struct mmc *mmc)\n+{\n+\tstruct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;\n+\tint ret = 0;\n+\n+\tif (cfg->esdhc_base == USDHC1_BASE_ADDR)\n+\t\tret = !gpio_get_value(USDHC1_CD_GPIO);\n+\n+\treturn ret;\n+}\n+\n+int tq_bb_board_mmc_getwp(struct mmc *mmc)\n+{\n+\tstruct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;\n+\tint ret = 0;\n+\n+\tif (cfg->esdhc_base == USDHC1_BASE_ADDR)\n+\t\tret = gpio_get_value(USDHC1_WP_GPIO);\n+\n+\treturn ret;\n+}\n+\n+int tq_bb_board_mmc_init(struct bd_info *bis)\n+{\n+\timx_iomux_v3_setup_multiple_pads(mba6ul_usdhc1_pads,\n+\t\t\t\t\t ARRAY_SIZE(mba6ul_usdhc1_pads));\n+\tgpio_request(USDHC1_CD_GPIO, \"usdhc1-cd\");\n+\tgpio_request(USDHC1_WP_GPIO, \"usdhc1-wp\");\n+\tgpio_direction_input(USDHC1_CD_GPIO);\n+\tgpio_direction_input(USDHC1_WP_GPIO);\n+\n+\tmba6ul_usdhc1_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);\n+\tif (fsl_esdhc_initialize(bis, &mba6ul_usdhc1_cfg))\n+\t\tputs(\"Warning: failed to initialize SD card\\n\");\n+\n+\treturn 0;\n+}\n+\n+int board_early_init_f(void)\n+{\n+\ttq_bb_board_early_init_f();\n+\n+\tmba6ul_setup_iomuxc_uart();\n+\n+\treturn 0;\n+}\n+\n+/*\n+ * This is done per baseboard to allow different implementations\n+ */\n+void board_boot_order(u32 *spl_boot_list)\n+{\n+\tu32 bmode = imx6_src_get_boot_mode();\n+\tu8 imx6_bmode = (bmode & IMX6_BMODE_MASK) >> IMX6_BMODE_SHIFT;\n+\n+\t/* USB boot */\n+\tif (spl_boot_device() == BOOT_DEVICE_BOARD) {\n+\t\tprintf(\"USB\\n\");\n+\t\tspl_boot_list[0] = BOOT_DEVICE_BOARD;\n+\t\treturn;\n+\t}\n+\n+\tswitch (imx6_bmode) {\n+\tcase IMX6_BMODE_SD:\n+\tcase IMX6_BMODE_ESD:\n+\t\t/* SD/eSD - BOOT_DEVICE_MMC2 */\n+\t\tprintf(\"SD\\n\");\n+\t\tspl_boot_list[0] = BOOT_DEVICE_MMC2;\n+\t\tbreak;\n+\tcase IMX6_BMODE_MMC:\n+\tcase IMX6_BMODE_EMMC:\n+\t\t/* MMC/eMMC - BOOT_DEVICE_MMC1 */\n+\t\tprintf(\"eMMC\\n\");\n+\t\tspl_boot_list[0] = BOOT_DEVICE_MMC1;\n+\t\tbreak;\n+\tcase IMX6_BMODE_QSPI:\n+\t\t/* QSPI - BOOT_DEVICE_SPI */\n+\t\tprintf(\"QSPI\\n\");\n+\t\tspl_boot_list[0] = BOOT_DEVICE_NOR;\n+\t\tbreak;\n+\tcase IMX6_BMODE_SERIAL_ROM:\n+\t\t/* SERIAL_ROM - BOOT_DEVICE_BOARD */\n+\t\tprintf(\"Serial ROM\\n\");\n+\t\tspl_boot_list[0] = BOOT_DEVICE_BOARD;\n+\t\tbreak;\n+\tdefault:\n+\t\tprintf(\"Wrong board boot order\\n\");\n+\t\tspl_boot_list[0] = BOOT_DEVICE_MMC1;\n+\t\tbreak;\n+\t}\n+}\n+\n+int board_fit_config_name_match(const char *name)\n+{\n+\t/* Longest FDT name */\n+\tchar dt[] = \"imx6ull-tqma6ull2l-mba6ulx\";\n+\tenum tqma6ul_som_type somtype;\n+\n+\tsomtype = set_tqma6ul_dt_name(dt, sizeof(dt), \"mba6ulx\");\n+\tif (somtype == tqma6ul_som_type_unknown)\n+\t\treturn -1;\n+\n+\tif (!strcmp(name, dt)) {\n+\t\tprintf(\"Device tree: %s\\n\", name);\n+\t\treturn 0;\n+\t}\n+\n+\treturn -1;\n+}\ndiff --git a/board/tq/tqma6ul/spl_tqma6ul_ram.c b/board/tq/tqma6ul/spl_tqma6ul_ram.c\nnew file mode 100644\nindex 00000000000..40284dd79a2\n--- /dev/null\n+++ b/board/tq/tqma6ul/spl_tqma6ul_ram.c\n@@ -0,0 +1,208 @@\n+// SPDX-License-Identifier: GPL-2.0-or-later\n+/*\n+ * Copyright (c) 2023-2026 TQ-Systems GmbH <u-boot@ew.tq-group.com>,\n+ * D-82229 Seefeld, Germany.\n+ * Author: Max Merchel\n+ */\n+\n+#include <config.h>\n+#include <hang.h>\n+#include <asm/arch/crm_regs.h>\n+#include <asm/arch/iomux.h>\n+#include <asm/arch/mx6-ddr.h>\n+#include <asm/arch/mx6ul-ddr.h>\n+#include <asm/arch/sys_proto.h>\n+\n+#include \"../common/tq_som.h\"\n+\n+static void tqma6ul_init_ddr_controller(u32 size)\n+{\n+\t/* TQMa6ul DDR config */\n+\n+\t/* reset DDR via Chip Select 0*/\n+\ttq_som_init_write_reg(MX6_MMDC_P0_MDCTL, 0x03180000);\n+\ttq_som_init_write_reg(MX6_MMDC_P0_MDCTL, 0x83180000);\n+\n+\tdebug(\"SPL: tqma6ul ddr iomux ....\\n\");\n+\n+\t/* DDR IO TYPE: */\n+\ttq_som_init_write_reg(MX6_IOM_GRP_DDR_TYPE, 0x000C0000);\n+\ttq_som_init_write_reg(MX6_IOM_GRP_DDRPKE, 0x00000000);\n+\t/* CLOCK: */\n+\ttq_som_init_write_reg(MX6_IOM_DRAM_SDCLK_0, 0x00000030);\n+\t/* Control: */\n+\ttq_som_init_write_reg(MX6_IOM_DRAM_CAS, 0x00000030);\n+\ttq_som_init_write_reg(MX6_IOM_DRAM_RAS, 0x00000030);\n+\ttq_som_init_write_reg(MX6_IOM_GRP_ADDDS, 0x00000030);\n+\ttq_som_init_write_reg(MX6_IOM_DRAM_RESET, 0x00000030);\n+\ttq_som_init_write_reg(MX6_IOM_DRAM_SDBA2, 0x00000000);\n+\ttq_som_init_write_reg(MX6_IOM_DRAM_SDODT0, 0x00000030);\n+\ttq_som_init_write_reg(MX6_IOM_DRAM_SDODT1, 0x00000030);\n+\ttq_som_init_write_reg(MX6_IOM_GRP_CTLDS, 0x00000030);\n+\t/* Data Strobes: */\n+\ttq_som_init_write_reg(MX6_IOM_DDRMODE_CTL, 0x00020000);\n+\ttq_som_init_write_reg(MX6_IOM_DRAM_SDQS0, 0x00000030);\n+\ttq_som_init_write_reg(MX6_IOM_DRAM_SDQS1, 0x00000030);\n+\t/* Data: */\n+\ttq_som_init_write_reg(MX6_IOM_GRP_DDRMODE, 0x00020000);\n+\ttq_som_init_write_reg(MX6_IOM_GRP_B0DS, 0x00000030);\n+\ttq_som_init_write_reg(MX6_IOM_GRP_B1DS, 0x00000030);\n+\ttq_som_init_write_reg(MX6_IOM_DRAM_DQM0, 0x00000030);\n+\ttq_som_init_write_reg(MX6_IOM_DRAM_DQM1, 0x00000030);\n+\n+\tdebug(\"tqma6ul ddr controller registers ....\\n\");\n+\n+\t/* MMDC_MDSCR - MMDC Core Special Command Register */\n+\ttq_som_init_write_reg(MX6_MMDC_P0_MDSCR, 0x00008000);\n+\n+\tdebug(\"tqma6ul ddr calibrations ....\\n\");\n+\n+\t/* DDR_PHY_P0_MPZQHWCTRL , enable both one-time & periodic HW ZQ calibration. */\n+\ttq_som_init_write_reg(MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003);\n+\n+\tswitch (size) {\n+\tcase SZ_512M:\n+\t\tif (IS_ENABLED(CONFIG_MX6UL)) {\n+\t\t\tdebug(\"tqma6ul ddr calibration standard variant ....\\n\");\n+\n+\t\t\ttq_som_init_write_reg(MX6_MMDC_P0_MPWLDECTRL0, 0x00000000);\n+\t\t\ttq_som_init_write_reg(MX6_MMDC_P0_MPDGCTRL0, 0x41580150);\n+\t\t\ttq_som_init_write_reg(MX6_MMDC_P0_MPRDDLCTL, 0x40404E52);\n+\t\t\ttq_som_init_write_reg(MX6_MMDC_P0_MPWRDLCTL, 0x40404E4A);\n+\n+\t\t} else if (IS_ENABLED(CONFIG_MX6ULL)) {\n+\t\t\tif (IS_ENABLED(CONFIG_TQMA6UL_VARIANT_STANDARD)) {\n+\t\t\t\tdebug(\"tqma6ull ddr calibration standard variant ....\\n\");\n+\n+\t\t\t\ttq_som_init_write_reg(MX6_MMDC_P0_MPWLDECTRL0, 0x00090009);\n+\t\t\t\ttq_som_init_write_reg(MX6_MMDC_P0_MPDGCTRL0, 0x4140013C);\n+\t\t\t\ttq_som_init_write_reg(MX6_MMDC_P0_MPRDDLCTL, 0x40403A3E);\n+\t\t\t\ttq_som_init_write_reg(MX6_MMDC_P0_MPWRDLCTL, 0x40402E26);\n+\n+\t\t\t} else if (IS_ENABLED(CONFIG_TQMA6UL_VARIANT_LGA)) {\n+\t\t\t\tdebug(\"tqma6ull ddr calibration lga variant ....\\n\");\n+\n+\t\t\t\ttq_som_init_write_reg(MX6_MMDC_P0_MPWLDECTRL0, 0x00050009);\n+\t\t\t\ttq_som_init_write_reg(MX6_MMDC_P0_MPDGCTRL0, 0x41340130);\n+\t\t\t\ttq_som_init_write_reg(MX6_MMDC_P0_MPRDDLCTL, 0x40403A3E);\n+\t\t\t\ttq_som_init_write_reg(MX6_MMDC_P0_MPWRDLCTL, 0x40402E28);\n+\n+\t\t\t} else {\n+\t\t\t\tpr_err(\"invalid/unsupported SoM variant ....\\n\");\n+\t\t\t\thang();\n+\t\t\t} /* IS_ENABLED(CONFIG_TQMA6UL_VARIANT_STANDARD) */\n+\t\t} else {\n+\t\t\tpr_err(\"ERROR: invalid/unsupported CPU variant ....\\n\");\n+\t\t\thang();\n+\t\t} /* IS_ENABLED(CONFIG_MX6UL) */\n+\t\tbreak;\n+\tcase SZ_256M:\n+\t\tif (IS_ENABLED(CONFIG_TQMA6UL_VARIANT_STANDARD)) {\n+\t\t\tdebug(\"tqma6ul ddr calibration standard variant ....\\n\");\n+\n+\t\t\ttq_som_init_write_reg(MX6_MMDC_P0_MPWLDECTRL0, 0x00000000);\n+\t\t\ttq_som_init_write_reg(MX6_MMDC_P0_MPDGCTRL0, 0x41480144);\n+\t\t\ttq_som_init_write_reg(MX6_MMDC_P0_MPRDDLCTL, 0x40404E54);\n+\t\t\ttq_som_init_write_reg(MX6_MMDC_P0_MPWRDLCTL, 0x40404E48);\n+\n+\t\t} else if (IS_ENABLED(CONFIG_TQMA6UL_VARIANT_LGA)) {\n+\t\t\tdebug(\"tqma6ul ddr calibration lga variant ....\\n\");\n+\n+\t\t\ttq_som_init_write_reg(MX6_MMDC_P0_MPWLDECTRL0, 0x00130003);\n+\t\t\ttq_som_init_write_reg(MX6_MMDC_P0_MPDGCTRL0, 0x41540154);\n+\t\t\ttq_som_init_write_reg(MX6_MMDC_P0_MPRDDLCTL, 0x40405050);\n+\t\t\ttq_som_init_write_reg(MX6_MMDC_P0_MPWRDLCTL, 0x40404E4C);\n+\n+\t\t} else {\n+\t\t\tpr_err(\"ERROR: invalid/unsupported SoM variant ....\\n\");\n+\t\t\thang();\n+\t\t} /* IS_ENABLED(CONFIG_TQMA6UL_VARIANT_STANDARD) */\n+\t\tbreak;\n+\tdefault:\n+\t\tpr_err(\"ERROR: invalid/unsupported RAM size ....\\n\");\n+\t\thang();\n+\t\tbreak;\n+\t}\n+\n+\ttq_som_init_write_reg(MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333);\n+\ttq_som_init_write_reg(MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333);\n+\n+\ttq_som_init_write_reg(0x021B082C, 0xf3333333); /* MMDC_MPWRDQBY0DL */\n+\ttq_som_init_write_reg(0x021B0830, 0xf3333333); /* MMDC_MPWRDQBY1DL */\n+\ttq_som_init_write_reg(0x021B08C0, 0x00921012); /* MMDC_MPDCCR */\n+\n+\t/*\n+\t * Complete calibration by forced measurement:\n+\t */\n+\ttq_som_init_write_reg(MX6_MMDC_P0_MPMUR0, 0x00000800);\n+\ttq_som_init_write_reg(MX6_MMDC_P0_MDPDC, 0x0002002D);\n+\n+\tdebug(\"tqma6ul ddr mmdc ....\\n\");\n+\n+\ttq_som_init_write_reg(MX6_MMDC_P0_MDOTC, 0x00333030);\n+\ttq_som_init_write_reg(MX6_MMDC_P0_MDCFG0, 0x676B52F3);\n+\ttq_som_init_write_reg(MX6_MMDC_P0_MDCFG1, 0xB66D8B63);\n+\ttq_som_init_write_reg(MX6_MMDC_P0_MDCFG2, 0x01FF00DB);\n+\ttq_som_init_write_reg(MX6_MMDC_P0_MDMISC, 0x00201740);\n+\ttq_som_init_write_reg(MX6_MMDC_P0_MDSCR, 0x00008000);\n+\ttq_som_init_write_reg(MX6_MMDC_P0_MDRWD, 0x000026D2);\n+\ttq_som_init_write_reg(MX6_MMDC_P0_MDOR, 0x006B1023);\n+\n+\tswitch (size) {\n+\tcase SZ_512M:\n+\t\ttq_som_init_write_reg(MX6_MMDC_P0_MDASP, 0x0000004F);\n+\t\ttq_som_init_write_reg(MX6_MMDC_P0_MDCTL, 0x84180000);\n+\t\tbreak;\n+\tcase SZ_256M:\n+\t\ttq_som_init_write_reg(MX6_MMDC_P0_MDASP, 0x00000047);\n+\t\ttq_som_init_write_reg(MX6_MMDC_P0_MDCTL, 0x83180000);\n+\t\tbreak;\n+\tdefault:\n+\t\thang();\n+\t\tbreak;\n+\t}\n+\n+\tdebug(\"tqma6ul ddr cs0 ....\\n\");\n+\ttq_som_init_write_reg(MX6_MMDC_P0_MDSCR, 0x02008032);\n+\ttq_som_init_write_reg(MX6_MMDC_P0_MDSCR, 0x00008033);\n+\ttq_som_init_write_reg(MX6_MMDC_P0_MDSCR, 0x00048031);\n+\ttq_som_init_write_reg(MX6_MMDC_P0_MDSCR, 0x15208030);\n+\ttq_som_init_write_reg(MX6_MMDC_P0_MDSCR, 0x04008040);\n+\ttq_som_init_write_reg(MX6_MMDC_P0_MDREF, 0x00000800);\n+\ttq_som_init_write_reg(MX6_MMDC_P0_MPODTCTRL, 0x00000227);\n+\ttq_som_init_write_reg(MX6_MMDC_P0_MDPDC, 0x0002552D);\n+\ttq_som_init_write_reg(MX6_MMDC_P0_MAPSR, 0x00011006);\n+\ttq_som_init_write_reg(MX6_MMDC_P0_MDSCR, 0x00000000);\n+}\n+\n+void tq_som_ram_init(void)\n+{\n+\tint i;\n+\t/* RAM sizes need to be in descending order */\n+\tstatic const u32 ram_sizes[] = {\n+#if IS_ENABLED(CONFIG_TQMA6UL_RAM_512M)\n+\t\tSZ_512M,\n+#endif\n+#if IS_ENABLED(CONFIG_TQMA6UL_RAM_256M)\n+\t\tSZ_256M,\n+#endif\n+\t};\n+\n+\tif (!is_mx6ul() && !is_mx6ull()) {\n+\t\tpr_err(\"ERROR: Not running on TQMa6UL[L]\\n\");\n+\t\thang();\n+\t}\n+\n+\tfor (i = 0; i < ARRAY_SIZE(ram_sizes); i++) {\n+\t\ttqma6ul_init_ddr_controller(ram_sizes[i]);\n+\t\tif (tq_som_ram_check_size(ram_sizes[i]))\n+\t\t\tbreak;\n+\t}\n+\n+\tif (i < ARRAY_SIZE(ram_sizes)) {\n+\t\tdebug(\"tqma6ul ddr init done ...\\n\");\n+\t} else {\n+\t\tpr_err(\"ERROR: Invalid DDR RAM size detected\\n\");\n+\t\thang();\n+\t}\n+}\ndiff --git a/board/tq/tqma6ul/tqma6ul.c b/board/tq/tqma6ul/tqma6ul.c\nnew file mode 100644\nindex 00000000000..999396f573d\n--- /dev/null\n+++ b/board/tq/tqma6ul/tqma6ul.c\n@@ -0,0 +1,184 @@\n+// SPDX-License-Identifier: GPL-2.0-or-later\n+/*\n+ * Copyright (c) 2016-2026 TQ-Systems GmbH <u-boot@ew.tq-group.com>,\n+ * D-82229 Seefeld, Germany.\n+ * Author: Marco Felsch, Nora Schiffer\n+ *\n+ */\n+\n+#include <env.h>\n+#include <fdt_support.h>\n+#include <mmc.h>\n+#include <mtd_node.h>\n+#include <spi_flash.h>\n+#include <asm/arch/clock.h>\n+#include <asm/arch/sys_proto.h>\n+#include <asm/mach-imx/boot_mode.h>\n+\n+#include \"../common/tq_bb.h\"\n+#include \"tqma6ul.h\"\n+\n+int tq_bb_board_early_init_f(void)\n+{\n+\tif (CONFIG_IS_ENABLED(FSL_QSPI))\n+\t\tenable_qspi_clk(0);\n+\n+\treturn 0;\n+}\n+\n+/**\n+ * Checks if CPU (imx6ul or ima6ull) matches the one set for the image.\n+ */\n+static const char *check_cpu_variant(void)\n+{\n+\tconst char *cpu;\n+\n+\tif (is_mx6ul()) {\n+\t\tcpu = \"ul\";\n+\t\tif (!IS_ENABLED(CONFIG_MX6UL))\n+\t\t\tprintf(\"*** ERROR: image not compiled for i.MX6UL!\\n\");\n+\t} else if (is_mx6ull()) {\n+\t\tcpu = \"ull\";\n+\t\tif (!IS_ENABLED(CONFIG_MX6ULL))\n+\t\t\tprintf(\"*** ERROR: image not compiled for i.MX6ULL!\\n\");\n+\t} else {\n+\t\tprintf(\"unknown CPU\\n\");\n+\t\treturn NULL;\n+\t}\n+\n+\treturn cpu;\n+}\n+\n+/**\n+ * Checks configuration for TQMa6UL SoM module variant.\n+ */\n+enum tqma6ul_som_type check_tqma6ul_variant(void)\n+{\n+\tif (IS_ENABLED(CONFIG_TQMA6UL_VARIANT_STANDARD))\n+\t\treturn tqma6ul_som_type_ca;\n+\n+\tif (IS_ENABLED(CONFIG_TQMA6UL_VARIANT_LGA))\n+\t\treturn tqma6ul_som_type_lga;\n+\n+\tprintf(\"unknown SoM variant\\n\");\n+\n+\treturn tqma6ul_som_type_unknown;\n+}\n+\n+/**\n+ * Adjusts device tree name based on CPU variant.\n+ */\n+enum tqma6ul_som_type set_tqma6ul_dt_name(char *dt, size_t dtsize, const char *mb)\n+{\n+\tconst char *tqma6ul_cpu, *tqma6ul_variant;\n+\tenum tqma6ul_som_type somtype;\n+\tu8 mx6ul_variant;\n+\n+\ttqma6ul_cpu = check_cpu_variant();\n+\tif (!tqma6ul_cpu)\n+\t\treturn tqma6ul_som_type_unknown;\n+\n+\t/* MX6UL1 vs MX6UL2 */\n+\tmx6ul_variant = check_module_fused(MODULE_ENET2) ? 1 : 2;\n+\n+\tsomtype = check_tqma6ul_variant();\n+\tswitch (somtype) {\n+\tcase tqma6ul_som_type_ca:\n+\t\ttqma6ul_variant = \"\";\n+\t\tbreak;\n+\tcase tqma6ul_som_type_lga:\n+\t\ttqma6ul_variant = \"l\";\n+\t\tbreak;\n+\tdefault:\n+\t\treturn tqma6ul_som_type_unknown;\n+\t}\n+\n+\tsnprintf(dt, dtsize, \"imx6%s-tqma6%s%u%s-%s\",\n+\t\t tqma6ul_cpu, tqma6ul_cpu, mx6ul_variant, tqma6ul_variant, mb);\n+\n+\treturn somtype;\n+}\n+\n+#if !IS_ENABLED(CONFIG_SPL_BUILD)\n+int dram_init(void)\n+{\n+\tgd->ram_size = imx_ddr_size();\n+\n+\treturn 0;\n+}\n+\n+const char *tq_som_get_modulename(void)\n+{\n+\tif (is_mx6ul()) {\n+\t\tif (IS_ENABLED(CONFIG_TQMA6UL_VARIANT_STANDARD))\n+\t\t\treturn \"TQMa6ULx\";\n+\n+\t\tif (IS_ENABLED(CONFIG_TQMA6UL_VARIANT_LGA))\n+\t\t\treturn \"TQMa6ULxL\";\n+\t}\n+\n+\tif (is_mx6ull()) {\n+\t\tif (IS_ENABLED(CONFIG_TQMA6UL_VARIANT_STANDARD))\n+\t\t\treturn \"TQMa6ULLx\";\n+\n+\t\tif (IS_ENABLED(CONFIG_TQMA6UL_VARIANT_LGA))\n+\t\t\treturn \"TQMa6ULLxL\";\n+\t}\n+\n+\treturn \"Unknown\";\n+}\n+\n+int checkboard(void)\n+{\n+\tprintf(\"Board: %s on %s\\n\", tq_som_get_modulename(),\n+\t tq_bb_get_boardname());\n+\n+\treturn tq_bb_checkboard();\n+}\n+\n+#if IS_ENABLED(CONFIG_CMD_BMODE)\n+static const struct boot_mode tqma6ul_board_boot_modes[] = {\n+\t/* 4 bit bus width */\n+\t{\"sd\", MAKE_CFGVAL(0x42, 0x20, 0x00, 0x00)},\n+\t{\"emmc\", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},\n+\t{\"qspi\", MAKE_CFGVAL(0x10, 0x00, 0x00, 0x00)},\n+\t{NULL, 0},\n+};\n+#endif\n+\n+int tq_bb_board_late_init(void)\n+{\n+\tif (IS_ENABLED(CONFIG_CMD_BMODE))\n+\t\tadd_board_boot_modes(tqma6ul_board_boot_modes);\n+\n+\tenv_set_runtime(\"board_name\", tq_som_get_modulename());\n+\n+\treturn 0;\n+}\n+\n+int tq_bb_checkboard(void)\n+{\n+\tif (is_mx6ul()) {\n+\t\tif (!IS_ENABLED(CONFIG_MX6UL))\n+\t\t\tprintf(\"*** ERROR: image not compiled for i.MX6UL!\\n\");\n+\t} else if (is_mx6ull()) {\n+\t\tif (!IS_ENABLED(CONFIG_MX6ULL))\n+\t\t\tprintf(\"*** ERROR: image not compiled for i.MX6ULL!\\n\");\n+\t} else {\n+\t\tprintf(\"*** ERROR: unknown CPU variant!\\n\");\n+\t}\n+\n+\treturn 0;\n+}\n+\n+/*\n+ * Device Tree Support\n+ */\n+#if IS_ENABLED(CONFIG_OF_BOARD_SETUP) && IS_ENABLED(CONFIG_OF_LIBFDT)\n+int tq_bb_ft_board_setup(void *blob, struct bd_info *bd)\n+{\n+\treturn 0;\n+}\n+#endif /* IS_ENABLED(CONFIG_OF_BOARD_SETUP) && IS_ENABLED(CONFIG_OF_LIBFDT) */\n+\n+#endif /* !IS_ENABLED(CONFIG_SPL_BUILD) */\ndiff --git a/board/tq/tqma6ul/tqma6ul.cfg b/board/tq/tqma6ul/tqma6ul.cfg\nnew file mode 100644\nindex 00000000000..42821ae5c7a\n--- /dev/null\n+++ b/board/tq/tqma6ul/tqma6ul.cfg\n@@ -0,0 +1,23 @@\n+// SPDX-License-Identifier: GPL-2.0-or-later\n+/*\n+ * Copyright (c) 2024-2026 TQ-Systems GmbH <u-boot@ew.tq-group.com>,\n+ * D-82229 Seefeld, Germany.\n+ * Author: Max Merchel\n+ *\n+ */\n+\n+#include <config.h>\n+\n+/* image version */\n+\n+IMAGE_VERSION 2\n+\n+#if IS_ENABLED(CONFIG_QSPI_BOOT)\n+BOOT_FROM\tqspi\n+#else\n+BOOT_FROM\tsd\n+#endif\n+\n+#if IS_ENABLED(CONFIG_IMX_HAB)\n+CSF CONFIG_CSF_SIZE\n+#endif\ndiff --git a/board/tq/tqma6ul/tqma6ul.env b/board/tq/tqma6ul/tqma6ul.env\nnew file mode 100644\nindex 00000000000..12281c8a3a4\n--- /dev/null\n+++ b/board/tq/tqma6ul/tqma6ul.env\n@@ -0,0 +1,47 @@\n+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n+/*\n+ * Copyright (c) 2016-2026 TQ-Systems GmbH <u-boot@ew.tq-group.com>,\n+ * D-82229 Seefeld, Germany.\n+ * Author: Max Merchel\n+ *\n+ * TQMa6UL environment\n+ */\n+\n+#include <env/tq/tq-imx-shared.env>\n+\n+emmc_dev=0\n+sd_dev=1\n+board=tqma6ul\n+boot_os=bootz \"${kernel_addr_r}\" - \"${fdt_addr_r}\"\n+emmc_bootp_start=TQMA6UL_MMC_UBOOT_SECTOR_START\n+fdt_addr_r=TQMA6UL_FDT_ADDRESS\n+fdtoverlay_addr_r=TQMA6UL_FDT_OVERLAY_ADDR\n+image=zImage\n+kernel_addr_r=CONFIG_SYS_LOAD_ADDR\n+pxefile_addr_r=CONFIG_SYS_LOAD_ADDR\n+ramdisk_addr_r=TQMA6UL_INITRD_ADDRESS\n+mmcautodetect=yes\n+mmcblkdev=0\n+mmcdev=CONFIG_ENV_MMC_DEVICE_INDEX\n+netdev=eth1\n+uboot=u-boot-with-spl.imx\n+uboot_mmc_start=TQMA6UL_MMC_UBOOT_SECTOR_START\n+uboot_mmc_size=TQMA6UL_MMC_UBOOT_SECTOR_COUNT\n+uboot_spi_sector_size=TQMA6UL_SPI_FLASH_SECTOR_SIZE\n+uboot_spi_start=TQMA6UL_SPI_UBOOT_START\n+uboot_spi_size=TQMA6UL_SPI_UBOOT_SIZE\n+\n+#ifdef CONFIG_USB_FUNCTION_FASTBOOT\n+\n+/* 0=user 1=boot1 2=boot2 */\n+fastboot_mmc_boot_partition = 1\n+\n+fastboot_partition_alias_all=CONFIG_FASTBOOT_FLASH_MMC_DEV :0\n+\n+fastboot_raw_partition_bootloader=\n+\tTQMA6UL_MMC_UBOOT_SECTOR_START TQMA6UL_MMC_UBOOT_SECTOR_COUNT mmcpart\n+\t\"${fastboot_mmc_boot_partition}\"\n+\n+fastbootcmd=fastboot usb 0\n+\n+#endif /* CONFIG_USB_FUNCTION_FASTBOOT */\ndiff --git a/board/tq/tqma6ul/tqma6ul.h b/board/tq/tqma6ul/tqma6ul.h\nnew file mode 100644\nindex 00000000000..595edc89e19\n--- /dev/null\n+++ b/board/tq/tqma6ul/tqma6ul.h\n@@ -0,0 +1,25 @@\n+/* SPDX-License-Identifier: GPL-2.0-or-later */\n+/*\n+ * Copyright (c) 2023-2026 TQ-Systems GmbH <u-boot@ew.tq-group.com>,\n+ * D-82229 Seefeld, Germany.\n+ * Author: Max Merchel\n+ */\n+\n+enum tqma6ul_som_type {\n+\t/* unknown */\n+\ttqma6ul_som_type_unknown,\n+\t/* connector module */\n+\ttqma6ul_som_type_ca,\n+\t/* LGA Variant */\n+\ttqma6ul_som_type_lga,\n+};\n+\n+/**\n+ * Checks configuration for TQMa6UL SoM module variant\n+ */\n+enum tqma6ul_som_type check_tqma6ul_variant(void);\n+\n+/**\n+ * Adjusts device tree name based on CPU variant.\n+ */\n+enum tqma6ul_som_type set_tqma6ul_dt_name(char *dt, size_t dtsize, const char *mb);\ndiff --git a/board/tq/tqma6ul/tqma6ul_mba6ul.c b/board/tq/tqma6ul/tqma6ul_mba6ul.c\nnew file mode 100644\nindex 00000000000..be78060cbda\n--- /dev/null\n+++ b/board/tq/tqma6ul/tqma6ul_mba6ul.c\n@@ -0,0 +1,138 @@\n+// SPDX-License-Identifier: GPL-2.0-or-later\n+/*\n+ * Copyright (c) 2016-2026 TQ-Systems GmbH <u-boot@ew.tq-group.com>,\n+ * D-82229 Seefeld, Germany.\n+ * Author: Marco Felsch, Nora Schiffer\n+ */\n+\n+#include <env.h>\n+#include <malloc.h>\n+#include <asm/arch/clock.h>\n+#include <asm/arch/iomux.h>\n+#include <asm/arch/mx6-pins.h>\n+#include <asm/mach-imx/sys_proto.h>\n+\n+#include \"../common/tq_bb.h\"\n+#include \"tqma6ul.h\"\n+\n+const char *tq_bb_get_boardname(void)\n+{\n+\treturn \"MBa6ULx\";\n+}\n+\n+int board_early_init_f(void)\n+{\n+\treturn tq_bb_board_early_init_f();\n+}\n+\n+static void mba6ul_setup_eth(void)\n+{\n+\tstruct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;\n+\n+\tif (check_module_fused(MODULE_ENET1)) {\n+\t\tprintf(\"FEC1: disabled by fuses\\n\");\n+\t} else {\n+\t\t/*\n+\t\t * Use 50M anatop loopback REF_CLK1 for ENET1,\n+\t\t * clear gpr1[13], set gpr1[17]\n+\t\t */\n+\t\tclrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK,\n+\t\t\t\tIOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK);\n+\n+\t\tenable_fec_anatop_clock(0, ENET_50MHZ);\n+\t}\n+\n+\tif (check_module_fused(MODULE_ENET2)) {\n+\t\tprintf(\"FEC2: disabled by fuses\\n\");\n+\t} else {\n+\t\t/*\n+\t\t * Use 50M anatop loopback REF_CLK1 for ENET2,\n+\t\t * clear gpr1[14], set gpr1[18]\n+\t\t */\n+\t\tclrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK,\n+\t\t\t\tIOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK);\n+\n+\t\tenable_fec_anatop_clock(1, ENET_50MHZ);\n+\t}\n+\n+\tenable_enet_clk(1);\n+}\n+\n+int board_init(void)\n+{\n+\treturn 0;\n+}\n+\n+static void mba6ul_set_fdt_file(void)\n+{\n+\t/* Longest FDT name */\n+\tchar dt[] = \"imx6ull-tqma6ull2l-mba6ulx.dtb\";\n+\tenum tqma6ul_som_type somtype;\n+\n+\tif (!env_get(\"fdtfile\")) {\n+\t\tsomtype = set_tqma6ul_dt_name(dt, sizeof(dt), \"mba6ulx.dtb\");\n+\t\tif (somtype == tqma6ul_som_type_unknown)\n+\t\t\treturn;\n+\n+\t\tenv_set_runtime(\"fdtfile\", dt);\n+\t}\n+}\n+\n+int board_late_init(void)\n+{\n+\tunsigned int bmode =\n+\t\t(imx6_src_get_boot_mode() & IMX6_BMODE_MASK) >> IMX6_BMODE_SHIFT;\n+\n+\ttq_bb_board_late_init();\n+\n+\tprintf(\"Boot: \");\n+\n+\tswitch (bmode) {\n+\tcase IMX6_BMODE_MMC:\n+\tcase IMX6_BMODE_EMMC:\n+\t\tprintf(\"eMMC\\n\");\n+\t\tenv_set_runtime(\"boot_dev\", \"mmc\");\n+\t\tboard_late_mmc_env_init();\n+\t\tbreak;\n+\tcase IMX6_BMODE_SD:\n+\tcase IMX6_BMODE_ESD:\n+\t\tprintf(\"SD\\n\");\n+\t\tenv_set_runtime(\"boot_dev\", \"mmc\");\n+\t\tboard_late_mmc_env_init();\n+\t\tbreak;\n+\tcase IMX6_BMODE_QSPI:\n+\tcase IMX6_BMODE_NOR:\n+\t\tprintf(\"QSPI\\n\");\n+\t\tenv_set_runtime(\"boot_dev\", \"qspi\");\n+\t\tbreak;\n+\tdefault:\n+\t\tprintf(\"unhandled boot device %u\\n\", bmode);\n+\t}\n+\n+\tmba6ul_set_fdt_file();\n+\tmba6ul_setup_eth();\n+\n+\treturn 0;\n+}\n+\n+int board_mmc_get_env_dev(int devno)\n+{\n+\tunsigned int port = (imx6_src_get_boot_mode() >> 11) & 0x3;\n+\n+\tswitch (port) {\n+\tcase 0:\n+\t\t/* SDHC1 - SD card on MBa6ULx */\n+\t\treturn 1;\n+\n+\tdefault:\n+\t\t/* Return eMMC device otherwise */\n+\t\treturn 0;\n+\t}\n+}\n+\n+#if IS_ENABLED(CONFIG_OF_BOARD_SETUP) && IS_ENABLED(CONFIG_OF_LIBFDT)\n+int ft_board_setup(void *blob, struct bd_info *bd)\n+{\n+\treturn tq_bb_ft_board_setup(blob, bd);\n+}\n+#endif /* IS_ENABLED(CONFIG_OF_BOARD_SETUP) && IS_ENABLED(CONFIG_OF_LIBFDT) */\ndiff --git a/doc/board/tq/index.rst b/doc/board/tq/index.rst\nindex d6dc6101c2c..775957474e7 100644\n--- a/doc/board/tq/index.rst\n+++ b/doc/board/tq/index.rst\n@@ -9,4 +9,5 @@ TQ-Systems\n .. toctree::\n :maxdepth: 2\n \n+ tqma6ul\n tqma7\ndiff --git a/doc/board/tq/tqma6ul.rst b/doc/board/tq/tqma6ul.rst\nnew file mode 100644\nindex 00000000000..2b346715642\n--- /dev/null\n+++ b/doc/board/tq/tqma6ul.rst\n@@ -0,0 +1,105 @@\n+.. SPDX-License-Identifier: GPL-2.0-or-later or CC-BY-4.0\n+\n+.. Copyright (c) 2017-2025 TQ-Systems GmbH <u-boot@ew.tq-group.com>,\n+.. D-82229 Seefeld, Germany.\n+\n+########################################\n+U-Boot for the TQ-Systems TQMa6x modules\n+########################################\n+\n+The following hardware revisions are supported:\n+\n+Modules:\n+\n++------------+----------+\n+| TQMa6ULx | REV.030x |\n++------------+----------+\n+| TQMa6ULLx | REV.030x |\n++------------+----------+\n+| TQMa6ULxL | REV.030x |\n++------------+----------+\n+| TQMa6ULLxL | REV.030x |\n++------------+----------+\n+\n+Mainboards:\n+\n++----------+----------+\n+| MBa6ULx | REV.020x |\n++----------+----------+\n+\n+Hardware on modules TQMa6ULx, TQMa6ULxL, TQMa6ULLx and TQMa6ULLxL\n+\n+- eMMC\n+- RTC\n+- PMIC\n+- SPI-NOR (optional)\n+- EEPROM\n+- Temperature sensor\n+- RAM (256 MiB / 512 MiB)\n+\n+Supported hardware on Starterkit MBa6ULx:\n+\n+- 2 Ethernet PHY connected to FEC0 / FEC1 (usage depends on CPU)\n+- SD-card slot\n+- UART\n+- USB\n+\n+Note: To change the Ethernet port to use for networking functionality, use the\n+U-Boot generic environment variable ``ethact``.\n+\n+.. code-block:: bash\n+\n+ setenv ethact <FEC>\n+\n+***********\n+Boot source\n+***********\n+\n+- SD/eMMC\n+- USB/SDP (with NXP UUU tool)\n+- SPI NOR (functional but requires additional prepended NXP header.\n+ Not supported in U-Boot.)\n+\n+********\n+Building\n+********\n+\n+To build U-Boot for the TQ-Systems TQMa6L modules:\n+\n+.. code-block:: bash\n+\n+\tmake <som>_<baseboard>_<boot>_defconfig\n+\tmake\n+\n+\n+**som** is a placeholder for the module base variant:\n+\n++------------+------------+----------------+\n+| tqma6ulx | TQMa6ULx | i.MX6UL |\n++------------+------------+----------------+\n+| tqma6ullx | TQMa6ULLx | i.MX6ULL |\n++------------+------------+----------------+\n+| tqma6ulxl | TQMa6ULxL | i.MX6UL (lga) |\n++------------+------------+----------------+\n+| tqma6ullxl | TQMa6ULLxL | i.MX6ULL (lga) |\n++------------+------------+----------------+\n+\n+**baseboard** is a placeholder for the mainboard to compile for:\n+\n++----------+----------+\n+| mba6ul | MBa6ULx |\n++----------+----------+\n+\n+**boot** is a placeholder for the boot device:\n+\n++------+---------+\n+| mmc | SD/eMMC |\n++------+---------+\n+| spi | SPI-NOR |\n++------+---------+\n+\n+************\n+Support Wiki\n+************\n+\n+See `TQ Embedded Wiki for TQMa6ulx <https://support.tq-group.com/en/arm/tqma6ulx>`_.\ndiff --git a/include/configs/tqma6ul.h b/include/configs/tqma6ul.h\nnew file mode 100644\nindex 00000000000..dce3816d0b7\n--- /dev/null\n+++ b/include/configs/tqma6ul.h\n@@ -0,0 +1,46 @@\n+/* SPDX-License-Identifier: GPL-2.0-or-later */\n+/*\n+ * Copyright (c) 2016-2026 TQ-Systems GmbH <u-boot@ew.tq-group.com>,\n+ * D-82229 Seefeld, Germany.\n+ * Author: Marco Felsch, Nora Schiffer\n+ *\n+ * Configuration settings for the TQ-Systems TQMa6UL[L]x[L] SOM family.\n+ */\n+\n+#ifndef __TQMA6UL_CONFIG_H\n+#define __TQMA6UL_CONFIG_H\n+\n+#include \"mx6_common.h\"\n+\n+/* 128 MiB offset as suggested in ARM related Linux docs */\n+#define TQMA6UL_FDT_ADDRESS\t\t0x88000000\n+\n+/* 256KiB above TQMA6UL_FDT_ADDRESS (TQMA6UL_FDT_ADDRESS + SZ_256K) */\n+#define TQMA6UL_FDT_OVERLAY_ADDR\t0x88040000\n+\n+/* 16MiB above TQMA6UL_FDT_ADDRESS (TQMA6UL_FDT_ADDRESS + SZ_16M) */\n+#define TQMA6UL_INITRD_ADDRESS\t\t0x89000000\n+\n+/* Physical Memory Map */\n+#define PHYS_SDRAM\t\t\tMMDC0_ARB_BASE_ADDR\n+\n+#define CFG_SYS_SDRAM_BASE\t\tPHYS_SDRAM\n+#define CFG_SYS_INIT_RAM_ADDR\t\tIRAM_BASE_ADDR\n+#define CFG_SYS_INIT_RAM_SIZE\t\tIRAM_SIZE\n+\n+/* u-boot.img base address for SPI-NOR boot */\n+#define CFG_SYS_UBOOT_BASE\t(QSPI0_AMBA_BASE + 0x1000 + CONFIG_SPL_PAD_TO)\n+\n+#define CFG_SYS_INIT_SP_OFFSET \\\n+\t(CFG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)\n+#define CFG_SYS_INIT_SP_ADDR \\\n+\t(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_SP_OFFSET)\n+\n+#define TQMA6UL_MMC_UBOOT_SECTOR_START\t0x2\n+#define TQMA6UL_MMC_UBOOT_SECTOR_COUNT\t0x7fe\n+\n+#define TQMA6UL_SPI_FLASH_SECTOR_SIZE\tSZ_64K\n+#define TQMA6UL_SPI_UBOOT_START\t\t0x1000\n+#define TQMA6UL_SPI_UBOOT_SIZE\t\t0xf0000\n+\n+#endif /* __TQMA6UL_CONFIG_H */\ndiff --git a/include/configs/tqma6ul_mba6ul.h b/include/configs/tqma6ul_mba6ul.h\nnew file mode 100644\nindex 00000000000..76e0553c68d\n--- /dev/null\n+++ b/include/configs/tqma6ul_mba6ul.h\n@@ -0,0 +1,19 @@\n+/* SPDX-License-Identifier: GPL-2.0-or-later */\n+/*\n+ * Copyright (c) 2016-2026 TQ-Systems GmbH <u-boot@ew.tq-group.com>,\n+ * D-82229 Seefeld, Germany.\n+ * Author: Markus Niebel, Nora Schiffer\n+ *\n+ * Configuration settings for the TQ-Systems MBa6ULx carrier board for\n+ * TQMa6UL[L]x[L] SOM family.\n+ */\n+\n+#ifndef __CONFIG_TQMA6UL_MBA6UL_H\n+#define __CONFIG_TQMA6UL_MBA6UL_H\n+\n+#include \"tqma6ul.h\"\n+\n+#define CFG_MXC_UART_BASE\t\tUART1_BASE\n+#define CFG_SYS_FSL_ESDHC_ADDR\t\t0\n+\n+#endif /* __CONFIG_TQMA6UL_MBA6UL_H */\n", "prefixes": [ "4/5" ] }