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GET /api/1.2/patches/2234857/?format=api
{ "id": 2234857, "url": "http://patchwork.ozlabs.org/api/1.2/patches/2234857/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260508064053.37529-7-fengchengwen@huawei.com/", "project": { "id": 28, "url": "http://patchwork.ozlabs.org/api/1.2/projects/28/?format=api", "name": "Linux PCI development", "link_name": "linux-pci", "list_id": "linux-pci.vger.kernel.org", "list_email": "linux-pci@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260508064053.37529-7-fengchengwen@huawei.com>", "list_archive_url": null, "date": "2026-05-08T06:40:52", "name": "[v8,6/7] vfio/pci: Add PCIe TPH GET_ST interface", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "1e52fe521b7d59f2a8cb59353c666f44dc08c0dc", "submitter": { "id": 92756, "url": "http://patchwork.ozlabs.org/api/1.2/people/92756/?format=api", "name": "fengchengwen", "email": "fengchengwen@huawei.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260508064053.37529-7-fengchengwen@huawei.com/mbox/", "series": [ { "id": 503332, "url": "http://patchwork.ozlabs.org/api/1.2/series/503332/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/list/?series=503332", "date": "2026-05-08T06:40:48", "name": "vfio/pci: Add PCIe TPH support", "version": 8, "mbox": "http://patchwork.ozlabs.org/series/503332/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2234857/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2234857/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-pci+bounces-54234-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-pci@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=huawei.com header.i=@huawei.com header.a=rsa-sha256\n header.s=dkim header.b=GBoMvK3a;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c0a:e001:db::12fc:5321; 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Fri, 8 May 2026 14:41:02 +0800" ], "ARC-Seal": "i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116;\n\tt=1778222481; cv=none;\n b=FR877RHW6aAVksjFLlJlX+oRErPsYD3N1HQvN+wvpQew7jCqvoiH06bnFjDOCW3mUyIIXmR3tWc0FEQUSjaLDGE8dUA4u2LqGODjB8TDNwGwaCawZkEfs7F6VefCP7p6ttmACT3gpRBbNl3sYXY1CAwsAB2NAs3KWRYLvzjjzP8=", "ARC-Message-Signature": "i=1; a=rsa-sha256; d=subspace.kernel.org;\n\ts=arc-20240116; t=1778222481; c=relaxed/simple;\n\tbh=j4cHPBKtXYs54un//PYC2+Gxn+fyCLRJFo230/dYNLg=;\n\th=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References:\n\t MIME-Version:Content-Type;\n b=gMQWXYe8lj31xutaWo7KFkha0TGiA7zizu1Ts/c8yDe6aiMwxbcxUaAgIaHO6buV3uSnkOu/G/C12YjHEgeATH/3yAmImN8kMplfzBr9SgzBuO9f/zrHodRLunswvvlgHlBFr3w2ubcYTCkrX/K+tSJ+vxDNFxPHAcMPYHJkFRc=", "ARC-Authentication-Results": "i=1; smtp.subspace.kernel.org;\n dmarc=pass (p=quarantine dis=none) header.from=huawei.com;\n spf=pass smtp.mailfrom=huawei.com;\n dkim=pass (1024-bit key) header.d=huawei.com header.i=@huawei.com\n header.b=GBoMvK3a; arc=none smtp.client-ip=113.46.200.224", "dkim-signature": "v=1; a=rsa-sha256; d=huawei.com; s=dkim;\n\tc=relaxed/relaxed; q=dns/txt;\n\th=From;\n\tbh=IIuHlm7qBrJL/uqB9uceN+lcTcvXUlghQgn++6PXji0=;\n\tb=GBoMvK3ab6tcwwx/EtXEfkzlVLQVvAdi4pHDHvvLu+ydK0XN0iQuu78fEn+AdAU4BjTBOZqIv\n\tC9bSdhItejnSt1huSNNYPngtoHugOdyPSR3/dIBjkAufLXaCdcAhtg1Rr8KjadfYcgZSStIUVtS\n\taCEdn2MeO+W85Mq5QBjpNaw=", "From": "Chengwen Feng <fengchengwen@huawei.com>", "To": "<alex@shazbot.org>, <jgg@ziepe.ca>", "CC": "<wathsala.vithanage@arm.com>, <helgaas@kernel.org>, <wei.huang2@amd.com>,\n\t<wangzhou1@hisilicon.com>, <wangyushan12@huawei.com>,\n\t<liuyonglong@huawei.com>, <kvm@vger.kernel.org>, <linux-pci@vger.kernel.org>", "Subject": "[PATCH v8 6/7] vfio/pci: Add PCIe TPH GET_ST interface", "Date": "Fri, 8 May 2026 14:40:52 +0800", "Message-ID": "<20260508064053.37529-7-fengchengwen@huawei.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20260508064053.37529-1-fengchengwen@huawei.com>", "References": "<20260508064053.37529-1-fengchengwen@huawei.com>", "Precedence": "bulk", "X-Mailing-List": "linux-pci@vger.kernel.org", "List-Id": "<linux-pci.vger.kernel.org>", "List-Subscribe": "<mailto:linux-pci+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-pci+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-ClientProxiedBy": "kwepems100002.china.huawei.com (7.221.188.206) To\n kwepemk500009.china.huawei.com (7.202.194.94)" }, "content": "Add support to batch get CPU steering tags for device-specific TPH mode.\nThis interface requires enabling the 'enable_unsafe_tph_ds_mode' module\nparameter.\n\nSigned-off-by: Chengwen Feng <fengchengwen@huawei.com>\n---\n drivers/vfio/pci/vfio_pci_core.c | 76 ++++++++++++++++++++++++++++++++\n 1 file changed, 76 insertions(+)", "diff": "diff --git a/drivers/vfio/pci/vfio_pci_core.c b/drivers/vfio/pci/vfio_pci_core.c\nindex bfc7e87d190f..7ec2dd32f106 100644\n--- a/drivers/vfio/pci/vfio_pci_core.c\n+++ b/drivers/vfio/pci/vfio_pci_core.c\n@@ -1532,6 +1532,80 @@ static int vfio_pci_tph_disable(struct vfio_pci_core_device *vdev)\n \treturn 0;\n }\n \n+static int vfio_pci_tph_get_st(struct vfio_pci_core_device *vdev,\n+\t\t\t struct vfio_device_pci_tph_op *op,\n+\t\t\t void __user *uarg)\n+{\n+\tstruct pci_dev *pdev = vdev->pdev;\n+\tu8 mode = pcie_tph_get_st_modes(pdev);\n+\tstruct vfio_pci_tph_entry *ents;\n+\tstruct vfio_pci_tph_st st;\n+\tenum tph_mem_type mtype;\n+\tsize_t size, ents_off;\n+\tint i, err;\n+\n+\tif (!enable_unsafe_tph_ds_mode || !(mode & PCI_TPH_CAP_ST_DS))\n+\t\treturn -EOPNOTSUPP;\n+\n+\tif (op->argsz < offsetofend(struct vfio_device_pci_tph_op, st))\n+\t\treturn -EINVAL;\n+\n+\tif (copy_from_user(&st, uarg, sizeof(st)))\n+\t\treturn -EFAULT;\n+\n+\t/* Check reserved fields are zero */\n+\tif (memchr_inv(&st.reserved, 0, sizeof(st.reserved)))\n+\t\treturn -EINVAL;\n+\n+\tif (!st.count || st.count > VFIO_PCI_TPH_MAX_ENTRIES)\n+\t\treturn -EINVAL;\n+\n+\tsize = st.count * sizeof(*ents);\n+\tif (op->argsz < offsetofend(struct vfio_device_pci_tph_op, st) + size)\n+\t\treturn -EINVAL;\n+\n+\tents = kvmalloc(size, GFP_KERNEL);\n+\tif (!ents)\n+\t\treturn -ENOMEM;\n+\n+\tents_off = offsetof(struct vfio_pci_tph_st, ents);\n+\tif (copy_from_user(ents, uarg + ents_off, size)) {\n+\t\terr = -EFAULT;\n+\t\tgoto out;\n+\t}\n+\n+\tfor (i = 0; i < st.count; i++) {\n+\t\t/* Check reserved fields and index are zero */\n+\t\tif (memchr_inv(&ents[i].reserved0, 0, sizeof(ents[i].reserved0)) ||\n+\t\t memchr_inv(&ents[i].reserved1, 0, sizeof(ents[i].reserved1)) ||\n+\t\t ents[i].index != 0) {\n+\t\t\terr = -EINVAL;\n+\t\t\tgoto out;\n+\t\t}\n+\n+\t\tif (ents[i].mem_type == VFIO_PCI_TPH_MEM_TYPE_VM) {\n+\t\t\tmtype = TPH_MEM_TYPE_VM;\n+\t\t} else if (ents[i].mem_type == VFIO_PCI_TPH_MEM_TYPE_PM) {\n+\t\t\tmtype = TPH_MEM_TYPE_PM;\n+\t\t} else {\n+\t\t\terr = -EINVAL;\n+\t\t\tgoto out;\n+\t\t}\n+\n+\t\terr = pcie_tph_get_cpu_st(pdev, mtype, ents[i].cpu,\n+\t\t\t\t\t &ents[i].st);\n+\t\tif (err)\n+\t\t\tgoto out;\n+\t}\n+\n+\tif (copy_to_user(uarg + ents_off, ents, size))\n+\t\terr = -EFAULT;\n+\n+out:\n+\tkvfree(ents);\n+\treturn err;\n+}\n+\n static int vfio_pci_ioctl_tph(struct vfio_pci_core_device *vdev,\n \t\t\t void __user *uarg)\n {\n@@ -1550,6 +1624,8 @@ static int vfio_pci_ioctl_tph(struct vfio_pci_core_device *vdev,\n \t\treturn vfio_pci_tph_enable(vdev, &op, uarg + minsz);\n \tcase VFIO_PCI_TPH_DISABLE:\n \t\treturn vfio_pci_tph_disable(vdev);\n+\tcase VFIO_PCI_TPH_GET_ST:\n+\t\treturn vfio_pci_tph_get_st(vdev, &op, uarg + minsz);\n \tdefault:\n \t\t/* Other ops are not implemented yet */\n \t\treturn -EINVAL;\n", "prefixes": [ "v8", "6/7" ] }