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GET /api/1.2/patches/2234855/?format=api
{ "id": 2234855, "url": "http://patchwork.ozlabs.org/api/1.2/patches/2234855/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260508064053.37529-2-fengchengwen@huawei.com/", "project": { "id": 28, "url": "http://patchwork.ozlabs.org/api/1.2/projects/28/?format=api", "name": "Linux PCI development", "link_name": "linux-pci", "list_id": "linux-pci.vger.kernel.org", "list_email": "linux-pci@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260508064053.37529-2-fengchengwen@huawei.com>", "list_archive_url": null, "date": "2026-05-08T06:40:47", "name": "[v8,1/7] PCI/TPH: Fix pcie_tph_get_st_table_loc() field extraction", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "c17a693542356bb2d8cc79304eca9e5850a740a1", "submitter": { "id": 92756, "url": "http://patchwork.ozlabs.org/api/1.2/people/92756/?format=api", "name": "fengchengwen", "email": "fengchengwen@huawei.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260508064053.37529-2-fengchengwen@huawei.com/mbox/", "series": [ { "id": 503332, "url": "http://patchwork.ozlabs.org/api/1.2/series/503332/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/list/?series=503332", "date": "2026-05-08T06:40:48", "name": "vfio/pci: Add PCIe TPH support", "version": 8, "mbox": "http://patchwork.ozlabs.org/series/503332/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2234855/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2234855/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-pci+bounces-54231-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-pci@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=huawei.com header.i=@huawei.com header.a=rsa-sha256\n header.s=dkim header.b=Akaxkqx8;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c0a:e001:db::12fc:5321; helo=sea.lore.kernel.org;\n envelope-from=linux-pci+bounces-54231-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)", "smtp.subspace.kernel.org;\n\tdkim=pass (1024-bit key) header.d=huawei.com header.i=@huawei.com\n header.b=\"Akaxkqx8\"", "smtp.subspace.kernel.org;\n arc=none smtp.client-ip=113.46.200.217", "smtp.subspace.kernel.org;\n dmarc=pass (p=quarantine dis=none) header.from=huawei.com", "smtp.subspace.kernel.org;\n spf=pass smtp.mailfrom=huawei.com" ], "Received": [ "from sea.lore.kernel.org (sea.lore.kernel.org\n [IPv6:2600:3c0a:e001:db::12fc:5321])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4gBffb1BgHz1yKm\n\tfor <incoming@patchwork.ozlabs.org>; Fri, 08 May 2026 16:41:43 +1000 (AEST)", "from smtp.subspace.kernel.org (conduit.subspace.kernel.org\n [100.90.174.1])\n\tby sea.lore.kernel.org (Postfix) with ESMTP id 08D62302A6DE\n\tfor <incoming@patchwork.ozlabs.org>; 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Fri, 8 May 2026 14:41:01 +0800" ], "ARC-Seal": "i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116;\n\tt=1778222478; cv=none;\n b=hFTdagXnATNak6GgkfRYlege2yC8Eo5K18SRmO9OGA9npPSWwT9Dxugbf19MM+hT5d7YbQl+pQg+MoDKjdNIS9kzQQzHcSxJYKIi+M26T19U2aNb9FyOVeiUnMXJ4eNrOZ1oywG63iQUqUoNiCUS8KTbx9S/CCtiU5YHKKlQSgw=", "ARC-Message-Signature": "i=1; a=rsa-sha256; d=subspace.kernel.org;\n\ts=arc-20240116; t=1778222478; c=relaxed/simple;\n\tbh=Jl36QBFaB1npZ4nQkXnLfLEiPBTpWQe0eZV5jvbLvV0=;\n\th=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References:\n\t MIME-Version:Content-Type;\n b=TKi5mXe0sfoFJqnH2dYJQqaF6qrkOTGDAAGjtRqsU9ahAhXv9Qz4vdNcIj/KiD/cJwHfpMMLMx72dE4W5Y3I//szX5E3H/YZhlIYRA1fvgI14JT+GwGv1pWrnYA5jtIKVFgfY3Gu0iicRGzadfMYXNx4eQdazu7i+hrN6lfL+Gc=", "ARC-Authentication-Results": "i=1; smtp.subspace.kernel.org;\n dmarc=pass (p=quarantine dis=none) header.from=huawei.com;\n spf=pass smtp.mailfrom=huawei.com;\n dkim=pass (1024-bit key) header.d=huawei.com header.i=@huawei.com\n header.b=Akaxkqx8; arc=none smtp.client-ip=113.46.200.217", "dkim-signature": "v=1; a=rsa-sha256; d=huawei.com; s=dkim;\n\tc=relaxed/relaxed; q=dns/txt;\n\th=From;\n\tbh=uIqZ4KBp1zO/lcRi0QiZxRKpi2g0llki1FIHFBCdG/E=;\n\tb=Akaxkqx8YW51TvNdywk7oh0bPH5uf6mDumcJvdyulTx6oabACOmULwGQFrdI9zSaGr29esOxj\n\tX2t8S71U3c27u1dqr+jgYHcovil0MDb090JE8YTVZ0wf+MkazxHApk6fozi3Zr2QUjDShl5BJHv\n\tEvO7cjxyiRqqUm1gylpmEhs=", "From": "Chengwen Feng <fengchengwen@huawei.com>", "To": "<alex@shazbot.org>, <jgg@ziepe.ca>", "CC": "<wathsala.vithanage@arm.com>, <helgaas@kernel.org>, <wei.huang2@amd.com>,\n\t<wangzhou1@hisilicon.com>, <wangyushan12@huawei.com>,\n\t<liuyonglong@huawei.com>, <kvm@vger.kernel.org>, <linux-pci@vger.kernel.org>", "Subject": "[PATCH v8 1/7] PCI/TPH: Fix pcie_tph_get_st_table_loc() field\n extraction", "Date": "Fri, 8 May 2026 14:40:47 +0800", "Message-ID": "<20260508064053.37529-2-fengchengwen@huawei.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20260508064053.37529-1-fengchengwen@huawei.com>", "References": "<20260508064053.37529-1-fengchengwen@huawei.com>", "Precedence": "bulk", "X-Mailing-List": "linux-pci@vger.kernel.org", "List-Id": "<linux-pci.vger.kernel.org>", "List-Subscribe": "<mailto:linux-pci+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-pci+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-ClientProxiedBy": "kwepems100002.china.huawei.com (7.221.188.206) To\n kwepemk500009.china.huawei.com (7.202.194.94)" }, "content": "pcie_tph_get_st_table_loc() incorrectly uses FIELD_GET(), which shifts the\nfield value to bit 0. But the function is designed to return raw\nPCI_TPH_LOC_* values as defined in the function comment.\n\nThis causes incorrect ST table location detection. Fix it by using bitwise\nAND with PCI_TPH_CAP_LOC_MASK to return the unshifted field value matching\nthe function specification.\n\nThis doesn't make a difference to mlx5_st_create(), the lone external\ncaller, because it only checks for PCI_TPH_LOC_NONE (0), but will be needed\nfor callers that check for PCI_TPH_LOC_CAP or PCI_TPH_LOC_MSIX.\n\nFixes: d2e8a34876ce (\"PCI/TPH: Add Steering Tag support\")\nCc: stable@vger.kernel.org\nSigned-off-by: Chengwen Feng <fengchengwen@huawei.com>\nReviewed-by: Alex Williamson <alex.williamson@nvidia.com>\nReviewed-by: Bjorn Helgaas <bhelgaas@google.com>\n---\n drivers/pci/tph.c | 7 +------\n 1 file changed, 1 insertion(+), 6 deletions(-)", "diff": "diff --git a/drivers/pci/tph.c b/drivers/pci/tph.c\nindex 91145e8d9d95..877cf556242b 100644\n--- a/drivers/pci/tph.c\n+++ b/drivers/pci/tph.c\n@@ -170,7 +170,7 @@ u32 pcie_tph_get_st_table_loc(struct pci_dev *pdev)\n \n \tpci_read_config_dword(pdev, pdev->tph_cap + PCI_TPH_CAP, ®);\n \n-\treturn FIELD_GET(PCI_TPH_CAP_LOC_MASK, reg);\n+\treturn reg & PCI_TPH_CAP_LOC_MASK;\n }\n EXPORT_SYMBOL(pcie_tph_get_st_table_loc);\n \n@@ -185,9 +185,6 @@ u16 pcie_tph_get_st_table_size(struct pci_dev *pdev)\n \n \t/* Check ST table location first */\n \tloc = pcie_tph_get_st_table_loc(pdev);\n-\n-\t/* Convert loc to match with PCI_TPH_LOC_* defined in pci_regs.h */\n-\tloc = FIELD_PREP(PCI_TPH_CAP_LOC_MASK, loc);\n \tif (loc != PCI_TPH_LOC_CAP)\n \t\treturn 0;\n \n@@ -316,8 +313,6 @@ int pcie_tph_set_st_entry(struct pci_dev *pdev, unsigned int index, u16 tag)\n \tset_ctrl_reg_req_en(pdev, PCI_TPH_REQ_DISABLE);\n \n \tloc = pcie_tph_get_st_table_loc(pdev);\n-\t/* Convert loc to match with PCI_TPH_LOC_* */\n-\tloc = FIELD_PREP(PCI_TPH_CAP_LOC_MASK, loc);\n \n \tswitch (loc) {\n \tcase PCI_TPH_LOC_MSIX:\n", "prefixes": [ "v8", "1/7" ] }