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GET /api/1.2/patches/2234854/?format=api
{ "id": 2234854, "url": "http://patchwork.ozlabs.org/api/1.2/patches/2234854/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260508064053.37529-4-fengchengwen@huawei.com/", "project": { "id": 28, "url": "http://patchwork.ozlabs.org/api/1.2/projects/28/?format=api", "name": "Linux PCI development", "link_name": "linux-pci", "list_id": "linux-pci.vger.kernel.org", "list_email": "linux-pci@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260508064053.37529-4-fengchengwen@huawei.com>", "list_archive_url": null, "date": "2026-05-08T06:40:49", "name": "[v8,3/7] PCI/TPH: Fix pcie_tph_get_st_table_size() for MSI-X table location", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "aa84b742407fdd7ffa6bdd005de42075c2423a38", "submitter": { "id": 92756, "url": "http://patchwork.ozlabs.org/api/1.2/people/92756/?format=api", "name": "fengchengwen", "email": "fengchengwen@huawei.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260508064053.37529-4-fengchengwen@huawei.com/mbox/", "series": [ { "id": 503332, "url": "http://patchwork.ozlabs.org/api/1.2/series/503332/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/list/?series=503332", "date": "2026-05-08T06:40:48", "name": "vfio/pci: Add PCIe TPH support", "version": 8, "mbox": "http://patchwork.ozlabs.org/series/503332/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2234854/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2234854/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-pci+bounces-54230-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-pci@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=huawei.com header.i=@huawei.com header.a=rsa-sha256\n header.s=dkim header.b=oBYbuELm;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=172.234.253.10; helo=sea.lore.kernel.org;\n envelope-from=linux-pci+bounces-54230-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)", "smtp.subspace.kernel.org;\n\tdkim=pass (1024-bit key) header.d=huawei.com header.i=@huawei.com\n header.b=\"oBYbuELm\"", "smtp.subspace.kernel.org;\n arc=none smtp.client-ip=113.46.200.216", "smtp.subspace.kernel.org;\n dmarc=pass (p=quarantine dis=none) header.from=huawei.com", "smtp.subspace.kernel.org;\n spf=pass smtp.mailfrom=huawei.com" ], "Received": [ "from sea.lore.kernel.org (sea.lore.kernel.org [172.234.253.10])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4gBffZ2rWmz1yCg\n\tfor <incoming@patchwork.ozlabs.org>; Fri, 08 May 2026 16:41:42 +1000 (AEST)", "from smtp.subspace.kernel.org (conduit.subspace.kernel.org\n [100.90.174.1])\n\tby sea.lore.kernel.org (Postfix) with ESMTP id A4533302416A\n\tfor <incoming@patchwork.ozlabs.org>; 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Fri, 8 May 2026 14:41:01 +0800" ], "ARC-Seal": "i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116;\n\tt=1778222473; cv=none;\n b=FGcVU/Vw9xo2+lgcNNIWG61JR+4K5gPc3XcWk+KGq1ecvKQerm3QtvNBxZEkOZRO38z4XfKViHMNPisIYX5KLd2Iv+X4p6zPUZTGxR42YLI3kpM6YeQg+ocUBIAiaHIT9Tsj9IrFH+RsRVP5IGtZKwCPBr6FO/gPiwJk5xgWtQk=", "ARC-Message-Signature": "i=1; a=rsa-sha256; d=subspace.kernel.org;\n\ts=arc-20240116; t=1778222473; c=relaxed/simple;\n\tbh=jGWZt+muHQjHiDAtSM3t1BbGSIeNek4CA9L/iIFoteo=;\n\th=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References:\n\t MIME-Version:Content-Type;\n b=sYAgrOMOx9kFZC2qKa5MDcMKzf8fdCGvXS7a+ptoE+YGiN7SdXrDmZocOm8HyTtljdFaUIRXOu3JpNRvVqJgniOsKITAP9reeRjlOeRda7ELyY8DwunZbw+NlcU5wa9lQ3jBiJaItlLU5KoaIGkaLx66VHY62bnod8OmxFC0V3c=", "ARC-Authentication-Results": "i=1; smtp.subspace.kernel.org;\n dmarc=pass (p=quarantine dis=none) header.from=huawei.com;\n spf=pass smtp.mailfrom=huawei.com;\n dkim=pass (1024-bit key) header.d=huawei.com header.i=@huawei.com\n header.b=oBYbuELm; arc=none smtp.client-ip=113.46.200.216", "dkim-signature": "v=1; a=rsa-sha256; d=huawei.com; s=dkim;\n\tc=relaxed/relaxed; q=dns/txt;\n\th=From;\n\tbh=RMM7zbz5ogyu0ekYiyez9w+tUq9cgNHg57Z5pm8yAMs=;\n\tb=oBYbuELmUO/hWTgQK1BnaVASaEjX3GTwitjGCpO2D/zfkUDw4+zk/P+oek+md93soGfACsjkO\n\tk4V9fxXSa/rv/iJWIqGf4XAkVXBOxoJHNYP32g4zAXIsr4FpXwCFnIuPAsiH8Nb0AyXMsH2WxTG\n\tUL4y7guGL2fxS5pwlyoB9wU=", "From": "Chengwen Feng <fengchengwen@huawei.com>", "To": "<alex@shazbot.org>, <jgg@ziepe.ca>", "CC": "<wathsala.vithanage@arm.com>, <helgaas@kernel.org>, <wei.huang2@amd.com>,\n\t<wangzhou1@hisilicon.com>, <wangyushan12@huawei.com>,\n\t<liuyonglong@huawei.com>, <kvm@vger.kernel.org>, <linux-pci@vger.kernel.org>", "Subject": "[PATCH v8 3/7] PCI/TPH: Fix pcie_tph_get_st_table_size() for MSI-X\n table location", "Date": "Fri, 8 May 2026 14:40:49 +0800", "Message-ID": "<20260508064053.37529-4-fengchengwen@huawei.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20260508064053.37529-1-fengchengwen@huawei.com>", "References": "<20260508064053.37529-1-fengchengwen@huawei.com>", "Precedence": "bulk", "X-Mailing-List": "linux-pci@vger.kernel.org", "List-Id": "<linux-pci.vger.kernel.org>", "List-Subscribe": "<mailto:linux-pci+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-pci+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-ClientProxiedBy": "kwepems100002.china.huawei.com (7.221.188.206) To\n kwepemk500009.china.huawei.com (7.202.194.94)" }, "content": "pcie_tph_get_st_table_size() previously only returned valid size when ST\nTable is in TPH Capability space. According to PCIe spec [1], ST table size\nis also valid when ST Table is located in MSI-X table.\n\nFix it to return valid table size for both PCI_TPH_LOC_CAP and\nPCI_TPH_LOC_MSIX locations.\n\n[1] PCI Express Base 6.1 Table 7-258 TPH Requester Capability Register\nST Table Size:\n- Value indicates the maximum number of ST Table entries the Function may\n use. Software reads this field to determine the ST Table Size N, which is\n encoded as N-1. For example, a returned value of 000 0000 0011b indicates\n a table size of four entries.\n- There is an upper limit of 64 entries when the ST Table is located in the\n TPH Requester Extended Capability structure.\n- When the ST Table is located in the MSI-X Table, this value is limited by\n the size of the MSI-X Table.\n- This field is only applicable for Functions that implement an ST Table as\n indicated by the ST Table Location field. Otherwise, the value in this\n field is undefined.\n\nSigned-off-by: Chengwen Feng <fengchengwen@huawei.com>\n---\n drivers/pci/tph.c | 5 +++--\n 1 file changed, 3 insertions(+), 2 deletions(-)", "diff": "diff --git a/drivers/pci/tph.c b/drivers/pci/tph.c\nindex ba31b010f67a..de5bd7039cdc 100644\n--- a/drivers/pci/tph.c\n+++ b/drivers/pci/tph.c\n@@ -191,7 +191,8 @@ EXPORT_SYMBOL(pcie_tph_get_st_table_loc);\n \n /*\n * Return the size of ST table. If ST table is not in TPH Requester Extended\n- * Capability space, return 0. Otherwise return the ST Table Size + 1.\n+ * Capability space or MSI-X table, return 0. Otherwise return the\n+ * ST Table Size + 1.\n */\n u16 pcie_tph_get_st_table_size(struct pci_dev *pdev)\n {\n@@ -200,7 +201,7 @@ u16 pcie_tph_get_st_table_size(struct pci_dev *pdev)\n \n \t/* Check ST table location first */\n \tloc = pcie_tph_get_st_table_loc(pdev);\n-\tif (loc != PCI_TPH_LOC_CAP)\n+\tif (loc != PCI_TPH_LOC_CAP && loc != PCI_TPH_LOC_MSIX)\n \t\treturn 0;\n \n \tpci_read_config_dword(pdev, pdev->tph_cap + PCI_TPH_CAP, ®);\n", "prefixes": [ "v8", "3/7" ] }