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GET /api/1.2/patches/2234851/?format=api
{ "id": 2234851, "url": "http://patchwork.ozlabs.org/api/1.2/patches/2234851/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260508064053.37529-3-fengchengwen@huawei.com/", "project": { "id": 28, "url": "http://patchwork.ozlabs.org/api/1.2/projects/28/?format=api", "name": "Linux PCI development", "link_name": "linux-pci", "list_id": "linux-pci.vger.kernel.org", "list_email": "linux-pci@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260508064053.37529-3-fengchengwen@huawei.com>", "list_archive_url": null, "date": "2026-05-08T06:40:48", "name": "[v8,2/7] PCI/TPH: Export pcie_tph_get_st_modes() for external use", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "d7fd4d88aa54e41cb0d9017c367da0619fcce54c", "submitter": { "id": 92756, "url": "http://patchwork.ozlabs.org/api/1.2/people/92756/?format=api", "name": "fengchengwen", "email": "fengchengwen@huawei.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260508064053.37529-3-fengchengwen@huawei.com/mbox/", "series": [ { "id": 503332, "url": "http://patchwork.ozlabs.org/api/1.2/series/503332/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/list/?series=503332", "date": "2026-05-08T06:40:48", "name": "vfio/pci: Add PCIe TPH support", "version": 8, "mbox": "http://patchwork.ozlabs.org/series/503332/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2234851/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2234851/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-pci+bounces-54227-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-pci@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=huawei.com header.i=@huawei.com header.a=rsa-sha256\n header.s=dkim header.b=ui3JM8fR;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c0a:e001:db::12fc:5321; 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Fri, 8 May 2026 14:41:01 +0800" ], "ARC-Seal": "i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116;\n\tt=1778222471; cv=none;\n b=kZoA09Vj2hMGQjIYFi6Zys9fU4Gwqsvcf2dQfCzqgXJIkJgle1Jtb82VjI6FpaHQdh3sBv6RRB9IQrJY+nEC5PBA0XV8sPF4k6dpp+2QNtqspPCHAzAptLgU7WBNyGMw9X9im9zGwBdnlT5dx1LfU7CCfg6WgWSZiWpYcB7e0Oc=", "ARC-Message-Signature": "i=1; a=rsa-sha256; d=subspace.kernel.org;\n\ts=arc-20240116; t=1778222471; c=relaxed/simple;\n\tbh=nZ77Qx15FQjlfkQiv1WNBEd+bTaQpuNpy4fkczqNe0s=;\n\th=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References:\n\t MIME-Version:Content-Type;\n b=hNZNKuR2aV5vUEdX3kBS/XjYn9NCZBDF54A+R0Et/uTScVn58Q5W1Ke+IpTVbL8FXxSF5hm8BLF1QHl8ZY2Y/AHDmVwFEig5RPB+Obsn+6d44NLvi0qguX5tPjAAjDY4u427ai+xZRc9bM99vxLLezHVEEg4tZzhDIYFxF79tWo=", "ARC-Authentication-Results": "i=1; smtp.subspace.kernel.org;\n dmarc=pass (p=quarantine dis=none) header.from=huawei.com;\n spf=pass smtp.mailfrom=huawei.com;\n dkim=pass (1024-bit key) header.d=huawei.com header.i=@huawei.com\n header.b=ui3JM8fR; arc=none smtp.client-ip=113.46.200.225", "dkim-signature": "v=1; a=rsa-sha256; d=huawei.com; s=dkim;\n\tc=relaxed/relaxed; q=dns/txt;\n\th=From;\n\tbh=5ZWpG5nAH4Ms4MOMRfRox3bKTRlzC2EutZldfGVDmEw=;\n\tb=ui3JM8fRTPCUjKUiUWGi+71kvtIRzOJRK/ShoXbYFzCuZM1S7+4TxymHYm++XU8yyP/YIb1fm\n\tv4Lr6EqZ5/7B5qpTmFPjapXn23zi7ptKQklh2GoILnndCzlQl1gHMNRPoORCJeiJa1fL8/DS0NL\n\tRiD/nSu0kEIHw23bhrPqNuA=", "From": "Chengwen Feng <fengchengwen@huawei.com>", "To": "<alex@shazbot.org>, <jgg@ziepe.ca>", "CC": "<wathsala.vithanage@arm.com>, <helgaas@kernel.org>, <wei.huang2@amd.com>,\n\t<wangzhou1@hisilicon.com>, <wangyushan12@huawei.com>,\n\t<liuyonglong@huawei.com>, <kvm@vger.kernel.org>, <linux-pci@vger.kernel.org>", "Subject": "[PATCH v8 2/7] PCI/TPH: Export pcie_tph_get_st_modes() for external\n use", "Date": "Fri, 8 May 2026 14:40:48 +0800", "Message-ID": "<20260508064053.37529-3-fengchengwen@huawei.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20260508064053.37529-1-fengchengwen@huawei.com>", "References": "<20260508064053.37529-1-fengchengwen@huawei.com>", "Precedence": "bulk", "X-Mailing-List": "linux-pci@vger.kernel.org", "List-Id": "<linux-pci.vger.kernel.org>", "List-Subscribe": "<mailto:linux-pci+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-pci+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-ClientProxiedBy": "kwepems100002.china.huawei.com (7.221.188.206) To\n kwepemk500009.china.huawei.com (7.202.194.94)" }, "content": "Export the helper to retrieve supported PCIe TPH steering tag modes so\nthat drivers like VFIO can query and expose device capabilities to\nuserspace.\n\nAdd stub functions for pcie_tph_get_st_table_size() and\npcie_tph_get_st_table_loc() when !CONFIG_PCIE_TPH.\n\nAdd tph_cap validation for pcie_tph_get_st_modes() and\npcie_tph_get_st_table_loc() to prevent invalid PCI configuration\nspace access when TPH is not supported.\n\nSigned-off-by: Chengwen Feng <fengchengwen@huawei.com>\nAcked-by: Bjorn Helgaas <bhelgaas@google.com>\n---\n drivers/pci/tph.c | 19 +++++++++++++++++--\n include/linux/pci-tph.h | 7 +++++++\n 2 files changed, 24 insertions(+), 2 deletions(-)", "diff": "diff --git a/drivers/pci/tph.c b/drivers/pci/tph.c\nindex 877cf556242b..ba31b010f67a 100644\n--- a/drivers/pci/tph.c\n+++ b/drivers/pci/tph.c\n@@ -145,15 +145,27 @@ static void set_ctrl_reg_req_en(struct pci_dev *pdev, u8 req_type)\n \tpci_write_config_dword(pdev, pdev->tph_cap + PCI_TPH_CTRL, reg);\n }\n \n-static u8 get_st_modes(struct pci_dev *pdev)\n+/**\n+ * pcie_tph_get_st_modes - Get supported Steering Tag modes\n+ * @pdev: PCI device to query\n+ *\n+ * Return:\n+ * Bitmask of supported ST modes (PCI_TPH_CAP_ST_NS, PCI_TPH_CAP_ST_IV,\n+ * PCI_TPH_CAP_ST_DS)\n+ */\n+u8 pcie_tph_get_st_modes(struct pci_dev *pdev)\n {\n \tu32 reg;\n \n+\tif (!pdev->tph_cap)\n+\t\treturn 0;\n+\n \tpci_read_config_dword(pdev, pdev->tph_cap + PCI_TPH_CAP, ®);\n \treg &= PCI_TPH_CAP_ST_NS | PCI_TPH_CAP_ST_IV | PCI_TPH_CAP_ST_DS;\n \n \treturn reg;\n }\n+EXPORT_SYMBOL(pcie_tph_get_st_modes);\n \n /**\n * pcie_tph_get_st_table_loc - Return the device's ST table location\n@@ -168,6 +180,9 @@ u32 pcie_tph_get_st_table_loc(struct pci_dev *pdev)\n {\n \tu32 reg;\n \n+\tif (!pdev->tph_cap)\n+\t\treturn PCI_TPH_LOC_NONE;\n+\n \tpci_read_config_dword(pdev, pdev->tph_cap + PCI_TPH_CAP, ®);\n \n \treturn reg & PCI_TPH_CAP_LOC_MASK;\n@@ -395,7 +410,7 @@ int pcie_enable_tph(struct pci_dev *pdev, int mode)\n \n \t/* Sanitize and check ST mode compatibility */\n \tmode &= PCI_TPH_CTRL_MODE_SEL_MASK;\n-\tdev_modes = get_st_modes(pdev);\n+\tdev_modes = pcie_tph_get_st_modes(pdev);\n \tif (!((1 << mode) & dev_modes))\n \t\treturn -EINVAL;\n \ndiff --git a/include/linux/pci-tph.h b/include/linux/pci-tph.h\nindex be68cd17f2f8..5772d48ea444 100644\n--- a/include/linux/pci-tph.h\n+++ b/include/linux/pci-tph.h\n@@ -30,6 +30,7 @@ void pcie_disable_tph(struct pci_dev *pdev);\n int pcie_enable_tph(struct pci_dev *pdev, int mode);\n u16 pcie_tph_get_st_table_size(struct pci_dev *pdev);\n u32 pcie_tph_get_st_table_loc(struct pci_dev *pdev);\n+u8 pcie_tph_get_st_modes(struct pci_dev *pdev);\n #else\n static inline int pcie_tph_set_st_entry(struct pci_dev *pdev,\n \t\t\t\t\tunsigned int index, u16 tag)\n@@ -41,6 +42,12 @@ static inline int pcie_tph_get_cpu_st(struct pci_dev *dev,\n static inline void pcie_disable_tph(struct pci_dev *pdev) { }\n static inline int pcie_enable_tph(struct pci_dev *pdev, int mode)\n { return -EINVAL; }\n+static inline u16 pcie_tph_get_st_table_size(struct pci_dev *pdev)\n+{ return 0; }\n+static inline u32 pcie_tph_get_st_table_loc(struct pci_dev *pdev)\n+{ return 0; }\n+static inline u8 pcie_tph_get_st_modes(struct pci_dev *pdev)\n+{ return 0; }\n #endif\n \n #endif /* LINUX_PCI_TPH_H */\n", "prefixes": [ "v8", "2/7" ] }