Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/1.2/patches/2234850/?format=api
{ "id": 2234850, "url": "http://patchwork.ozlabs.org/api/1.2/patches/2234850/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260508064053.37529-8-fengchengwen@huawei.com/", "project": { "id": 28, "url": "http://patchwork.ozlabs.org/api/1.2/projects/28/?format=api", "name": "Linux PCI development", "link_name": "linux-pci", "list_id": "linux-pci.vger.kernel.org", "list_email": "linux-pci@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260508064053.37529-8-fengchengwen@huawei.com>", "list_archive_url": null, "date": "2026-05-08T06:40:53", "name": "[v8,7/7] vfio/pci: Add PCIe TPH SET_ST interface", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "c5332125d69d44eecb2835c6118516ce34caedf5", "submitter": { "id": 92756, "url": "http://patchwork.ozlabs.org/api/1.2/people/92756/?format=api", "name": "fengchengwen", "email": "fengchengwen@huawei.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260508064053.37529-8-fengchengwen@huawei.com/mbox/", "series": [ { "id": 503332, "url": "http://patchwork.ozlabs.org/api/1.2/series/503332/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/list/?series=503332", "date": "2026-05-08T06:40:48", "name": "vfio/pci: Add PCIe TPH support", "version": 8, "mbox": "http://patchwork.ozlabs.org/series/503332/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2234850/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2234850/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-pci+bounces-54228-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-pci@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=huawei.com header.i=@huawei.com header.a=rsa-sha256\n header.s=dkim header.b=TRrGX/GE;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c04:e001:36c::12fc:5321; helo=tor.lore.kernel.org;\n envelope-from=linux-pci+bounces-54228-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)", "smtp.subspace.kernel.org;\n\tdkim=pass (1024-bit key) header.d=huawei.com header.i=@huawei.com\n header.b=\"TRrGX/GE\"", "smtp.subspace.kernel.org;\n arc=none smtp.client-ip=113.46.200.222", "smtp.subspace.kernel.org;\n dmarc=pass (p=quarantine dis=none) header.from=huawei.com", "smtp.subspace.kernel.org;\n spf=pass smtp.mailfrom=huawei.com" ], "Received": [ "from tor.lore.kernel.org (tor.lore.kernel.org\n [IPv6:2600:3c04:e001:36c::12fc:5321])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4gBff70QHzz1yCg\n\tfor <incoming@patchwork.ozlabs.org>; Fri, 08 May 2026 16:41:18 +1000 (AEST)", "from smtp.subspace.kernel.org (conduit.subspace.kernel.org\n [100.90.174.1])\n\tby tor.lore.kernel.org (Postfix) with ESMTP id 20F04300D93B\n\tfor <incoming@patchwork.ozlabs.org>; Fri, 8 May 2026 06:41:17 +0000 (UTC)", "from localhost.localdomain (localhost.localdomain [127.0.0.1])\n\tby smtp.subspace.kernel.org (Postfix) with ESMTP id 5CC1731E846;\n\tFri, 8 May 2026 06:41:15 +0000 (UTC)", "from canpmsgout07.his.huawei.com (canpmsgout07.his.huawei.com\n [113.46.200.222])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby smtp.subspace.kernel.org (Postfix) with ESMTPS id DD9AF346FD2;\n\tFri, 8 May 2026 06:41:07 +0000 (UTC)", "from mail.maildlp.com (unknown [172.19.163.15])\n\tby canpmsgout07.his.huawei.com (SkyGuard) with ESMTPS id 4gBfT60xDJzLlX9;\n\tFri, 8 May 2026 14:33:30 +0800 (CST)", "from kwepemk500009.china.huawei.com (unknown [7.202.194.94])\n\tby mail.maildlp.com (Postfix) with ESMTPS id 9BC6C40539;\n\tFri, 8 May 2026 14:41:03 +0800 (CST)", "from localhost.localdomain (10.50.163.32) by\n kwepemk500009.china.huawei.com (7.202.194.94) with Microsoft SMTP Server\n (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id\n 15.2.1544.11; Fri, 8 May 2026 14:41:03 +0800" ], "ARC-Seal": "i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116;\n\tt=1778222472; cv=none;\n b=QuRk9pLlJjcdsRP2x7F49IE3LxdVEHSXttzTz2a5C0qKu5HWoh/X7LsKItSwIzASGO5Znl0Tp4mMYSUwL90QK8OnQG+8AjkQ+gCg26ZZ8nFtKykmKZ6anrdbQxI8yHXXEybfE1XbQ1DpJ/fTwSMIvLw7YaDVcTVorggXsf5TqAs=", "ARC-Message-Signature": "i=1; a=rsa-sha256; d=subspace.kernel.org;\n\ts=arc-20240116; t=1778222472; c=relaxed/simple;\n\tbh=eRTzNOuDc7dat6s4hNmwZXsKyWASDNuahad7V9t5tdM=;\n\th=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References:\n\t MIME-Version:Content-Type;\n b=IEnTAIQ+zLFJo/o5Lq7OXJMZrGJ7rJjfdiF0rJiEsXMIHUl1R2BlKnERvTtpx0phWnOa1Q8z93RS/5Hb6haJziF8PTbNraAVomRJI3cdeAbBRt8YXQ8Hj3aD95PPJxy7fQ3XGuTLTt9QGHF9SaBleUmCc7HSuypWWdS+C5oVC3g=", "ARC-Authentication-Results": "i=1; smtp.subspace.kernel.org;\n dmarc=pass (p=quarantine dis=none) header.from=huawei.com;\n spf=pass smtp.mailfrom=huawei.com;\n dkim=pass (1024-bit key) header.d=huawei.com header.i=@huawei.com\n header.b=TRrGX/GE; arc=none smtp.client-ip=113.46.200.222", "dkim-signature": "v=1; a=rsa-sha256; d=huawei.com; s=dkim;\n\tc=relaxed/relaxed; q=dns/txt;\n\th=From;\n\tbh=fd2VDTjAdMqXsNa5cZTMm3EpBDW41poENzxMNDtCrgQ=;\n\tb=TRrGX/GE+CsDsW4tZKC1DrB2+RkHLxowLixpUOYPilkwQtsvKS2J1ZkKsyqdh44dkMBFYX7n3\n\t9684qmag0vOtlT9vSk6Jc73q1OsVEEr1QAtLFSVdITiP1EqdzP1vHHy8UySrPFcCKCIxsB0TGSQ\n\tMYwunOyy0IWtBQuwaVaUzDo=", "From": "Chengwen Feng <fengchengwen@huawei.com>", "To": "<alex@shazbot.org>, <jgg@ziepe.ca>", "CC": "<wathsala.vithanage@arm.com>, <helgaas@kernel.org>, <wei.huang2@amd.com>,\n\t<wangzhou1@hisilicon.com>, <wangyushan12@huawei.com>,\n\t<liuyonglong@huawei.com>, <kvm@vger.kernel.org>, <linux-pci@vger.kernel.org>", "Subject": "[PATCH v8 7/7] vfio/pci: Add PCIe TPH SET_ST interface", "Date": "Fri, 8 May 2026 14:40:53 +0800", "Message-ID": "<20260508064053.37529-8-fengchengwen@huawei.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20260508064053.37529-1-fengchengwen@huawei.com>", "References": "<20260508064053.37529-1-fengchengwen@huawei.com>", "Precedence": "bulk", "X-Mailing-List": "linux-pci@vger.kernel.org", "List-Id": "<linux-pci.vger.kernel.org>", "List-Subscribe": "<mailto:linux-pci+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-pci+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-ClientProxiedBy": "kwepems100002.china.huawei.com (7.221.188.206) To\n kwepemk500009.china.huawei.com (7.202.194.94)" }, "content": "Add VFIO_PCI_TPH_SET_ST operation to support batch programming of steering\ntag entries. If any entry fails, roll back successfully programmed entries\nto 0 to prevent inconsistent device state.\n\nSigned-off-by: Chengwen Feng <fengchengwen@huawei.com>\n---\n drivers/vfio/pci/vfio_pci_core.c | 90 ++++++++++++++++++++++++++++++++\n 1 file changed, 90 insertions(+)", "diff": "diff --git a/drivers/vfio/pci/vfio_pci_core.c b/drivers/vfio/pci/vfio_pci_core.c\nindex 7ec2dd32f106..9e399696ce6e 100644\n--- a/drivers/vfio/pci/vfio_pci_core.c\n+++ b/drivers/vfio/pci/vfio_pci_core.c\n@@ -1606,6 +1606,94 @@ static int vfio_pci_tph_get_st(struct vfio_pci_core_device *vdev,\n \treturn err;\n }\n \n+static int vfio_pci_tph_set_st(struct vfio_pci_core_device *vdev,\n+\t\t\t struct vfio_device_pci_tph_op *op,\n+\t\t\t void __user *uarg)\n+{\n+\tstruct pci_dev *pdev = vdev->pdev;\n+\tstruct vfio_pci_tph_entry *ents;\n+\tstruct vfio_pci_tph_st st;\n+\tenum tph_mem_type mtype;\n+\tsize_t size, ents_off;\n+\tint i = 0, j, err;\n+\tu32 tab_sz;\n+\tu16 st_val;\n+\n+\ttab_sz = pcie_tph_get_st_table_size(pdev);\n+\tif (tab_sz == 0)\n+\t\treturn -EOPNOTSUPP;\n+\n+\tif (op->argsz < offsetofend(struct vfio_device_pci_tph_op, st))\n+\t\treturn -EINVAL;\n+\n+\tif (copy_from_user(&st, uarg, sizeof(st)))\n+\t\treturn -EFAULT;\n+\n+\tif (!st.count || st.count > VFIO_PCI_TPH_MAX_ENTRIES)\n+\t\treturn -EINVAL;\n+\n+\t/* Check reserved fields are zero */\n+\tif (memchr_inv(&st.reserved, 0, sizeof(st.reserved)))\n+\t\treturn -EINVAL;\n+\n+\tsize = st.count * sizeof(*ents);\n+\tif (op->argsz < offsetofend(struct vfio_device_pci_tph_op, st) + size)\n+\t\treturn -EINVAL;\n+\n+\tents = kvmalloc(size, GFP_KERNEL);\n+\tif (!ents)\n+\t\treturn -ENOMEM;\n+\n+\tents_off = offsetof(struct vfio_pci_tph_st, ents);\n+\tif (copy_from_user(ents, uarg + ents_off, size)) {\n+\t\terr = -EFAULT;\n+\t\tgoto out;\n+\t}\n+\n+\tfor (; i < st.count; i++) {\n+\t\terr = -EINVAL;\n+\n+\t\t/* Check reserved fields and st are zero */\n+\t\tif (memchr_inv(&ents[i].reserved0, 0, sizeof(ents[i].reserved0)) ||\n+\t\t memchr_inv(&ents[i].reserved1, 0, sizeof(ents[i].reserved1)) ||\n+\t\t ents[i].st != 0)\n+\t\t\tgoto out;\n+\n+\t\tif (ents[i].mem_type == VFIO_PCI_TPH_MEM_TYPE_VM)\n+\t\t\tmtype = TPH_MEM_TYPE_VM;\n+\t\telse if (ents[i].mem_type == VFIO_PCI_TPH_MEM_TYPE_PM)\n+\t\t\tmtype = TPH_MEM_TYPE_PM;\n+\t\telse\n+\t\t\tgoto out;\n+\n+\t\tif (ents[i].index >= tab_sz)\n+\t\t\tgoto out;\n+\n+\t\tif (ents[i].cpu == U32_MAX) {\n+\t\t\terr = pcie_tph_set_st_entry(pdev, ents[i].index, 0);\n+\t\t\tif (err)\n+\t\t\t\tgoto out;\n+\t\t\tcontinue;\n+\t\t}\n+\n+\t\terr = pcie_tph_get_cpu_st(pdev, mtype, ents[i].cpu, &st_val);\n+\t\tif (err)\n+\t\t\tgoto out;\n+\t\terr = pcie_tph_set_st_entry(pdev, ents[i].index, st_val);\n+\t\tif (err)\n+\t\t\tgoto out;\n+\t}\n+\n+out:\n+\tif (err) {\n+\t\t/* Roll back previously programmed entries to 0 */\n+\t\tfor (j = 0; j < i; j++)\n+\t\t\tpcie_tph_set_st_entry(pdev, ents[j].index, 0);\n+\t}\n+\tkvfree(ents);\n+\treturn err;\n+}\n+\n static int vfio_pci_ioctl_tph(struct vfio_pci_core_device *vdev,\n \t\t\t void __user *uarg)\n {\n@@ -1626,6 +1714,8 @@ static int vfio_pci_ioctl_tph(struct vfio_pci_core_device *vdev,\n \t\treturn vfio_pci_tph_disable(vdev);\n \tcase VFIO_PCI_TPH_GET_ST:\n \t\treturn vfio_pci_tph_get_st(vdev, &op, uarg + minsz);\n+\tcase VFIO_PCI_TPH_SET_ST:\n+\t\treturn vfio_pci_tph_set_st(vdev, &op, uarg + minsz);\n \tdefault:\n \t\t/* Other ops are not implemented yet */\n \t\treturn -EINVAL;\n", "prefixes": [ "v8", "7/7" ] }