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GET /api/1.2/patches/2234707/?format=api
{ "id": 2234707, "url": "http://patchwork.ozlabs.org/api/1.2/patches/2234707/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260507234413.643512-43-richard.henderson@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.2/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260507234413.643512-43-richard.henderson@linaro.org>", "list_archive_url": null, "date": "2026-05-07T23:43:55", "name": "[v4,42/60] target/arm: Implement LUTI4 (four registers, 8-bit)", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "2d79471139e9db86da43040844f27855bba1c1a3", "submitter": { "id": 72104, "url": "http://patchwork.ozlabs.org/api/1.2/people/72104/?format=api", "name": "Richard Henderson", "email": "richard.henderson@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260507234413.643512-43-richard.henderson@linaro.org/mbox/", "series": [ { "id": 503296, "url": "http://patchwork.ozlabs.org/api/1.2/series/503296/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=503296", "date": "2026-05-07T23:43:14", "name": "target/arm: Implement FEAT_FP8", "version": 4, "mbox": "http://patchwork.ozlabs.org/series/503296/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2234707/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2234707/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit 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helo=mail-oi1-x22e.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "Signed-off-by: Richard Henderson <richard.henderson@linaro.org>\n---\n target/arm/cpu-features.h | 5 +++++\n target/arm/tcg/helper-defs.h | 1 +\n target/arm/tcg/translate-sme.c | 6 ++++++\n target/arm/tcg/vec_helper.c | 14 ++++++++++++++\n target/arm/tcg/sme.decode | 6 ++++++\n 5 files changed, 32 insertions(+)", "diff": "diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h\nindex fa8a619ae0..1963392730 100644\n--- a/target/arm/cpu-features.h\n+++ b/target/arm/cpu-features.h\n@@ -1637,6 +1637,11 @@ static inline bool isar_feature_aa64_sme2_f8cvt(const ARMISARegisters *id)\n return isar_feature_aa64_sme2(id) && isar_feature_aa64_f8cvt(id);\n }\n \n+static inline bool isar_feature_aa64_sme2p1_lutv2(const ARMISARegisters *id)\n+{\n+ return isar_feature_aa64_sme2p1(id) && isar_feature_aa64_sme_lutv2(id);\n+}\n+\n static inline bool isar_feature_aa64_sve_i8mm(const ARMISARegisters *id)\n {\n return isar_feature_aa64_sve(id) && isar_feature_aa64_sme_sve_i8mm(id);\ndiff --git a/target/arm/tcg/helper-defs.h b/target/arm/tcg/helper-defs.h\nindex 05ccf795e8..8ec6c16319 100644\n--- a/target/arm/tcg/helper-defs.h\n+++ b/target/arm/tcg/helper-defs.h\n@@ -1120,6 +1120,7 @@ DEF_HELPER_FLAGS_4(sme2_luti4_2b, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)\n DEF_HELPER_FLAGS_4(sme2_luti4_2h, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)\n DEF_HELPER_FLAGS_4(sme2_luti4_2s, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)\n \n+DEF_HELPER_FLAGS_4(sme2_luti4_4b, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)\n DEF_HELPER_FLAGS_4(sme2_luti4_4h, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)\n DEF_HELPER_FLAGS_4(sme2_luti4_4s, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)\n \ndiff --git a/target/arm/tcg/translate-sme.c b/target/arm/tcg/translate-sme.c\nindex 214427db1f..0af133c1c4 100644\n--- a/target/arm/tcg/translate-sme.c\n+++ b/target/arm/tcg/translate-sme.c\n@@ -1846,6 +1846,9 @@ TRANS_FEAT(LUTI4_c_2s, aa64_sme2, do_lut, a, gen_helper_sme2_luti4_2s, false)\n TRANS_FEAT(LUTI4_c_4h, aa64_sme2, do_lut, a, gen_helper_sme2_luti4_4h, false)\n TRANS_FEAT(LUTI4_c_4s, aa64_sme2, do_lut, a, gen_helper_sme2_luti4_4s, false)\n \n+TRANS_FEAT(LUTI4_c_4b, aa64_sme_lutv2, do_lut, a,\n+ gen_helper_sme2_luti4_4b, false)\n+\n static bool do_lut_s4(DisasContext *s, arg_lut *a, gen_helper_gvec_2_ptr *fn)\n {\n return !(a->zd & 0b01100) && do_lut(s, a, fn, true);\n@@ -1866,3 +1869,6 @@ TRANS_FEAT(LUTI4_s_2b, aa64_sme2p1, do_lut_s8, a, gen_helper_sme2_luti4_2b)\n TRANS_FEAT(LUTI4_s_2h, aa64_sme2p1, do_lut_s8, a, gen_helper_sme2_luti4_2h)\n \n TRANS_FEAT(LUTI4_s_4h, aa64_sme2p1, do_lut_s4, a, gen_helper_sme2_luti4_4h)\n+\n+TRANS_FEAT(LUTI4_s_4b, aa64_sme2p1_lutv2, do_lut_s4, a,\n+ gen_helper_sme2_luti4_4b)\ndiff --git a/target/arm/tcg/vec_helper.c b/target/arm/tcg/vec_helper.c\nindex f0dc11bc8a..20ecdb0a9e 100644\n--- a/target/arm/tcg/vec_helper.c\n+++ b/target/arm/tcg/vec_helper.c\n@@ -3346,6 +3346,20 @@ DO_SME2_LUT(4,4,s, 4)\n \n #undef DO_SME2_LUT\n \n+void helper_sme2_luti4_4b(void *zd, void *zn, CPUARMState *env, uint32_t desc)\n+{\n+ unsigned vl = simd_oprsz(desc);\n+ unsigned strided = extract32(desc, SIMD_DATA_SHIFT, 1);\n+ unsigned dstride = !strided ? 1 : 4;\n+ uint64_t indexes[ARM_MAX_VQ * 4];\n+\n+ memcpy(&indexes, zn, vl);\n+ memcpy((void *)&indexes + vl, zn + sizeof(ARMVectorReg), vl);\n+\n+ do_lut_b(zd, indexes, (void *)env->za_state.zt0, vl, 0,\n+ dstride * sizeof(ARMVectorReg), 4, 32, 4);\n+}\n+\n void HELPER(gvec_luti2_b)(void *vd, void *vn, void *vm, uint32_t desc)\n {\n unsigned part = simd_data(desc);\ndiff --git a/target/arm/tcg/sme.decode b/target/arm/tcg/sme.decode\nindex 339de72b8a..495330aed7 100644\n--- a/target/arm/tcg/sme.decode\n+++ b/target/arm/tcg/sme.decode\n@@ -1014,8 +1014,14 @@ LUTI4_c_2s 1100 0000 1000 101 idx:2 1 10 00 zn:5 .... 0 &lut zd=%zd_ax2\n LUTI4_c_4h 1100 0000 1000 101 idx:1 10 01 00 zn:5 ... 00 &lut zd=%zd_ax4\n LUTI4_c_4s 1100 0000 1000 101 idx:1 10 10 00 zn:5 ... 00 &lut zd=%zd_ax4\n \n+LUTI4_c_4b 1100 0000 1000 101 1 00 00 00 ....0 ...00 \\\n+ &lut zd=%zd_ax4 zn=%zn_ax2 idx=0\n+\n # LUTI4, strided (must check zd alignment)\n LUTI4_s_2b 1100 0000 1001 101 idx:2 1 00 00 zn:5 zd:5 &lut\n LUTI4_s_2h 1100 0000 1001 101 idx:2 1 01 00 zn:5 zd:5 &lut\n \n LUTI4_s_4h 1100 0000 1001 101 idx:1 10 01 00 zn:5 zd:5 &lut\n+\n+LUTI4_s_4b 1100 0000 1001 101 1 00 00 00 ....0 zd:5 \\\n+ &lut zn=%zn_ax2 idx=0\n", "prefixes": [ "v4", "42/60" ] }