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GET /api/1.2/patches/2234701/?format=api
{ "id": 2234701, "url": "http://patchwork.ozlabs.org/api/1.2/patches/2234701/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260507234413.643512-53-richard.henderson@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.2/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260507234413.643512-53-richard.henderson@linaro.org>", "list_archive_url": null, "date": "2026-05-07T23:44:05", "name": "[v4,52/60] target/arm: Implement FDOT (FP8 to FP16) for AdvSIMD", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "90f2e1b2ab0c9ec7cdafb507fc5fcd485335d08e", "submitter": { "id": 72104, "url": "http://patchwork.ozlabs.org/api/1.2/people/72104/?format=api", "name": "Richard Henderson", "email": "richard.henderson@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260507234413.643512-53-richard.henderson@linaro.org/mbox/", "series": [ { "id": 503296, "url": "http://patchwork.ozlabs.org/api/1.2/series/503296/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=503296", "date": "2026-05-07T23:43:14", "name": "target/arm: Implement FEAT_FP8", "version": 4, "mbox": "http://patchwork.ozlabs.org/series/503296/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2234701/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2234701/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=swIlN2DX;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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helo=mail-oa1-x30.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "Signed-off-by: Richard Henderson <richard.henderson@linaro.org>\n---\n target/arm/cpu-features.h | 5 ++++\n target/arm/tcg/helper-fp8-defs.h | 3 +++\n target/arm/tcg/fp8_helper.c | 41 ++++++++++++++++++++++++++++++++\n target/arm/tcg/translate-a64.c | 2 ++\n target/arm/tcg/a64.decode | 2 ++\n 5 files changed, 53 insertions(+)", "diff": "diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h\nindex 908dfe0edd..ae98d126ae 100644\n--- a/target/arm/cpu-features.h\n+++ b/target/arm/cpu-features.h\n@@ -1604,6 +1604,11 @@ static inline bool isar_feature_aa64_f8dp4(const ARMISARegisters *id)\n return FIELD_EX64_IDREG(id, ID_AA64FPFR0, F8DP4);\n }\n \n+static inline bool isar_feature_aa64_f8dp2(const ARMISARegisters *id)\n+{\n+ return FIELD_EX64_IDREG(id, ID_AA64FPFR0, F8DP2);\n+}\n+\n /*\n * Combinations of feature tests, for ease of use with TRANS_FEAT.\n */\ndiff --git a/target/arm/tcg/helper-fp8-defs.h b/target/arm/tcg/helper-fp8-defs.h\nindex ee6f2e9236..5995d77577 100644\n--- a/target/arm/tcg/helper-fp8-defs.h\n+++ b/target/arm/tcg/helper-fp8-defs.h\n@@ -32,3 +32,6 @@ DEF_HELPER_FLAGS_5(gvec_fmla_idx_sb, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env,\n \n DEF_HELPER_FLAGS_5(gvec_fdot_sb, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32)\n DEF_HELPER_FLAGS_5(gvec_fdot_idx_sb, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32)\n+\n+DEF_HELPER_FLAGS_5(gvec_fdot_hb, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32)\n+DEF_HELPER_FLAGS_5(gvec_fdot_idx_hb, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32)\ndiff --git a/target/arm/tcg/fp8_helper.c b/target/arm/tcg/fp8_helper.c\nindex 48a2e29a31..d169e8327f 100644\n--- a/target/arm/tcg/fp8_helper.c\n+++ b/target/arm/tcg/fp8_helper.c\n@@ -772,3 +772,44 @@ void HELPER(gvec_fdot_idx_sb)(void *vd, void *vn, void *vm,\n fp8_mul_finish(env, &ctx);\n clear_tail(vd, oprsz, simd_maxsz(desc));\n }\n+\n+void HELPER(gvec_fdot_hb)(void *vd, void *vn, void *vm,\n+ CPUARMState *env, uint32_t desc)\n+{\n+ FP8MulContext ctx = fp8_mul_start(env, 0xf);\n+ size_t oprsz = simd_oprsz(desc);\n+ size_t nelem = oprsz / 2;\n+ uint16_t *n = vn;\n+ uint16_t *m = vm;\n+ float16 *d = vd;\n+\n+ for (size_t i = 0; i < nelem; i++) {\n+ d[i] = f8dotadd_h(n[i], m[i], 2, d[i], &ctx);\n+ }\n+\n+ fp8_mul_finish(env, &ctx);\n+ clear_tail(vd, oprsz, simd_maxsz(desc));\n+}\n+\n+void HELPER(gvec_fdot_idx_hb)(void *vd, void *vn, void *vm,\n+ CPUARMState *env, uint32_t desc)\n+{\n+ FP8MulContext ctx = fp8_mul_start(env, 0xf);\n+ size_t idx = simd_data(desc);\n+ size_t oprsz = simd_oprsz(desc);\n+ size_t nelem = oprsz / 2;\n+ uint16_t *n = vn;\n+ uint16_t *m = vm;\n+ float16 *d = vd;\n+ size_t i = 0;\n+\n+ do {\n+ uint16_t e1 = m[i + H2(idx)];\n+ do {\n+ d[i] = f8dotadd_h(n[i], e1, 2, d[i], &ctx);\n+ } while (++i % 8 != 0);\n+ } while (i < nelem);\n+\n+ fp8_mul_finish(env, &ctx);\n+ clear_tail(vd, oprsz, simd_maxsz(desc));\n+}\ndiff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c\nindex 8ea63e94fe..c5ea6b27a9 100644\n--- a/target/arm/tcg/translate-a64.c\n+++ b/target/arm/tcg/translate-a64.c\n@@ -7417,6 +7417,7 @@ static bool do_f8dot(DisasContext *s, arg_qrrr_e *a,\n }\n \n TRANS_FEAT(FDOT_sb_v, aa64_f8dp4, do_f8dot, a, gen_helper_gvec_fdot_sb)\n+TRANS_FEAT(FDOT_hb_v, aa64_f8dp2, do_f8dot, a, gen_helper_gvec_fdot_hb)\n \n static bool do_f8dot_idx(DisasContext *s, arg_qrrx_e *a,\n gen_helper_gvec_3_ptr *fn)\n@@ -7432,6 +7433,7 @@ static bool do_f8dot_idx(DisasContext *s, arg_qrrx_e *a,\n }\n \n TRANS_FEAT(FDOT_sb_vi, aa64_f8dp4, do_f8dot_idx, a, gen_helper_gvec_fdot_idx_sb)\n+TRANS_FEAT(FDOT_hb_vi, aa64_f8dp2, do_f8dot_idx, a, gen_helper_gvec_fdot_idx_hb)\n \n static bool do_int3_vector_idx(DisasContext *s, arg_qrrx_e *a,\n gen_helper_gvec_3 * const fns[2])\ndiff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode\nindex d78a3d5486..d1254355b6 100644\n--- a/target/arm/tcg/a64.decode\n+++ b/target/arm/tcg/a64.decode\n@@ -1214,6 +1214,7 @@ FMLALL_sb_v 0.00 1110 0.0 rm:5 110001 rn:5 rd:5 \\\n &rxx idxm=0 idxn=%fmlall_idxn\n \n FDOT_sb_v 0.00 1110 000 ..... 11111 1 ..... ..... @qrrr_s\n+FDOT_hb_v 0.00 1110 010 ..... 11111 1 ..... ..... @qrrr_h\n \n ### Advanced SIMD scalar x indexed element\n \n@@ -1340,6 +1341,7 @@ FMLALL_sb_vi 0 . 10 1111 0 . ... rm:3 1000 . 0 rn:5 rd:5 \\\n &rxx idxm=%hlm4 idxn=%fmlall_idxn\n \n FDOT_sb_vi 0.00 1111 00 . ..... 0000 . 0 ..... ..... @qrrx_s\n+FDOT_hb_vi 0.00 1111 01 .. .... 0000 . 0 ..... ..... @qrrx_h\n \n # Floating-point conditional select\n \n", "prefixes": [ "v4", "52/60" ] }