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GET /api/1.2/patches/2234699/?format=api
{ "id": 2234699, "url": "http://patchwork.ozlabs.org/api/1.2/patches/2234699/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260507234413.643512-59-richard.henderson@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.2/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260507234413.643512-59-richard.henderson@linaro.org>", "list_archive_url": null, "date": "2026-05-07T23:44:11", "name": "[v4,58/60] target/arm: Implement FMMLA (FP8 to FP16) for AdvSIMD", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "626c1a122461a4bf5b4ce775424670913de53637", "submitter": { "id": 72104, "url": "http://patchwork.ozlabs.org/api/1.2/people/72104/?format=api", "name": "Richard Henderson", "email": "richard.henderson@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260507234413.643512-59-richard.henderson@linaro.org/mbox/", "series": [ { "id": 503296, "url": "http://patchwork.ozlabs.org/api/1.2/series/503296/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=503296", "date": "2026-05-07T23:43:14", "name": "target/arm: Implement FEAT_FP8", "version": 4, "mbox": "http://patchwork.ozlabs.org/series/503296/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2234699/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2234699/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=PjLQ47E+;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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helo=mail-oa1-x2f.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "Signed-off-by: Richard Henderson <richard.henderson@linaro.org>\n---\n target/arm/cpu-features.h | 5 +++++\n target/arm/tcg/helper-fp8-defs.h | 1 +\n target/arm/tcg/fp8_helper.c | 26 ++++++++++++++++++++++++++\n target/arm/tcg/translate-a64.c | 1 +\n target/arm/tcg/a64.decode | 1 +\n 5 files changed, 34 insertions(+)", "diff": "diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h\nindex 0aaf08eba9..41066ec5f7 100644\n--- a/target/arm/cpu-features.h\n+++ b/target/arm/cpu-features.h\n@@ -1619,6 +1619,11 @@ static inline bool isar_feature_aa64_f8mm8(const ARMISARegisters *id)\n return FIELD_EX64_IDREG(id, ID_AA64FPFR0, F8MM8);\n }\n \n+static inline bool isar_feature_aa64_f8mm4(const ARMISARegisters *id)\n+{\n+ return FIELD_EX64_IDREG(id, ID_AA64FPFR0, F8MM4);\n+}\n+\n /*\n * Combinations of feature tests, for ease of use with TRANS_FEAT.\n */\ndiff --git a/target/arm/tcg/helper-fp8-defs.h b/target/arm/tcg/helper-fp8-defs.h\nindex 3c74f02022..e942308af4 100644\n--- a/target/arm/tcg/helper-fp8-defs.h\n+++ b/target/arm/tcg/helper-fp8-defs.h\n@@ -37,3 +37,4 @@ DEF_HELPER_FLAGS_5(gvec_fdot_hb, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32)\n DEF_HELPER_FLAGS_5(gvec_fdot_idx_hb, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32)\n \n DEF_HELPER_FLAGS_5(gvec_fmmla_sb, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32)\n+DEF_HELPER_FLAGS_5(gvec_fmmla_hb, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32)\ndiff --git a/target/arm/tcg/fp8_helper.c b/target/arm/tcg/fp8_helper.c\nindex c90b276913..c40e026aea 100644\n--- a/target/arm/tcg/fp8_helper.c\n+++ b/target/arm/tcg/fp8_helper.c\n@@ -839,3 +839,29 @@ void HELPER(gvec_fmmla_sb)(void *vd, void *vn, void *vm,\n fp8_mul_finish(env, &ctx);\n clear_tail(vd, oprsz, simd_maxsz(desc));\n }\n+\n+void HELPER(gvec_fmmla_hb)(void *vd, void *vn, void *vm,\n+ CPUARMState *env, uint32_t desc)\n+{\n+ FP8MulContext ctx = fp8_mul_start(env, -1);\n+ size_t oprsz = simd_oprsz(desc);\n+ size_t nseg = oprsz / 16;\n+ uint32_t *n = vn;\n+ uint32_t *m = vm;\n+ float16 *d = vd;\n+\n+ for (size_t seg = 0; seg < nseg; seg++, d += 4, n += 2, m += 2) {\n+ float16 d0 = f8dotadd_h(n[0], m[0], 4, d[H4(0)], &ctx);\n+ float16 d1 = f8dotadd_h(n[0], m[1], 4, d[H4(1)], &ctx);\n+ float16 d2 = f8dotadd_h(n[1], m[0], 4, d[H4(2)], &ctx);\n+ float16 d3 = f8dotadd_h(n[1], m[1], 4, d[H4(3)], &ctx);\n+\n+ d[H4(0)] = d0;\n+ d[H4(1)] = d1;\n+ d[H4(2)] = d2;\n+ d[H4(3)] = d3;\n+ }\n+\n+ fp8_mul_finish(env, &ctx);\n+ clear_tail(vd, oprsz, simd_maxsz(desc));\n+}\ndiff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c\nindex 02d5e007f9..aff0f332ac 100644\n--- a/target/arm/tcg/translate-a64.c\n+++ b/target/arm/tcg/translate-a64.c\n@@ -7419,6 +7419,7 @@ static bool do_f8dot(DisasContext *s, arg_qrrr_e *a,\n TRANS_FEAT(FDOT_sb_v, aa64_f8dp4, do_f8dot, a, gen_helper_gvec_fdot_sb)\n TRANS_FEAT(FDOT_hb_v, aa64_f8dp2, do_f8dot, a, gen_helper_gvec_fdot_hb)\n TRANS_FEAT(FMMLA_sb, aa64_f8mm8, do_f8dot, a, gen_helper_gvec_fmmla_sb)\n+TRANS_FEAT(FMMLA_hb, aa64_f8mm4, do_f8dot, a, gen_helper_gvec_fmmla_hb)\n \n static bool do_f8dot_idx(DisasContext *s, arg_qrrx_e *a,\n gen_helper_gvec_3_ptr *fn)\ndiff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode\nindex 6404c26540..e7f2f30abb 100644\n--- a/target/arm/tcg/a64.decode\n+++ b/target/arm/tcg/a64.decode\n@@ -1217,6 +1217,7 @@ FDOT_sb_v 0.00 1110 000 ..... 11111 1 ..... ..... @qrrr_s\n FDOT_hb_v 0.00 1110 010 ..... 11111 1 ..... ..... @qrrr_h\n \n FMMLA_sb 0110 1110 100 ..... 11101 1 ..... ..... @rrr_q1e0\n+FMMLA_hb 0110 1110 000 ..... 11101 1 ..... ..... @rrr_q1e0\n \n ### Advanced SIMD scalar x indexed element\n \n", "prefixes": [ "v4", "58/60" ] }