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GET /api/1.2/patches/2234698/?format=api
{ "id": 2234698, "url": "http://patchwork.ozlabs.org/api/1.2/patches/2234698/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260507234413.643512-51-richard.henderson@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.2/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260507234413.643512-51-richard.henderson@linaro.org>", "list_archive_url": null, "date": "2026-05-07T23:44:03", "name": "[v4,50/60] target/arm: Implement FDOT (FP8 to FP32) for SVE", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "ccc6f598afaa6d3ce852375efd164168cdcb9106", "submitter": { "id": 72104, "url": "http://patchwork.ozlabs.org/api/1.2/people/72104/?format=api", "name": "Richard Henderson", "email": "richard.henderson@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260507234413.643512-51-richard.henderson@linaro.org/mbox/", "series": [ { "id": 503296, "url": "http://patchwork.ozlabs.org/api/1.2/series/503296/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=503296", "date": "2026-05-07T23:43:14", "name": "target/arm: Implement FEAT_FP8", "version": 4, "mbox": "http://patchwork.ozlabs.org/series/503296/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2234698/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2234698/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=EVEcBJ44;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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helo=mail-oo1-xc2c.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "Signed-off-by: Richard Henderson <richard.henderson@linaro.org>\n---\n target/arm/cpu-features.h | 5 +++++\n target/arm/tcg/translate-sve.c | 35 ++++++++++++++++++++++++++++++++++\n target/arm/tcg/sve.decode | 4 ++++\n 3 files changed, 44 insertions(+)", "diff": "diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h\nindex 95e1849a6c..908dfe0edd 100644\n--- a/target/arm/cpu-features.h\n+++ b/target/arm/cpu-features.h\n@@ -1544,6 +1544,11 @@ static inline bool isar_feature_aa64_ssve_f8fma(const ARMISARegisters *id)\n return FIELD_EX64_IDREG(id, ID_AA64SMFR0, SF8FMA);\n }\n \n+static inline bool isar_feature_aa64_ssve_f8dp4(const ARMISARegisters *id)\n+{\n+ return FIELD_EX64_IDREG(id, ID_AA64SMFR0, SF8DP4);\n+}\n+\n static inline bool isar_feature_aa64_sme_b16b16(const ARMISARegisters *id)\n {\n return FIELD_EX64_IDREG(id, ID_AA64SMFR0, B16B16);\ndiff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c\nindex e23ca43f55..88e6148b83 100644\n--- a/target/arm/tcg/translate-sve.c\n+++ b/target/arm/tcg/translate-sve.c\n@@ -8372,3 +8372,38 @@ TRANS(FMLAL_idx_hb, do_fmla_fp8, a, gen_helper_gvec_fmla_idx_hb)\n \n TRANS(FMLALL_sb, do_fmla_fp8, a, gen_helper_gvec_fmla_sb)\n TRANS(FMLALL_idx_sb, do_fmla_fp8, a, gen_helper_gvec_fmla_idx_sb)\n+\n+static bool do_f8dp4(DisasContext *s, gen_helper_gvec_3_ptr *fn,\n+ int rd, int rn, int rm, int index)\n+{\n+ bool fp8dp4 = dc_isar_feature(aa64_f8dp4, s);\n+ bool ssve_fp8dp4 = dc_isar_feature(aa64_ssve_f8dp4, s);\n+ bool ok = false;\n+\n+ /* Feature detection and enabling are complex here. */\n+ if (!(ssve_fp8dp4 || (fp8dp4 && dc_isar_feature(aa64_sve2, s)))) {\n+ return false;\n+ }\n+ if (fpmr_access_check(s)) {\n+ if (fp8dp4) {\n+ s->is_nonstreaming = !ssve_fp8dp4;\n+ ok = sve_access_check(s);\n+ } else {\n+ ok = sme_sm_enabled_check(s);\n+ }\n+ }\n+\n+ if (ok) {\n+ unsigned vsz = vec_full_reg_size(s);\n+ tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, rd),\n+ vec_full_reg_offset(s, rn),\n+ vec_full_reg_offset(s, rm),\n+ tcg_env, vsz, vsz,\n+ index, fn);\n+ }\n+ return true;\n+}\n+\n+TRANS(FDOT_sb, do_f8dp4, gen_helper_gvec_fdot_sb, a->rd, a->rn, a->rm, 0)\n+TRANS(FDOT_idx_sb, do_f8dp4, gen_helper_gvec_fdot_idx_sb,\n+ a->rd, a->rn, a->rm, a->index)\ndiff --git a/target/arm/tcg/sve.decode b/target/arm/tcg/sve.decode\nindex 06bbd7fa63..c49e992f10 100644\n--- a/target/arm/tcg/sve.decode\n+++ b/target/arm/tcg/sve.decode\n@@ -1874,6 +1874,8 @@ FMLALL_sb 01100100 00 1 rm:5 10 idxn:2 10 rn:5 rd:5 &rxx idxm=0\n FDOT_zzzz 01100100 00 1 ..... 10 0 00 0 ..... ..... @rda_rn_rm_ex esz=2\n BFDOT_zzzz 01100100 01 1 ..... 10 0 00 0 ..... ..... @rda_rn_rm_ex esz=2\n \n+FDOT_sb 01100100 01 1 ..... 10 0 00 1 ..... ..... @rda_rn_rm_ex esz=2\n+\n ### SVE2 floating-point multiply-add long (indexed)\n \n FMLALB_zzxw 01100100 10 1 ..... 0100.0 ..... ..... @rrxr_3a esz=2\n@@ -1897,6 +1899,8 @@ FMLALL_idx_sb 01100100 idxn:2 1 .. rm:3 1100 .. rn:5 rd:5 \\\n FDOT_zzxz 01100100 00 1 ..... 010000 ..... ..... @rrxr_2 esz=2\n BFDOT_zzxz 01100100 01 1 ..... 010000 ..... ..... @rrxr_2 esz=2\n \n+FDOT_idx_sb 01100100 01 1 ..... 010001 ..... ..... @rrxr_2 esz=2\n+\n ### SVE broadcast predicate element\n \n &psel esz pd pn pm rv imm\n", "prefixes": [ "v4", "50/60" ] }