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GET /api/1.2/patches/2234690/?format=api
{ "id": 2234690, "url": "http://patchwork.ozlabs.org/api/1.2/patches/2234690/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260507234413.643512-45-richard.henderson@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.2/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260507234413.643512-45-richard.henderson@linaro.org>", "list_archive_url": null, "date": "2026-05-07T23:43:57", "name": "[v4,44/60] target/arm: Implement FMLALB, FMLALT for AdvSIMD", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "29c1c1d7707cda33c6348032df4514bbe5d7784e", "submitter": { "id": 72104, "url": "http://patchwork.ozlabs.org/api/1.2/people/72104/?format=api", "name": "Richard Henderson", "email": "richard.henderson@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260507234413.643512-45-richard.henderson@linaro.org/mbox/", "series": [ { "id": 503296, "url": "http://patchwork.ozlabs.org/api/1.2/series/503296/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=503296", "date": "2026-05-07T23:43:14", "name": "target/arm: Implement FEAT_FP8", "version": 4, "mbox": "http://patchwork.ozlabs.org/series/503296/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2234690/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2234690/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit 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"X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "Signed-off-by: Richard Henderson <richard.henderson@linaro.org>\n---\n target/arm/cpu-features.h | 5 ++\n target/arm/tcg/helper-fp8-defs.h | 3 +\n target/arm/tcg/fp8_helper.c | 119 +++++++++++++++++++++++++++++--\n target/arm/tcg/translate-a64.c | 16 +++++\n target/arm/tcg/a64.decode | 8 +++\n 5 files changed, 147 insertions(+), 4 deletions(-)", "diff": "diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h\nindex 1963392730..dcbd839d2d 100644\n--- a/target/arm/cpu-features.h\n+++ b/target/arm/cpu-features.h\n@@ -1584,6 +1584,11 @@ static inline bool isar_feature_aa64_f8cvt(const ARMISARegisters *id)\n return FIELD_EX64_IDREG(id, ID_AA64FPFR0, F8CVT);\n }\n \n+static inline bool isar_feature_aa64_f8fma(const ARMISARegisters *id)\n+{\n+ return FIELD_EX64_IDREG(id, ID_AA64FPFR0, F8FMA);\n+}\n+\n /*\n * Combinations of feature tests, for ease of use with TRANS_FEAT.\n */\ndiff --git a/target/arm/tcg/helper-fp8-defs.h b/target/arm/tcg/helper-fp8-defs.h\nindex 36ae977431..7aa8366d94 100644\n--- a/target/arm/tcg/helper-fp8-defs.h\n+++ b/target/arm/tcg/helper-fp8-defs.h\n@@ -23,3 +23,6 @@ DEF_HELPER_FLAGS_4(sve2_fcvtnb_bs, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)\n DEF_HELPER_FLAGS_4(sve2_fcvtnt_bs, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)\n DEF_HELPER_FLAGS_4(sme2_fcvt_bs, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)\n DEF_HELPER_FLAGS_4(sme2_fcvtn_bs, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)\n+\n+DEF_HELPER_FLAGS_5(gvec_fmla_hb, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32)\n+DEF_HELPER_FLAGS_5(gvec_fmla_idx_hb, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32)\ndiff --git a/target/arm/tcg/fp8_helper.c b/target/arm/tcg/fp8_helper.c\nindex d7c1ff97b7..6d9f8a6135 100644\n--- a/target/arm/tcg/fp8_helper.c\n+++ b/target/arm/tcg/fp8_helper.c\n@@ -55,12 +55,15 @@ static FP8Context fp8_start(CPUARMState *env, uint32_t desc,\n return ret;\n }\n \n+static void fp8_finish_fpst(float_status *orig, float_status *tmp)\n+{\n+ int e = get_float_exception_flags(tmp);\n+ float_raise(e & ~float_flag_input_denormal_used, orig);\n+}\n+\n static void fp8_finish(CPUARMState *env, FP8Context *c)\n {\n- int new_flags = get_float_exception_flags(&c->stat);\n-\n- new_flags &= ~float_flag_input_denormal_used;\n- float_raise(new_flags, &env->vfp.fp_status[c->fpst]);\n+ fp8_finish_fpst(&env->vfp.fp_status[c->fpst], &c->stat);\n }\n \n static FP8Context fp8_src_start(CPUARMState *env, uint32_t desc, int scale_mask)\n@@ -563,3 +566,111 @@ void HELPER(sme2_fcvtn_bs)(void *vd, void *vn, CPUARMState *env, uint32_t desc)\n \n fp8_finish(env, &ctx);\n }\n+\n+typedef struct FP8MulContext {\n+ float_status stat;\n+ fp8_input_fn *fmt1;\n+ fp8_input_fn *fmt2;\n+ int scale;\n+} FP8MulContext;\n+\n+static FP8MulContext fp8_mul_start(CPUARMState *env, int scale_mask)\n+{\n+ uint64_t fpmr = env->vfp.fpmr;\n+\n+ FP8MulContext ret = {\n+ .stat = env->vfp.fp_status[FPST_A64],\n+ .fmt1 = fp8_input_fmt[FIELD_EX64(fpmr, FPMR, F8S1)],\n+ .fmt2 = fp8_input_fmt[FIELD_EX64(fpmr, FPMR, F8S2)],\n+ .scale = -(FIELD_EX64(fpmr, FPMR, LSCALE) & scale_mask),\n+ };\n+\n+ set_flush_to_zero(0, &ret.stat);\n+ set_flush_inputs_to_zero(0, &ret.stat);\n+ set_default_nan_mode(true, &ret.stat);\n+ set_float_rounding_mode(FIELD_EX64(fpmr, FPMR, OSM)\n+ ? float_round_nearest_even_max\n+ : float_round_nearest_even, &ret.stat);\n+\n+ return ret;\n+}\n+\n+static void fp8_mul_finish(CPUARMState *env, FP8MulContext *c)\n+{\n+ fp8_finish_fpst(&env->vfp.fp_status[FPST_A64], &c->stat);\n+}\n+\n+static FloatParts64 f8dot(uint64_t a, uint64_t b, int n, FP8MulContext *ctx)\n+{\n+ /*\n+ * Because of default_nan_mode, NaNs need no special handling.\n+ * We'll simply get the default NaN out at the end of the sequence.\n+ */\n+ FloatParts64 p0 = ctx->fmt1(a & 0xff, &ctx->stat);\n+ FloatParts64 p1 = ctx->fmt2(b & 0xff, &ctx->stat);\n+ FloatParts64 pr = parts64_mul(&p0, &p1, &ctx->stat);\n+\n+ for (int i = 1; i < n; ++i) {\n+ p0 = ctx->fmt1(extract64(a, i * 8, 8), &ctx->stat);\n+ p1 = ctx->fmt2(extract64(b, i * 8, 8), &ctx->stat);\n+ pr = parts64_muladd(&p0, &p1, &pr, 0, &ctx->stat);\n+ }\n+ return parts64_scalbn(&pr, ctx->scale, &ctx->stat);\n+}\n+\n+static float16 f8dotadd_h(uint64_t a, uint64_t b, int n, float16 c,\n+ FP8MulContext *ctx)\n+{\n+ FloatParts64 p0 = f8dot(a, b, n, ctx);\n+ FloatParts64 p1 = float16_unpack_canonical(c, &ctx->stat);\n+\n+ p0 = parts64_addsub(&p0, &p1, &ctx->stat, false);\n+ return float16_round_pack_canonical(&p0, &ctx->stat);\n+}\n+\n+void HELPER(gvec_fmla_hb)(void *vd, void *vn, void *vm,\n+ CPUARMState *env, uint32_t desc)\n+{\n+ FP8MulContext ctx = fp8_mul_start(env, 0xf);\n+ bool high = extract32(desc, SIMD_DATA_SHIFT, 1);\n+ size_t oprsz = simd_oprsz(desc);\n+ size_t nelem = oprsz / 2;\n+ uint8_t *n = vn;\n+ uint8_t *m = vm;\n+ float16 *d = vd;\n+\n+ for (size_t i = 0; i < nelem; i++) {\n+ uint8_t e0 = n[H1(2 * i + high)];\n+ uint8_t e1 = m[H1(2 * i + high)];\n+\n+ d[H2(i)] = f8dotadd_h(e0, e1, 1, d[H2(i)], &ctx);\n+ }\n+\n+ fp8_mul_finish(env, &ctx);\n+ clear_tail(vd, oprsz, simd_maxsz(desc));\n+}\n+\n+void HELPER(gvec_fmla_idx_hb)(void *vd, void *vn, void *vm,\n+ CPUARMState *env, uint32_t desc)\n+{\n+ FP8MulContext ctx = fp8_mul_start(env, 0xf);\n+ bool idx_n = extract32(desc, SIMD_DATA_SHIFT, 1);\n+ size_t idx_m = extract32(desc, SIMD_DATA_SHIFT + 2, 4);\n+ size_t oprsz = simd_oprsz(desc);\n+ size_t nelem = oprsz / 2;\n+ uint8_t *n = vn;\n+ uint8_t *m = vm;\n+ float16 *d = vd;\n+ size_t i = 0;\n+\n+ do {\n+ uint8_t e1 = m[2 * i + H1(idx_m)];\n+ do {\n+ uint8_t e0 = n[H1(2 * i + idx_n)];\n+ d[H2(i)] = f8dotadd_h(e0, e1, 1, d[H2(i)], &ctx);\n+ } while (++i % 8 != 0);\n+ } while (i < nelem);\n+\n+ fp8_mul_finish(env, &ctx);\n+ clear_tail(vd, oprsz, simd_maxsz(desc));\n+}\ndiff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c\nindex ee71c63116..1c1d4ad2f7 100644\n--- a/target/arm/tcg/translate-a64.c\n+++ b/target/arm/tcg/translate-a64.c\n@@ -7384,6 +7384,22 @@ TRANS_FEAT(FMLSL_vi, aa64_fhm, do_fmlal_idx, a, true, false)\n TRANS_FEAT(FMLAL2_vi, aa64_fhm, do_fmlal_idx, a, false, true)\n TRANS_FEAT(FMLSL2_vi, aa64_fhm, do_fmlal_idx, a, true, true)\n \n+static bool do_fmla_fp8(DisasContext *s, arg_rxx *a,\n+ gen_helper_gvec_3_ptr *fn)\n+{\n+ if (fpmr_access_check(s) && fp_access_check(s)) {\n+ tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, a->rd),\n+ vec_full_reg_offset(s, a->rn),\n+ vec_full_reg_offset(s, a->rm),\n+ tcg_env, 16, vec_full_reg_size(s),\n+ a->idxn | (a->idxm << 2), fn);\n+ }\n+ return true;\n+}\n+\n+TRANS_FEAT(FMLAL_hb_v, aa64_f8fma, do_fmla_fp8, a, gen_helper_gvec_fmla_hb)\n+TRANS_FEAT(FMLAL_hb_vi, aa64_f8fma, do_fmla_fp8, a, gen_helper_gvec_fmla_idx_hb)\n+\n static bool do_int3_vector_idx(DisasContext *s, arg_qrrx_e *a,\n gen_helper_gvec_3 * const fns[2])\n {\ndiff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode\nindex 6aea3ce89f..b89e83ce76 100644\n--- a/target/arm/tcg/a64.decode\n+++ b/target/arm/tcg/a64.decode\n@@ -25,6 +25,7 @@\n %esz_hsd 22:2 !function=xor_2\n %hl 11:1 21:1\n %hlm 11:1 20:2\n+%hlm4 11:1 19:3\n \n &r rn\n &rrr rd rn rm\n@@ -38,6 +39,7 @@\n &rri_e rd rn imm esz\n &rrr_e rd rn rm esz\n &rrx_e rd rn rm idx esz\n+&rxx rd rn rm idxn idxm\n &rrrr_e rd rn rm ra esz\n &qrr_e q rd rn esz\n &qrri_e q rd rn imm esz\n@@ -1204,6 +1206,9 @@ FSCALE 0.10 1110 1.1 ..... 11111 1 ..... ..... @qrrr_sd\n FCVTN_bh 0.00 1110 010 ..... 11110 1 ..... ..... @qrrr_h\n FCVTN_bs 0.00 1110 000 ..... 11110 1 ..... ..... @qrrr_h\n \n+FMLAL_hb_v 0 idxn:1 00 1110 110 rm:5 11111 1 rn:5 rd:5 \\\n+ &rxx idxm=0\n+\n ### Advanced SIMD scalar x indexed element\n \n FMUL_si 0101 1111 00 .. .... 1001 . 0 ..... ..... @rrx_h\n@@ -1322,6 +1327,9 @@ SQDMLAL_vi 0.00 1111 10 . ..... 0011 . 0 ..... ..... @qrrx_s\n SQDMLSL_vi 0.00 1111 01 .. .... 0111 . 0 ..... ..... @qrrx_h\n SQDMLSL_vi 0.00 1111 10 . ..... 0111 . 0 ..... ..... @qrrx_s\n \n+FMLAL_hb_vi 0 idxn:1 00 1111 11 ... rm:3 0000 . 0 rn:5 rd:5 \\\n+ &rxx idxm=%hlm4\n+\n # Floating-point conditional select\n \n FCSEL 0001 1110 .. 1 rm:5 cond:4 11 rn:5 rd:5 esz=%esz_hsd\n", "prefixes": [ "v4", "44/60" ] }