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GET /api/1.2/patches/2234689/?format=api
{ "id": 2234689, "url": "http://patchwork.ozlabs.org/api/1.2/patches/2234689/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260507234413.643512-47-richard.henderson@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.2/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260507234413.643512-47-richard.henderson@linaro.org>", "list_archive_url": null, "date": "2026-05-07T23:43:59", "name": "[v4,46/60] target/arm: Implement FMLALL{BB, BT, TB, TT} for AdvSIMD", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "40d2b790e2c52c1a2510d4cb67fb61fe3e885bac", "submitter": { "id": 72104, "url": "http://patchwork.ozlabs.org/api/1.2/people/72104/?format=api", "name": "Richard Henderson", "email": "richard.henderson@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260507234413.643512-47-richard.henderson@linaro.org/mbox/", "series": [ { "id": 503296, "url": "http://patchwork.ozlabs.org/api/1.2/series/503296/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=503296", "date": "2026-05-07T23:43:14", "name": "target/arm: Implement FEAT_FP8", "version": 4, "mbox": "http://patchwork.ozlabs.org/series/503296/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2234689/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2234689/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=D9wxzJEU;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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helo=mail-oo1-xc34.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "Signed-off-by: Richard Henderson <richard.henderson@linaro.org>\n---\n target/arm/tcg/helper-fp8-defs.h | 3 ++\n target/arm/tcg/fp8_helper.c | 57 ++++++++++++++++++++++++++++++++\n target/arm/tcg/translate-a64.c | 3 ++\n target/arm/tcg/a64.decode | 7 ++++\n 4 files changed, 70 insertions(+)", "diff": "diff --git a/target/arm/tcg/helper-fp8-defs.h b/target/arm/tcg/helper-fp8-defs.h\nindex 7aa8366d94..802a3b430e 100644\n--- a/target/arm/tcg/helper-fp8-defs.h\n+++ b/target/arm/tcg/helper-fp8-defs.h\n@@ -26,3 +26,6 @@ DEF_HELPER_FLAGS_4(sme2_fcvtn_bs, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)\n \n DEF_HELPER_FLAGS_5(gvec_fmla_hb, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32)\n DEF_HELPER_FLAGS_5(gvec_fmla_idx_hb, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32)\n+\n+DEF_HELPER_FLAGS_5(gvec_fmla_sb, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32)\n+DEF_HELPER_FLAGS_5(gvec_fmla_idx_sb, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32)\ndiff --git a/target/arm/tcg/fp8_helper.c b/target/arm/tcg/fp8_helper.c\nindex 6d9f8a6135..1d64138c18 100644\n--- a/target/arm/tcg/fp8_helper.c\n+++ b/target/arm/tcg/fp8_helper.c\n@@ -628,6 +628,16 @@ static float16 f8dotadd_h(uint64_t a, uint64_t b, int n, float16 c,\n return float16_round_pack_canonical(&p0, &ctx->stat);\n }\n \n+static float32 f8dotadd_s(uint64_t a, uint64_t b, int n, float32 c,\n+ FP8MulContext *ctx)\n+{\n+ FloatParts64 p0 = f8dot(a, b, n, ctx);\n+ FloatParts64 p1 = float32_unpack_canonical(c, &ctx->stat);\n+\n+ p0 = parts64_addsub(&p0, &p1, &ctx->stat, false);\n+ return float32_round_pack_canonical(&p0, &ctx->stat);\n+}\n+\n void HELPER(gvec_fmla_hb)(void *vd, void *vn, void *vm,\n CPUARMState *env, uint32_t desc)\n {\n@@ -674,3 +684,50 @@ void HELPER(gvec_fmla_idx_hb)(void *vd, void *vn, void *vm,\n fp8_mul_finish(env, &ctx);\n clear_tail(vd, oprsz, simd_maxsz(desc));\n }\n+\n+void HELPER(gvec_fmla_sb)(void *vd, void *vn, void *vm,\n+ CPUARMState *env, uint32_t desc)\n+{\n+ FP8MulContext ctx = fp8_mul_start(env, -1);\n+ size_t idx = extract32(desc, SIMD_DATA_SHIFT, 2);\n+ size_t oprsz = simd_oprsz(desc);\n+ size_t nelem = oprsz / 4;\n+ uint8_t *n = vn;\n+ uint8_t *m = vm;\n+ float32 *d = vd;\n+\n+ for (size_t i = 0; i < nelem; i++) {\n+ uint8_t e0 = n[H1(4 * i + idx)];\n+ uint8_t e1 = m[H1(4 * i + idx)];\n+\n+ d[H4(i)] = f8dotadd_s(e0, e1, 1, d[H4(i)], &ctx);\n+ }\n+\n+ fp8_mul_finish(env, &ctx);\n+ clear_tail(vd, oprsz, simd_maxsz(desc));\n+}\n+\n+void HELPER(gvec_fmla_idx_sb)(void *vd, void *vn, void *vm,\n+ CPUARMState *env, uint32_t desc)\n+{\n+ FP8MulContext ctx = fp8_mul_start(env, -1);\n+ size_t idx_n = extract32(desc, SIMD_DATA_SHIFT, 2);\n+ size_t idx_m = extract32(desc, SIMD_DATA_SHIFT + 2, 4);\n+ size_t oprsz = simd_oprsz(desc);\n+ size_t nelem = oprsz / 4;\n+ uint8_t *n = vn;\n+ uint8_t *m = vm;\n+ float32 *d = vd;\n+ size_t i = 0;\n+\n+ do {\n+ uint8_t e1 = m[4 * i + H1(idx_m)];\n+ do {\n+ uint8_t e0 = n[H1(4 * i + idx_n)];\n+ d[H4(i)] = f8dotadd_s(e0, e1, 1, d[H4(i)], &ctx);\n+ } while (++i % 4 != 0);\n+ } while (i < nelem);\n+\n+ fp8_mul_finish(env, &ctx);\n+ clear_tail(vd, oprsz, simd_maxsz(desc));\n+}\ndiff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c\nindex 1c1d4ad2f7..946c16d439 100644\n--- a/target/arm/tcg/translate-a64.c\n+++ b/target/arm/tcg/translate-a64.c\n@@ -7400,6 +7400,9 @@ static bool do_fmla_fp8(DisasContext *s, arg_rxx *a,\n TRANS_FEAT(FMLAL_hb_v, aa64_f8fma, do_fmla_fp8, a, gen_helper_gvec_fmla_hb)\n TRANS_FEAT(FMLAL_hb_vi, aa64_f8fma, do_fmla_fp8, a, gen_helper_gvec_fmla_idx_hb)\n \n+TRANS_FEAT(FMLALL_sb_v, aa64_f8fma, do_fmla_fp8, a, gen_helper_gvec_fmla_sb)\n+TRANS_FEAT(FMLALL_sb_vi, aa64_f8fma, do_fmla_fp8, a, gen_helper_gvec_fmla_idx_sb)\n+\n static bool do_int3_vector_idx(DisasContext *s, arg_qrrx_e *a,\n gen_helper_gvec_3 * const fns[2])\n {\ndiff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode\nindex b89e83ce76..ef6d7dfeaa 100644\n--- a/target/arm/tcg/a64.decode\n+++ b/target/arm/tcg/a64.decode\n@@ -1209,6 +1209,10 @@ FCVTN_bs 0.00 1110 000 ..... 11110 1 ..... ..... @qrrr_h\n FMLAL_hb_v 0 idxn:1 00 1110 110 rm:5 11111 1 rn:5 rd:5 \\\n &rxx idxm=0\n \n+%fmlall_idxn 30:1 22:1\n+FMLALL_sb_v 0.00 1110 0.0 rm:5 110001 rn:5 rd:5 \\\n+ &rxx idxm=0 idxn=%fmlall_idxn\n+\n ### Advanced SIMD scalar x indexed element\n \n FMUL_si 0101 1111 00 .. .... 1001 . 0 ..... ..... @rrx_h\n@@ -1330,6 +1334,9 @@ SQDMLSL_vi 0.00 1111 10 . ..... 0111 . 0 ..... ..... @qrrx_s\n FMLAL_hb_vi 0 idxn:1 00 1111 11 ... rm:3 0000 . 0 rn:5 rd:5 \\\n &rxx idxm=%hlm4\n \n+FMLALL_sb_vi 0 . 10 1111 0 . ... rm:3 1000 . 0 rn:5 rd:5 \\\n+ &rxx idxm=%hlm4 idxn=%fmlall_idxn\n+\n # Floating-point conditional select\n \n FCSEL 0001 1110 .. 1 rm:5 cond:4 11 rn:5 rd:5 esz=%esz_hsd\n", "prefixes": [ "v4", "46/60" ] }