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GET /api/1.2/patches/2234688/?format=api
{ "id": 2234688, "url": "http://patchwork.ozlabs.org/api/1.2/patches/2234688/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260507234413.643512-37-richard.henderson@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.2/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260507234413.643512-37-richard.henderson@linaro.org>", "list_archive_url": null, "date": "2026-05-07T23:43:49", "name": "[v4,36/60] target/arm: Implement LUTI2, LUTI4 for AdvSIMD", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "a23dec5981a2b0ac271366400b4cee14fe28b53c", "submitter": { "id": 72104, "url": "http://patchwork.ozlabs.org/api/1.2/people/72104/?format=api", "name": "Richard Henderson", "email": "richard.henderson@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260507234413.643512-37-richard.henderson@linaro.org/mbox/", "series": [ { "id": 503296, "url": "http://patchwork.ozlabs.org/api/1.2/series/503296/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=503296", "date": "2026-05-07T23:43:14", "name": "target/arm: Implement FEAT_FP8", "version": 4, "mbox": "http://patchwork.ozlabs.org/series/503296/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2234688/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2234688/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n 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"X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "Signed-off-by: Richard Henderson <richard.henderson@linaro.org>\n---\n target/arm/tcg/helper-defs.h | 5 ++++\n target/arm/tcg/translate-a64.c | 38 +++++++++++++++++++++++++\n target/arm/tcg/vec_helper.c | 52 ++++++++++++++++++++++++++++++++++\n target/arm/tcg/a64.decode | 6 ++++\n 4 files changed, 101 insertions(+)", "diff": "diff --git a/target/arm/tcg/helper-defs.h b/target/arm/tcg/helper-defs.h\nindex a05f2258f2..05ccf795e8 100644\n--- a/target/arm/tcg/helper-defs.h\n+++ b/target/arm/tcg/helper-defs.h\n@@ -1122,3 +1122,8 @@ DEF_HELPER_FLAGS_4(sme2_luti4_2s, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)\n \n DEF_HELPER_FLAGS_4(sme2_luti4_4h, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)\n DEF_HELPER_FLAGS_4(sme2_luti4_4s, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)\n+\n+DEF_HELPER_FLAGS_4(gvec_luti2_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)\n+DEF_HELPER_FLAGS_4(gvec_luti2_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)\n+DEF_HELPER_FLAGS_4(gvec_luti4_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)\n+DEF_HELPER_FLAGS_4(gvec_luti4_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)\ndiff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c\nindex 3c784afc99..508d8e377b 100644\n--- a/target/arm/tcg/translate-a64.c\n+++ b/target/arm/tcg/translate-a64.c\n@@ -5405,6 +5405,44 @@ static bool trans_TBL_TBX(DisasContext *s, arg_TBL_TBX *a)\n return true;\n }\n \n+static bool do_lut_1(DisasContext *s, arg_rrx_e *a, gen_helper_gvec_3 *fn)\n+{\n+ if (fp_access_check(s)) {\n+ gen_gvec_op3_ool(s, true, a->rd, a->rn, a->rm, a->idx, fn);\n+ }\n+ return true;\n+}\n+\n+TRANS_FEAT(LUTI2_1b, aa64_lut, do_lut_1, a, gen_helper_gvec_luti2_b)\n+TRANS_FEAT(LUTI2_1h, aa64_lut, do_lut_1, a, gen_helper_gvec_luti2_h)\n+TRANS_FEAT(LUTI4_1b, aa64_lut, do_lut_1, a, gen_helper_gvec_luti4_b)\n+\n+static bool trans_LUTI4_2h(DisasContext *s, arg_rrx_e *a)\n+{\n+ if (!dc_isar_feature(aa64_lut, s)) {\n+ return false;\n+ }\n+ if (fp_access_check(s)) {\n+ /*\n+ * (Ab)use preg_tmp to merge two disjoint 128-bit quantities\n+ * into a sequential 256-bit table.\n+ */\n+ QEMU_BUILD_BUG_ON(sizeof_field(CPUARMState, vfp.preg_tmp) < 32);\n+ unsigned tmp_ofs = offsetof(CPUARMState, vfp.preg_tmp);\n+ unsigned rn0_ofs = vec_full_reg_offset(s, a->rn);\n+ unsigned rn1_ofs = vec_full_reg_offset(s, (a->rn + 1) % 32);\n+\n+ tcg_gen_gvec_mov(MO_64, tmp_ofs, rn0_ofs, 16, 16);\n+ tcg_gen_gvec_mov(MO_64, tmp_ofs + 16, rn1_ofs, 16, 16);\n+\n+ tcg_gen_gvec_3_ool(vec_full_reg_offset(s, a->rd), tmp_ofs,\n+ vec_full_reg_offset(s, a->rm),\n+ 16, vec_full_reg_size(s),\n+ a->idx, gen_helper_gvec_luti4_h);\n+ }\n+ return true;\n+}\n+\n typedef int simd_permute_idx_fn(int i, int part, int elements);\n \n static bool do_simd_permute(DisasContext *s, arg_qrrr_e *a,\ndiff --git a/target/arm/tcg/vec_helper.c b/target/arm/tcg/vec_helper.c\nindex 3231bb2100..f0dc11bc8a 100644\n--- a/target/arm/tcg/vec_helper.c\n+++ b/target/arm/tcg/vec_helper.c\n@@ -3345,3 +3345,55 @@ DO_SME2_LUT(4,4,h, 2)\n DO_SME2_LUT(4,4,s, 4)\n \n #undef DO_SME2_LUT\n+\n+void HELPER(gvec_luti2_b)(void *vd, void *vn, void *vm, uint32_t desc)\n+{\n+ unsigned part = simd_data(desc);\n+ unsigned vl = simd_oprsz(desc);\n+ unsigned elements = vl / 8;\n+ unsigned ibase = elements * part;\n+ ARMVectorReg scratch;\n+\n+ do_lut_b(&scratch, vm, vn, elements, ibase, 0, 2, 8, 1);\n+ memcpy(vd, &scratch, vl);\n+ clear_tail(vd, vl, simd_maxsz(desc));\n+}\n+\n+void HELPER(gvec_luti2_h)(void *vd, void *vn, void *vm, uint32_t desc)\n+{\n+ unsigned part = simd_data(desc);\n+ unsigned vl = simd_oprsz(desc);\n+ unsigned elements = vl / 16;\n+ unsigned ibase = elements * part;\n+ ARMVectorReg scratch;\n+\n+ do_lut_h(&scratch, vm, vn, elements, ibase, 0, 2, 16, 1);\n+ memcpy(vd, &scratch, vl);\n+ clear_tail(vd, vl, simd_maxsz(desc));\n+}\n+\n+void HELPER(gvec_luti4_b)(void *vd, void *vn, void *vm, uint32_t desc)\n+{\n+ unsigned part = simd_data(desc);\n+ unsigned vl = simd_oprsz(desc);\n+ unsigned elements = vl / 8;\n+ unsigned ibase = elements * part;\n+ ARMVectorReg scratch;\n+\n+ do_lut_b(&scratch, vm, vn, elements, ibase, 0, 4, 8, 1);\n+ memcpy(vd, &scratch, vl);\n+ clear_tail(vd, vl, simd_maxsz(desc));\n+}\n+\n+void HELPER(gvec_luti4_h)(void *vd, void *vn, void *vm, uint32_t desc)\n+{\n+ unsigned part = simd_data(desc);\n+ unsigned vl = simd_oprsz(desc);\n+ unsigned elements = vl / 16;\n+ unsigned ibase = elements * part;\n+ ARMVectorReg scratch;\n+\n+ do_lut_h(&scratch, vm, vn, elements, ibase, 0, 2, 16, 1);\n+ memcpy(vd, &scratch, vl);\n+ clear_tail(vd, vl, simd_maxsz(desc));\n+}\ndiff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode\nindex a9cf259b9b..6aea3ce89f 100644\n--- a/target/arm/tcg/a64.decode\n+++ b/target/arm/tcg/a64.decode\n@@ -1344,6 +1344,12 @@ EXT_q 0110 1110 00 0 rm:5 0 imm:4 0 rn:5 rd:5\n \n TBL_TBX 0 q:1 00 1110 000 rm:5 0 len:2 tbx:1 00 rn:5 rd:5\n \n+LUTI2_1b 0100 1110 100 rm:5 0 idx:2 100 rn:5 rd:5 &rrx_e esz=0\n+LUTI2_1h 0100 1110 110 rm:5 0 idx:3 00 rn:5 rd:5 &rrx_e esz=1\n+\n+LUTI4_1b 0100 1110 010 rm:5 0 idx:1 1000 rn:5 rd:5 &rrx_e esz=0\n+LUTI4_2h 0100 1110 010 rm:5 0 idx:2 100 rn:5 rd:5 &rrx_e esz=1\n+\n # Advanced SIMD Permute\n \n UZP1 0.00 1110 .. 0 ..... 0 001 10 ..... ..... @qrrr_e\n", "prefixes": [ "v4", "36/60" ] }