Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/1.2/patches/2234684/?format=api
{ "id": 2234684, "url": "http://patchwork.ozlabs.org/api/1.2/patches/2234684/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260507234413.643512-19-richard.henderson@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.2/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260507234413.643512-19-richard.henderson@linaro.org>", "list_archive_url": null, "date": "2026-05-07T23:43:31", "name": "[v4,18/60] target/arm: Implement FSCALE for AdvSIMD", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "a34fa907e5c87046a0b4eb51b362a4ec68396688", "submitter": { "id": 72104, "url": "http://patchwork.ozlabs.org/api/1.2/people/72104/?format=api", "name": "Richard Henderson", "email": "richard.henderson@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260507234413.643512-19-richard.henderson@linaro.org/mbox/", "series": [ { "id": 503296, "url": "http://patchwork.ozlabs.org/api/1.2/series/503296/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=503296", "date": "2026-05-07T23:43:14", "name": "target/arm: Implement FEAT_FP8", "version": 4, "mbox": "http://patchwork.ozlabs.org/series/503296/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2234684/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2234684/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=MPQznC7y;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4gBTWs0jc6z1yKm\n\tfor <incoming@patchwork.ozlabs.org>; Fri, 08 May 2026 09:50:17 +1000 (AEST)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1wL8OT-0000Ot-At; Thu, 07 May 2026 19:44:37 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <richard.henderson@linaro.org>)\n id 1wL8OQ-0000Ll-6W\n for qemu-devel@nongnu.org; Thu, 07 May 2026 19:44:34 -0400", "from mail-ot1-x32e.google.com ([2607:f8b0:4864:20::32e])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from <richard.henderson@linaro.org>)\n id 1wL8OO-00014X-HV\n for qemu-devel@nongnu.org; Thu, 07 May 2026 19:44:33 -0400", "by mail-ot1-x32e.google.com with SMTP id\n 46e09a7af769-7de4a9cb8eeso1232849a34.0\n for <qemu-devel@nongnu.org>; Thu, 07 May 2026 16:44:32 -0700 (PDT)", "from stoup.attlocal.net ([2600:381:c938:6375:9641:bbb2:a93a:bb4c])\n by smtp.gmail.com with ESMTPSA id\n 46e09a7af769-7e367d8feb1sm84320a34.23.2026.05.07.16.44.30\n (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256);\n Thu, 07 May 2026 16:44:30 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=linaro.org; s=google; t=1778197471; x=1778802271; darn=nongnu.org;\n h=content-transfer-encoding:mime-version:references:in-reply-to\n :message-id:date:subject:cc:to:from:from:to:cc:subject:date\n :message-id:reply-to;\n bh=iofCuUxrv6R6S77RADDQbkOhUsY0jTM8gW3WKAb19LM=;\n b=MPQznC7yr8wtazVNeOCxnNuZW/m3T77sYUcBSxCExhz9SvPYglwvNNBzFow5zqc40O\n nn7dXHwJBQB5lQHkB9inFbNb0AMHzwMJnRsN23D9btD44aj0lDsX0LPaFeFYsSZZM/hC\n mwgtQH77/fDmnaPBTSDlVD6NlSrxwPXUvaskcmCs7muU0+E49A08fNACdS7tVQuOmDF4\n yxus5INt4kNj9fOw+J40poANuPlW6DHPqcwIMHQaoDOli6Tjb64IzdUSwWo0ErjG3IjY\n KByQcT8NdBaZ6E7TUKAT4mLUklcLojdc8YbpQbQzce6vFoTxC757rmEwB4CkZ37RjA+O\n w/Wg==", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=1e100.net; s=20251104; t=1778197471; x=1778802271;\n h=content-transfer-encoding:mime-version:references:in-reply-to\n :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from\n :to:cc:subject:date:message-id:reply-to;\n bh=iofCuUxrv6R6S77RADDQbkOhUsY0jTM8gW3WKAb19LM=;\n b=NRuLp+FbicCHoeiKq3V9LVIUf/BqFT30KS+T7tSV8hbfUwrCzhYTz8PDHgMrNz354S\n 4gDY98Vzrpa+U4xitozDXnAD7/slD0pJHQ7R1ffelPbcruqOiJg1P3aLrZryCxjS2+FJ\n nx61br4VhB3x/VrUUlWBcyJoBoQHpjoKAt4gxqdWSefabXR2di04cW3Fl0euvzjXnHYH\n cR/WvvDclny0p/GDm+BZh/9YItfPYofqaP22fNgbZCJ0rClDFttI7nekbInf4m42j5vN\n mZpF2Vmh0/reUb7uuB3oEGk0KFZTTMkFRSGhFRpIxUXX782S/Yb7aKGpywddX8NPrEcn\n 4ucA==", "X-Gm-Message-State": "AOJu0YztYx5zB5nQ8lmkamq/9k+YqXJZ1FfHyvjXPqjhkQVhpL4ugH+M\n l8KpD7RiyFbjhdYMQyWy2J5md80MBPPoDY1Bzqfwx1lPJh8t50VlnD2A9n/Gdyti0brWlw7J/Wl\n 3Vaqo", "X-Gm-Gg": "AeBDieu01ajgLsykCE6f1/4bpxrGcS74P2PAdQNfuelJNfzcKAYt1ouD9uIsrYKLtj1\n mZWCf0wrqNaA7sis8hCqZp12ykIFKbu9/0lw0YZujXo3kKC5AM+lX8TJBDpzXmRuFWUwfJKNbMO\n J0diC4ok0tgJZ51EKL+cZ0DytHGBEIIpcw150gQj32TAKbuYf667qvedymGTAtUJYeJZ8PQ3SKj\n ugt9rG/LTfMV7fmEQLOEDW8p89CPzlnb78mqxX2JNfSQqAisYKzfy1BTj1jTXCsRQE9YQ0lyp5H\n mjU41HCMf7e3zJT5VyUWeoMSaRGe9zmExaO5IFHByuj4wjdn+ki7j/BzvEJ+EbrzTkVNgcIxUFY\n AQhZ20aDF1JBo/951iJGqRDVhw1zNGz1HV4kdA1t1rTndV46rM2Cyn8hOBSPsLxpXpLYggXY2yJ\n hrhm3lpFQ9H/LkBd0Yex0P/lRpzzncPlM5CJM0DysAQRhmng==", "X-Received": "by 2002:a05:6830:3110:b0:7dc:c7aa:22bd with SMTP id\n 46e09a7af769-7e1deec720emr6759146a34.6.1778197471257;\n Thu, 07 May 2026 16:44:31 -0700 (PDT)", "From": "Richard Henderson <richard.henderson@linaro.org>", "To": "qemu-devel@nongnu.org", "Cc": "qemu-arm@nongnu.org", "Subject": "[PATCH v4 18/60] target/arm: Implement FSCALE for AdvSIMD", "Date": "Thu, 7 May 2026 18:43:31 -0500", "Message-ID": "<20260507234413.643512-19-richard.henderson@linaro.org>", "X-Mailer": "git-send-email 2.43.0", "In-Reply-To": "<20260507234413.643512-1-richard.henderson@linaro.org>", "References": "<20260507234413.643512-1-richard.henderson@linaro.org>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Received-SPF": "pass client-ip=2607:f8b0:4864:20::32e;\n envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x32e.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "Signed-off-by: Richard Henderson <richard.henderson@linaro.org>\n---\n target/arm/tcg/helper-a64-defs.h | 4 ++++\n target/arm/tcg/vec_internal.h | 4 ++++\n target/arm/tcg/translate-a64.c | 7 +++++++\n target/arm/tcg/vec_helper64.c | 16 ++++++++++++++++\n target/arm/tcg/a64.decode | 3 +++\n 5 files changed, 34 insertions(+)", "diff": "diff --git a/target/arm/tcg/helper-a64-defs.h b/target/arm/tcg/helper-a64-defs.h\nindex 215df1201b..b7880f773e 100644\n--- a/target/arm/tcg/helper-a64-defs.h\n+++ b/target/arm/tcg/helper-a64-defs.h\n@@ -152,6 +152,10 @@ DEF_HELPER_FLAGS_5(gvec_famin_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32\n DEF_HELPER_FLAGS_5(gvec_famax_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)\n DEF_HELPER_FLAGS_5(gvec_famin_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)\n \n+DEF_HELPER_FLAGS_5(gvec_fscale_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)\n+DEF_HELPER_FLAGS_5(gvec_fscale_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)\n+DEF_HELPER_FLAGS_5(gvec_fscale_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)\n+\n #ifndef CONFIG_USER_ONLY\n DEF_HELPER_2(exception_return, void, env, i64)\n #endif\ndiff --git a/target/arm/tcg/vec_internal.h b/target/arm/tcg/vec_internal.h\nindex cc2691b2f6..68b1116171 100644\n--- a/target/arm/tcg/vec_internal.h\n+++ b/target/arm/tcg/vec_internal.h\n@@ -345,6 +345,10 @@ float32 float32_famin(float32, float32, float_status *);\n float64 float64_famax(float64, float64, float_status *);\n float64 float64_famin(float64, float64, float_status *);\n \n+#define float16_fscale float16_scalbn\n+#define float32_fscale float32_scalbn\n+float64 float64_fscale(float64, int64_t, float_status *);\n+\n /*\n * Decode helper functions for predicate as counter.\n */\ndiff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c\nindex d2a4b0fadc..ac18ceeeab 100644\n--- a/target/arm/tcg/translate-a64.c\n+++ b/target/arm/tcg/translate-a64.c\n@@ -6496,6 +6496,13 @@ static gen_helper_gvec_3_ptr * const f_vector_famin[3] = {\n };\n TRANS_FEAT(FAMIN, aa64_faminmax, do_fp3_vector, a, 0, f_vector_famin)\n \n+static gen_helper_gvec_3_ptr * const f_vector_fscale[3] = {\n+ gen_helper_gvec_fscale_h,\n+ gen_helper_gvec_fscale_s,\n+ gen_helper_gvec_fscale_d,\n+};\n+TRANS_FEAT(FSCALE, aa64_f8cvt, do_fp3_vector, a, 0, f_vector_fscale)\n+\n static bool do_fmlal(DisasContext *s, arg_qrrr_e *a, bool is_s, bool is_2)\n {\n if (fp_access_check(s)) {\ndiff --git a/target/arm/tcg/vec_helper64.c b/target/arm/tcg/vec_helper64.c\nindex b5ad67b5e0..5479d98daf 100644\n--- a/target/arm/tcg/vec_helper64.c\n+++ b/target/arm/tcg/vec_helper64.c\n@@ -175,3 +175,19 @@ DO_3OP(gvec_famax_s, float32_famax, float32)\n DO_3OP(gvec_famin_s, float32_famin, float32)\n DO_3OP(gvec_famax_d, float64_famax, float64)\n DO_3OP(gvec_famin_d, float64_famin, float64)\n+\n+float64 float64_fscale(float64 n, int64_t m, float_status *s)\n+{\n+ /*\n+ * Given the 'int' parameter of float64_scalbn, we have to saturate\n+ * the 'int64_t' parameter of the operation to some value. Since\n+ * float64 has an 11-bit exponent, saturating to 12 bits is sufficient\n+ * to ensure that DBL_TRUE_MIN can be made to overflow.\n+ */\n+ int sat_m = MIN(MAX(m, -0xfff), 0xfff);\n+ return float64_scalbn(n, sat_m, s);\n+}\n+\n+DO_3OP(gvec_fscale_h, float16_fscale, int16_t)\n+DO_3OP(gvec_fscale_s, float32_fscale, int32_t)\n+DO_3OP(gvec_fscale_d, float64_fscale, int64_t)\ndiff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode\nindex 666a293540..02c7264cb9 100644\n--- a/target/arm/tcg/a64.decode\n+++ b/target/arm/tcg/a64.decode\n@@ -1198,6 +1198,9 @@ FAMAX 0.00 1110 1.1 ..... 11011 1 ..... ..... @qrrr_sd\n FAMIN 0.10 1110 110 ..... 00011 1 ..... ..... @qrrr_h\n FAMIN 0.10 1110 1.1 ..... 11011 1 ..... ..... @qrrr_sd\n \n+FSCALE 0.10 1110 110 ..... 00111 1 ..... ..... @qrrr_h\n+FSCALE 0.10 1110 1.1 ..... 11111 1 ..... ..... @qrrr_sd\n+\n ### Advanced SIMD scalar x indexed element\n \n FMUL_si 0101 1111 00 .. .... 1001 . 0 ..... ..... @rrx_h\n", "prefixes": [ "v4", "18/60" ] }