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GET /api/1.2/patches/2234683/?format=api
{ "id": 2234683, "url": "http://patchwork.ozlabs.org/api/1.2/patches/2234683/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260507234413.643512-46-richard.henderson@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.2/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260507234413.643512-46-richard.henderson@linaro.org>", "list_archive_url": null, "date": "2026-05-07T23:43:58", "name": "[v4,45/60] target/arm: Implement FMLALB, FMLALT (FP8 to FP16) for SVE", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "60332435fbdd3bfd4ad5d861b9198d9009d13b61", "submitter": { "id": 72104, "url": "http://patchwork.ozlabs.org/api/1.2/people/72104/?format=api", "name": "Richard Henderson", "email": "richard.henderson@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260507234413.643512-46-richard.henderson@linaro.org/mbox/", "series": [ { "id": 503296, "url": "http://patchwork.ozlabs.org/api/1.2/series/503296/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=503296", "date": "2026-05-07T23:43:14", "name": "target/arm: Implement FEAT_FP8", "version": 4, "mbox": "http://patchwork.ozlabs.org/series/503296/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2234683/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2234683/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=U1T60c2N;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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helo=mail-oo1-xc34.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "Signed-off-by: Richard Henderson <richard.henderson@linaro.org>\n---\n target/arm/cpu-features.h | 5 +++++\n target/arm/tcg/translate-sve.c | 33 +++++++++++++++++++++++++++++++++\n target/arm/tcg/sve.decode | 7 +++++++\n 3 files changed, 45 insertions(+)", "diff": "diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h\nindex dcbd839d2d..e5e249d824 100644\n--- a/target/arm/cpu-features.h\n+++ b/target/arm/cpu-features.h\n@@ -1539,6 +1539,11 @@ static inline bool isar_feature_aa64_sve_b16b16(const ARMISARegisters *id)\n return FIELD_EX64_IDREG(id, ID_AA64ZFR0, B16B16);\n }\n \n+static inline bool isar_feature_aa64_ssve_f8fma(const ARMISARegisters *id)\n+{\n+ return FIELD_EX64_IDREG(id, ID_AA64SMFR0, SF8FMA);\n+}\n+\n static inline bool isar_feature_aa64_sme_b16b16(const ARMISARegisters *id)\n {\n return FIELD_EX64_IDREG(id, ID_AA64SMFR0, B16B16);\ndiff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c\nindex ea0d66178e..aa785fa0c3 100644\n--- a/target/arm/tcg/translate-sve.c\n+++ b/target/arm/tcg/translate-sve.c\n@@ -8336,3 +8336,36 @@ static bool trans_LUTI4_2h(DisasContext *s, arg_LUTI4_2h *a)\n }\n return true;\n }\n+\n+static bool do_fmla_fp8(DisasContext *s, arg_rxx *a, gen_helper_gvec_3_ptr *fn)\n+{\n+ bool fp8fma = dc_isar_feature(aa64_f8fma, s);\n+ bool ssve_fp8fma = dc_isar_feature(aa64_ssve_f8fma, s);\n+ bool ok = false;\n+\n+ /* Feature detection and enabling are complex here. */\n+ if (!(ssve_fp8fma || (fp8fma && dc_isar_feature(aa64_sve2, s)))) {\n+ return false;\n+ }\n+ if (fpmr_access_check(s)) {\n+ if (fp8fma) {\n+ s->is_nonstreaming = !ssve_fp8fma;\n+ ok = sve_access_check(s);\n+ } else {\n+ ok = sme_sm_enabled_check(s);\n+ }\n+ }\n+\n+ if (ok) {\n+ unsigned vsz = vec_full_reg_size(s);\n+ tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, a->rd),\n+ vec_full_reg_offset(s, a->rn),\n+ vec_full_reg_offset(s, a->rm),\n+ tcg_env, vsz, vsz,\n+ a->idxn | (a->idxm << 2), fn);\n+ }\n+ return true;\n+}\n+\n+TRANS(FMLAL_hb, do_fmla_fp8, a, gen_helper_gvec_fmla_hb)\n+TRANS(FMLAL_idx_hb, do_fmla_fp8, a, gen_helper_gvec_fmla_idx_hb)\ndiff --git a/target/arm/tcg/sve.decode b/target/arm/tcg/sve.decode\nindex e2106fc7f5..71ec09393c 100644\n--- a/target/arm/tcg/sve.decode\n+++ b/target/arm/tcg/sve.decode\n@@ -29,6 +29,7 @@\n %imm9_16_10 16:s6 10:3\n %size_23 23:2\n %dtype_23_13 23:2 13:2\n+%index4_19_10 19:2 10:2\n %index3_22_19 22:1 19:2\n %index3_22_17 22:1 17:2\n %index3_22_12 22:2 12:1\n@@ -73,6 +74,7 @@\n &rri rd rn imm\n &rr_dbm rd rn dbm\n &rrri rd rn rm imm\n+&rxx rd rn rm idxn idxm\n &rri_esz rd rn imm esz\n &rrri_esz rd rn rm imm esz\n &rrr_esz rd rn rm esz\n@@ -1864,6 +1866,8 @@ BFMLALT_zzzw 01100100 11 1 ..... 10 0 00 1 ..... ..... @rda_rn_rm_ex esz=2\n BFMLSLB_zzzw 01100100 11 1 ..... 10 1 00 0 ..... ..... @rda_rn_rm_ex esz=2\n BFMLSLT_zzzw 01100100 11 1 ..... 10 1 00 1 ..... ..... @rda_rn_rm_ex esz=2\n \n+FMLAL_hb 01100100 10 1 rm:5 100 idxn:1 10 rn:5 rd:5 &rxx idxm=0\n+\n ### SVE2 floating-point dot-product\n FDOT_zzzz 01100100 00 1 ..... 10 0 00 0 ..... ..... @rda_rn_rm_ex esz=2\n BFDOT_zzzz 01100100 01 1 ..... 10 0 00 0 ..... ..... @rda_rn_rm_ex esz=2\n@@ -1880,6 +1884,9 @@ BFMLALT_zzxw 01100100 11 1 ..... 0100.1 ..... ..... @rrxr_3a esz=2\n BFMLSLB_zzxw 01100100 11 1 ..... 0110.0 ..... ..... @rrxr_3a esz=2\n BFMLSLT_zzxw 01100100 11 1 ..... 0110.1 ..... ..... @rrxr_3a esz=2\n \n+FMLAL_idx_hb 01100100 idxn:1 01 .. rm:3 0101 .. rn:5 rd:5 \\\n+ &rxx idxm=%index4_19_10\n+\n ### SVE2 floating-point dot-product (indexed)\n \n FDOT_zzxz 01100100 00 1 ..... 010000 ..... ..... @rrxr_2 esz=2\n", "prefixes": [ "v4", "45/60" ] }