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GET /api/1.2/patches/2234678/?format=api
{ "id": 2234678, "url": "http://patchwork.ozlabs.org/api/1.2/patches/2234678/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260507234413.643512-20-richard.henderson@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.2/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260507234413.643512-20-richard.henderson@linaro.org>", "list_archive_url": null, "date": "2026-05-07T23:43:32", "name": "[v4,19/60] target/arm: Implement FSCALE for SME", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "e48206ef67012bbffe9ae5a7e92a138e2a089988", "submitter": { "id": 72104, "url": "http://patchwork.ozlabs.org/api/1.2/people/72104/?format=api", "name": "Richard Henderson", "email": "richard.henderson@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260507234413.643512-20-richard.henderson@linaro.org/mbox/", "series": [ { "id": 503296, "url": "http://patchwork.ozlabs.org/api/1.2/series/503296/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=503296", "date": "2026-05-07T23:43:14", "name": "target/arm: Implement FEAT_FP8", "version": 4, "mbox": "http://patchwork.ozlabs.org/series/503296/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2234678/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2234678/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=S9m5O8VM;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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helo=mail-ot1-x32a.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "Signed-off-by: Richard Henderson <richard.henderson@linaro.org>\n---\n target/arm/cpu-features.h | 5 +++++\n target/arm/tcg/translate-sme.c | 15 +++++++++++++--\n target/arm/tcg/sme.decode | 6 ++++++\n 3 files changed, 24 insertions(+), 2 deletions(-)", "diff": "diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h\nindex 3758bd19c2..69bc9bf6c7 100644\n--- a/target/arm/cpu-features.h\n+++ b/target/arm/cpu-features.h\n@@ -1616,6 +1616,11 @@ static inline bool isar_feature_aa64_sme2_faminmax(const ARMISARegisters *id)\n return isar_feature_aa64_sme2(id) && isar_feature_aa64_faminmax(id);\n }\n \n+static inline bool isar_feature_aa64_sme2_f8cvt(const ARMISARegisters *id)\n+{\n+ return isar_feature_aa64_sme2(id) && isar_feature_aa64_f8cvt(id);\n+}\n+\n static inline bool isar_feature_aa64_sve_i8mm(const ARMISARegisters *id)\n {\n return isar_feature_aa64_sve(id) && isar_feature_aa64_sme_sve_i8mm(id);\ndiff --git a/target/arm/tcg/translate-sme.c b/target/arm/tcg/translate-sme.c\nindex a67501226f..e2d17de165 100644\n--- a/target/arm/tcg/translate-sme.c\n+++ b/target/arm/tcg/translate-sme.c\n@@ -707,9 +707,12 @@ static bool do_z2z_n1_fpst(DisasContext *s, arg_z2z_en *a,\n {\n int esz = a->esz, n, dn, vsz, mofs;\n bool overlap = false;\n- gen_helper_gvec_3_ptr *fn;\n+ gen_helper_gvec_3_ptr *fn = fns[esz];\n TCGv_ptr fpst;\n \n+ if (fn == NULL) {\n+ return false;\n+ }\n /* These insns use MO_8 to encode BFloat16. */\n if (esz == MO_8 && !dc_isar_feature(aa64_sme_b16b16, s)) {\n return false;\n@@ -719,7 +722,6 @@ static bool do_z2z_n1_fpst(DisasContext *s, arg_z2z_en *a,\n }\n \n fpst = fpstatus_ptr(esz == MO_16 ? FPST_A64_F16 : FPST_A64);\n- fn = fns[esz];\n n = a->n;\n dn = a->zdn;\n mofs = vec_full_reg_offset(s, a->zm);\n@@ -831,6 +833,15 @@ static gen_helper_gvec_3_ptr * const f_vector_famin[4] = {\n };\n TRANS_FEAT(FAMIN_nn, aa64_sme2_faminmax, do_z2z_nn_fpst, a, f_vector_famin)\n \n+static gen_helper_gvec_3_ptr * const f_vector_fscale[4] = {\n+ NULL,\n+ gen_helper_gvec_fscale_h,\n+ gen_helper_gvec_fscale_s,\n+ gen_helper_gvec_fscale_d,\n+};\n+TRANS_FEAT(FSCALE_n1, aa64_sme2_f8cvt, do_z2z_n1_fpst, a, f_vector_fscale)\n+TRANS_FEAT(FSCALE_nn, aa64_sme2_f8cvt, do_z2z_nn_fpst, a, f_vector_fscale)\n+\n /* Add/Sub vector Z[m] to each Z[n*N] with result in ZA[d*N]. */\n static bool do_azz_n1(DisasContext *s, arg_azz_n *a, int esz,\n GVecGen3FnVar *fn)\ndiff --git a/target/arm/tcg/sme.decode b/target/arm/tcg/sme.decode\nindex 9dec7318a4..ee874be1a6 100644\n--- a/target/arm/tcg/sme.decode\n+++ b/target/arm/tcg/sme.decode\n@@ -250,6 +250,9 @@ ADD_n1 1100000 1 .. 10 .... 1010.0 11000 .... 0 @z2z_4x1\n SQDMULH_n1 1100000 1 .. 10 .... 1010.1 00000 .... 0 @z2z_2x1\n SQDMULH_n1 1100000 1 .. 10 .... 1010.1 00000 .... 0 @z2z_4x1\n \n+FSCALE_n1 1100000 1 .. 10 .... 1010.0 01100 .... 0 @z2z_2x1\n+FSCALE_n1 1100000 1 .. 10 .... 1010.0 01100 .... 0 @z2z_4x1\n+\n ### SME2 Multi-vector Multiple Vectors SVE Destructive\n \n %zm_ax2 17:4 !function=times_2\n@@ -291,6 +294,9 @@ FAMAX_nn 1100000 1 .. 1 ..... 1011.0 01010 .... 0 @z2z_4x4\n FAMIN_nn 1100000 1 .. 1 ..... 1011.0 01010 .... 1 @z2z_2x2\n FAMIN_nn 1100000 1 .. 1 ..... 1011.0 01010 .... 1 @z2z_4x4\n \n+FSCALE_nn 1100000 1 .. 1 ..... 1011.0 01100 .... 0 @z2z_2x2\n+FSCALE_nn 1100000 1 .. 1 ..... 1011.0 01100 .... 0 @z2z_4x4\n+\n ### SME2 Multi-vector Multiple and Single Array Vectors\n \n &azz_n n off rv zn zm\n", "prefixes": [ "v4", "19/60" ] }