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GET /api/1.2/patches/2234677/?format=api
{ "id": 2234677, "url": "http://patchwork.ozlabs.org/api/1.2/patches/2234677/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260507234413.643512-24-richard.henderson@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.2/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260507234413.643512-24-richard.henderson@linaro.org>", "list_archive_url": null, "date": "2026-05-07T23:43:36", "name": "[v4,23/60] target/arm: Implement BF1CVT, BF1CVTLT, BF2CVT, BF2CVTLT for SVE", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "172f880da8318f9d8adc09a9aa12410e938aa2d3", "submitter": { "id": 72104, "url": "http://patchwork.ozlabs.org/api/1.2/people/72104/?format=api", "name": "Richard Henderson", "email": "richard.henderson@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260507234413.643512-24-richard.henderson@linaro.org/mbox/", "series": [ { "id": 503296, "url": "http://patchwork.ozlabs.org/api/1.2/series/503296/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=503296", "date": "2026-05-07T23:43:14", "name": "target/arm: Implement FEAT_FP8", "version": 4, "mbox": "http://patchwork.ozlabs.org/series/503296/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2234677/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2234677/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=rrhql2T8;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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helo=mail-ot1-x32e.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "Signed-off-by: Richard Henderson <richard.henderson@linaro.org>\n---\n target/arm/cpu-features.h | 6 ++++++\n target/arm/tcg/helper-fp8-defs.h | 1 +\n target/arm/tcg/fp8_helper.c | 16 ++++++++++++++++\n target/arm/tcg/translate-sve.c | 23 +++++++++++++++++++++++\n target/arm/tcg/sve.decode | 6 ++++++\n 5 files changed, 52 insertions(+)", "diff": "diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h\nindex 69bc9bf6c7..c1f092b690 100644\n--- a/target/arm/cpu-features.h\n+++ b/target/arm/cpu-features.h\n@@ -1637,6 +1637,12 @@ isar_feature_aa64_sme2_or_sve2_faminmax(const ARMISARegisters *id)\n return isar_feature_aa64_sme2_or_sve2(id) && isar_feature_aa64_faminmax(id);\n }\n \n+static inline bool\n+isar_feature_aa64_sme2_or_sve2_f8cvt(const ARMISARegisters *id)\n+{\n+ return isar_feature_aa64_sme2_or_sve2(id) && isar_feature_aa64_f8cvt(id);\n+}\n+\n /*\n * Feature tests for \"does this exist in either 32-bit or 64-bit?\"\n */\ndiff --git a/target/arm/tcg/helper-fp8-defs.h b/target/arm/tcg/helper-fp8-defs.h\nindex 0caaf63749..18ff483bb0 100644\n--- a/target/arm/tcg/helper-fp8-defs.h\n+++ b/target/arm/tcg/helper-fp8-defs.h\n@@ -4,3 +4,4 @@\n */\n \n DEF_HELPER_FLAGS_4(advsimd_bfcvtl, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)\n+DEF_HELPER_FLAGS_4(sve2_bfcvt, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)\ndiff --git a/target/arm/tcg/fp8_helper.c b/target/arm/tcg/fp8_helper.c\nindex 7c8c4d6e06..ceb36bc926 100644\n--- a/target/arm/tcg/fp8_helper.c\n+++ b/target/arm/tcg/fp8_helper.c\n@@ -124,3 +124,19 @@ void HELPER(advsimd_bfcvtl)(void *vd, void *vn, CPUARMState *env, uint32_t desc)\n fp8_finish(env, &ctx);\n clear_tail(vd, 16, simd_maxsz(desc));\n }\n+\n+void HELPER(sve2_bfcvt)(void *vd, void *vn, CPUARMState *env, uint32_t desc)\n+{\n+ FP8Context ctx = fp8_src_start(env, desc, 0x3f);\n+ fp8_input_fn *input_fmt = fp8_input_fmt[ctx.f8fmt];\n+ uint8_t *n = vn;\n+ uint16_t *d = vd;\n+ size_t nelem = simd_oprsz(desc) / 2;\n+\n+ for (size_t i = 0; i < nelem; ++i) {\n+ d[H2(i)] = fcvt_fp8_to_b16(n[H1(2 * i + ctx.high)],\n+ input_fmt, ctx.scale, &ctx.stat);\n+ }\n+\n+ fp8_finish(env, &ctx);\n+}\ndiff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c\nindex db32230595..9bab5feb93 100644\n--- a/target/arm/tcg/translate-sve.c\n+++ b/target/arm/tcg/translate-sve.c\n@@ -21,6 +21,7 @@\n #include \"cpu.h\"\n #include \"helper-sme.h\"\n #include \"helper-sve.h\"\n+#include \"helper-fp8.h\"\n #include \"translate.h\"\n #include \"translate-a64.h\"\n #include \"tcg/tcg-op.h\"\n@@ -4067,6 +4068,28 @@ TRANS_FEAT(FRSQRTE, aa64_sme_or_sve, gen_gvec_fpst_ah_arg_zz,\n s->fpcr_ah && dc_isar_feature(aa64_rpres, s) ?\n frsqrte_rpres_fns[a->esz] : frsqrte_fns[a->esz], a, 0)\n \n+static bool do_f8cvt(DisasContext *s, arg_rr_esz *a,\n+ gen_helper_gvec_2_ptr *fn, bool issrc2, bool isodd)\n+{\n+ if (fpmr_access_check(s) && sve_access_check(s)) {\n+ unsigned vsz = vec_full_reg_size(s);\n+ tcg_gen_gvec_2_ptr(vec_full_reg_offset(s, a->rd),\n+ vec_full_reg_offset(s, a->rn),\n+ tcg_env, vsz, vsz,\n+ issrc2 | (isodd << 1) | (FPST_A64 << 2), fn);\n+ }\n+ return true;\n+}\n+\n+TRANS_FEAT(BF1CVT, aa64_sme2_or_sve2_f8cvt, do_f8cvt, a,\n+ gen_helper_sve2_bfcvt, false, false)\n+TRANS_FEAT(BF2CVT, aa64_sme2_or_sve2_f8cvt, do_f8cvt, a,\n+ gen_helper_sve2_bfcvt, true, false)\n+TRANS_FEAT(BF1CVTLT, aa64_sme2_or_sve2_f8cvt, do_f8cvt, a,\n+ gen_helper_sve2_bfcvt, false, true)\n+TRANS_FEAT(BF2CVTLT, aa64_sme2_or_sve2_f8cvt, do_f8cvt, a,\n+ gen_helper_sve2_bfcvt, true, true)\n+\n /*\n *** SVE Floating Point Compare with Zero Group\n */\ndiff --git a/target/arm/tcg/sve.decode b/target/arm/tcg/sve.decode\nindex 078a085a79..e7984fa8e0 100644\n--- a/target/arm/tcg/sve.decode\n+++ b/target/arm/tcg/sve.decode\n@@ -108,6 +108,7 @@\n # Two operand\n @pd_pn ........ esz:2 .. .... ....... rn:4 . rd:4 &rr_esz\n @rd_rn ........ esz:2 ...... ...... rn:5 rd:5 &rr_esz\n+@rd_rn_e0 ........ .. ...... ...... rn:5 rd:5 &rr_esz esz=0\n @rd_rnx2 ........ ... ..... ...... ..... rd:5 &rr_esz rn=%rn_ax2\n \n # Two operand with governing predicate, flags setting\n@@ -1090,6 +1091,11 @@ FMINQV 01100100 .. 010 111 101 ... ..... ..... @rd_pg_rn\n FRECPE 01100101 .. 001 110 001100 ..... ..... @rd_rn\n FRSQRTE 01100101 .. 001 111 001100 ..... ..... @rd_rn\n \n+BF1CVT 01100101 00 001 000 001110 ..... ..... @rd_rn_e0\n+BF2CVT 01100101 00 001 000 001111 ..... ..... @rd_rn_e0\n+BF1CVTLT 01100101 00 001 001 001110 ..... ..... @rd_rn_e0\n+BF2CVTLT 01100101 00 001 001 001111 ..... ..... @rd_rn_e0\n+\n ### SVE FP Compare with Zero Group\n \n FCMGE_ppz0 01100101 .. 0100 00 001 ... ..... 0 .... @pd_pg_rn\n", "prefixes": [ "v4", "23/60" ] }