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GET /api/1.2/patches/2234676/?format=api
{ "id": 2234676, "url": "http://patchwork.ozlabs.org/api/1.2/patches/2234676/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260507234413.643512-30-richard.henderson@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.2/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260507234413.643512-30-richard.henderson@linaro.org>", "list_archive_url": null, "date": "2026-05-07T23:43:42", "name": "[v4,29/60] target/arm: Implement BFCVTN for SVE", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "9234a58a9a7be673c3320012972720770e32b35c", "submitter": { "id": 72104, "url": "http://patchwork.ozlabs.org/api/1.2/people/72104/?format=api", "name": "Richard Henderson", "email": "richard.henderson@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260507234413.643512-30-richard.henderson@linaro.org/mbox/", "series": [ { "id": 503296, "url": "http://patchwork.ozlabs.org/api/1.2/series/503296/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=503296", "date": "2026-05-07T23:43:14", "name": "target/arm: Implement FEAT_FP8", "version": 4, "mbox": "http://patchwork.ozlabs.org/series/503296/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2234676/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2234676/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=oSvKupWl;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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helo=mail-ot1-x333.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "Signed-off-by: Richard Henderson <richard.henderson@linaro.org>\n---\n target/arm/tcg/helper-fp8-defs.h | 2 +\n target/arm/tcg/fp8_helper.c | 85 ++++++++++++++++++++++++++++++++\n target/arm/tcg/translate-sve.c | 3 ++\n target/arm/tcg/sve.decode | 2 +\n 4 files changed, 92 insertions(+)", "diff": "diff --git a/target/arm/tcg/helper-fp8-defs.h b/target/arm/tcg/helper-fp8-defs.h\nindex b5dc2b7064..bbc8d69e28 100644\n--- a/target/arm/tcg/helper-fp8-defs.h\n+++ b/target/arm/tcg/helper-fp8-defs.h\n@@ -12,3 +12,5 @@ DEF_HELPER_FLAGS_4(advsimd_fcvtl_hb, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)\n DEF_HELPER_FLAGS_4(sve2_fcvt_hb, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)\n DEF_HELPER_FLAGS_4(sme2_fcvt_hb, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)\n DEF_HELPER_FLAGS_4(sme2_fcvtl_hb, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)\n+\n+DEF_HELPER_FLAGS_4(sve2_bfcvtn_bh, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)\ndiff --git a/target/arm/tcg/fp8_helper.c b/target/arm/tcg/fp8_helper.c\nindex fce02f68fa..400deee612 100644\n--- a/target/arm/tcg/fp8_helper.c\n+++ b/target/arm/tcg/fp8_helper.c\n@@ -78,6 +78,14 @@ static FP8Context fp8_src_start(CPUARMState *env, uint32_t desc, int scale_mask)\n return fp8_start(env, desc, f8fmt, scale);\n }\n \n+static FP8Context fp8_dst_start(CPUARMState *env, uint32_t desc)\n+{\n+ uint64_t fpmr = env->vfp.fpmr;\n+ FPMRType f8fmt = FIELD_EX64(fpmr, FPMR, F8D);\n+ int scale = FIELD_SEX64(fpmr, FPMR, NSCALE);\n+\n+ return fp8_start(env, desc, f8fmt, scale);\n+}\n \n static FloatParts64 fp8_invalid_input(uint8_t x, float_status *s)\n {\n@@ -113,6 +121,60 @@ static float16 fcvt_fp8_to_f16(uint8_t x, fp8_input_fn *f8fmt,\n return float16_round_pack_canonical(&p, s);\n }\n \n+typedef uint8_t fcvt_fp8_output_fn(FloatParts64 *, int, bool, float_status *);\n+\n+static uint8_t fcvt_fp8_invalid_output(FloatParts64 *p, int scale,\n+ bool saturate, float_status *s)\n+{\n+ /* Invalid output format writes -1 and raises invalid. */\n+ float_raise(float_flag_invalid, s);\n+ return 0xff;\n+}\n+\n+static uint8_t fcvt_fp8_e4m3_output(FloatParts64 *p, int scale,\n+ bool saturate, float_status *s)\n+{\n+ *p = parts64_scalbn(p, scale, s);\n+ /*\n+ * Saturating Inf -> Max handled in uncanon_e4m3_overflow\n+ * because there is no infinity encoding.\n+ */\n+ return float8_e4m3_round_pack_canonical(p, s, saturate);\n+}\n+\n+static uint8_t fcvt_fp8_e5m2_output(FloatParts64 *p, int scale,\n+ bool saturate, float_status *s)\n+{\n+ /*\n+ * Because e5m2 has an infinity encoding, we need to handle\n+ * conversion of Inf -> Max manually. This will be converted\n+ * to the actual maximum value during rounding.\n+ */\n+ if (unlikely(p->cls == float_class_inf)) {\n+ if (saturate) {\n+ p->cls = float_class_normal;\n+ p->exp = INT_MAX;\n+ p->frac = -1;\n+ }\n+ } else {\n+ *p = parts64_scalbn(p, scale, s);\n+ }\n+ return float8_e5m2_round_pack_canonical(p, s, saturate);\n+}\n+\n+static fcvt_fp8_output_fn * const fcvt_fp8_output_fmt[8] = {\n+ [0 ... 7] = fcvt_fp8_invalid_output,\n+ [OFP8_E5M2] = fcvt_fp8_e5m2_output,\n+ [OFP8_E4M3] = fcvt_fp8_e4m3_output,\n+};\n+\n+static uint8_t fcvt_b16_to_fp8(bfloat16 x, fcvt_fp8_output_fn *f8fmt,\n+ int scale, bool saturate, float_status *s)\n+{\n+ FloatParts64 p = bfloat16_unpack_canonical(x, s);\n+ return f8fmt(&p, scale, saturate, s);\n+}\n+\n void HELPER(advsimd_bfcvtl)(void *vd, void *vn, CPUARMState *env, uint32_t desc)\n {\n FP8Context ctx = fp8_src_start(env, desc, 0x3f);\n@@ -279,3 +341,26 @@ void HELPER(sme2_fcvtl_hb)(void *vd, void *vn, CPUARMState *env, uint32_t desc)\n \n fp8_finish(env, &ctx);\n }\n+\n+void HELPER(sve2_bfcvtn_bh)(void *vd, void *vn, CPUARMState *env, uint32_t desc)\n+{\n+ FP8Context ctx = fp8_dst_start(env, desc);\n+ fcvt_fp8_output_fn *output_fmt = fcvt_fp8_output_fmt[ctx.f8fmt];\n+ uint16_t *n0 = vn;\n+ uint16_t *n1 = vn + sizeof(ARMVectorReg);\n+ uint8_t *d = vd;\n+ size_t oprsz = simd_oprsz(desc);\n+ size_t nelem = oprsz / 2;\n+ bool osc = FIELD_EX64(env->vfp.fpmr, FPMR, OSC);\n+\n+ for (size_t i = 0; i < nelem; ++i) {\n+ bfloat16 e0 = n0[H2(i)];\n+ bfloat16 e1 = n1[H2(i)];\n+ d[H1(2 * i + 0)] = fcvt_b16_to_fp8(e0, output_fmt,\n+ ctx.scale, osc, &ctx.stat);\n+ d[H1(2 * i + 1)] = fcvt_b16_to_fp8(e1, output_fmt,\n+ ctx.scale, osc, &ctx.stat);\n+ }\n+\n+ fp8_finish(env, &ctx);\n+}\ndiff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c\nindex 5200f3d034..7276d9c44a 100644\n--- a/target/arm/tcg/translate-sve.c\n+++ b/target/arm/tcg/translate-sve.c\n@@ -4099,6 +4099,9 @@ TRANS_FEAT(BF1CVTLT, aa64_sme2_or_sve2_f8cvt, do_f8cvt, a,\n TRANS_FEAT(BF2CVTLT, aa64_sme2_or_sve2_f8cvt, do_f8cvt, a,\n gen_helper_sve2_bfcvt, true, true)\n \n+TRANS_FEAT(BFCVTN, aa64_sme2_or_sve2_f8cvt, do_f8cvt,\n+ a, gen_helper_sve2_bfcvtn_bh, false, false)\n+\n /*\n *** SVE Floating Point Compare with Zero Group\n */\ndiff --git a/target/arm/tcg/sve.decode b/target/arm/tcg/sve.decode\nindex ca110f4bc1..b6ef8ed8de 100644\n--- a/target/arm/tcg/sve.decode\n+++ b/target/arm/tcg/sve.decode\n@@ -1101,6 +1101,8 @@ BF2CVT 01100101 00 001 000 001111 ..... ..... @rd_rn_e0\n BF1CVTLT 01100101 00 001 001 001110 ..... ..... @rd_rn_e0\n BF2CVTLT 01100101 00 001 001 001111 ..... ..... @rd_rn_e0\n \n+BFCVTN 01100101 00 001 010 001110 ....0 ..... @rd_rnx2 esz=1\n+\n ### SVE FP Compare with Zero Group\n \n FCMGE_ppz0 01100101 .. 0100 00 001 ... ..... 0 .... @pd_pg_rn\n", "prefixes": [ "v4", "29/60" ] }