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GET /api/1.2/patches/2234672/?format=api
{ "id": 2234672, "url": "http://patchwork.ozlabs.org/api/1.2/patches/2234672/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260507234413.643512-33-richard.henderson@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.2/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260507234413.643512-33-richard.henderson@linaro.org>", "list_archive_url": null, "date": "2026-05-07T23:43:45", "name": "[v4,32/60] target/arm: Implement FCVTN (16- to 8-bit fp) for SVE", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "fa0a82948282bd886139e843e8d51794020e3ca5", "submitter": { "id": 72104, "url": "http://patchwork.ozlabs.org/api/1.2/people/72104/?format=api", "name": "Richard Henderson", "email": "richard.henderson@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260507234413.643512-33-richard.henderson@linaro.org/mbox/", "series": [ { "id": 503296, "url": "http://patchwork.ozlabs.org/api/1.2/series/503296/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=503296", "date": "2026-05-07T23:43:14", "name": "target/arm: Implement FEAT_FP8", "version": 4, "mbox": "http://patchwork.ozlabs.org/series/503296/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2234672/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2234672/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=t/rdhqnN;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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helo=mail-ot1-x329.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "Signed-off-by: Richard Henderson <richard.henderson@linaro.org>\n---\n target/arm/tcg/helper-fp8-defs.h | 1 +\n target/arm/tcg/fp8_helper.c | 23 +++++++++++++++++++++++\n target/arm/tcg/translate-sve.c | 2 ++\n target/arm/tcg/sve.decode | 1 +\n 4 files changed, 27 insertions(+)", "diff": "diff --git a/target/arm/tcg/helper-fp8-defs.h b/target/arm/tcg/helper-fp8-defs.h\nindex 023a49e12f..e67fb191c2 100644\n--- a/target/arm/tcg/helper-fp8-defs.h\n+++ b/target/arm/tcg/helper-fp8-defs.h\n@@ -16,5 +16,6 @@ DEF_HELPER_FLAGS_4(sme2_fcvtl_hb, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)\n DEF_HELPER_FLAGS_4(sve2_bfcvtn_bh, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)\n \n DEF_HELPER_FLAGS_5(gvec_fcvt_bh, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32)\n+DEF_HELPER_FLAGS_4(sve2_fcvtn_bh, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)\n \n DEF_HELPER_FLAGS_5(advsimd_fcvt_bs, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32)\ndiff --git a/target/arm/tcg/fp8_helper.c b/target/arm/tcg/fp8_helper.c\nindex 2252d2c526..6588768ba1 100644\n--- a/target/arm/tcg/fp8_helper.c\n+++ b/target/arm/tcg/fp8_helper.c\n@@ -409,6 +409,29 @@ void HELPER(gvec_fcvt_bh)(void *vd, void *vn, void *vm,\n clear_tail(vd, oprsz, simd_maxsz(desc));\n }\n \n+void HELPER(sve2_fcvtn_bh)(void *vd, void *vn, CPUARMState *env, uint32_t desc)\n+{\n+ FP8Context ctx = fp8_dst_start(env, desc);\n+ fcvt_fp8_output_fn *output_fmt = fcvt_fp8_output_fmt[ctx.f8fmt];\n+ uint16_t *n0 = vn;\n+ uint16_t *n1 = vn + sizeof(ARMVectorReg);\n+ uint8_t *d = vd;\n+ bool osc = FIELD_EX64(env->vfp.fpmr, FPMR, OSC);\n+ size_t oprsz = simd_oprsz(desc);\n+ size_t nelem = oprsz / 2;\n+\n+ for (size_t i = 0; i < nelem; ++i) {\n+ float16 e0 = n0[H2(i)];\n+ float16 e1 = n1[H2(i)];\n+ d[H1(2 * i + 0)] = fcvt_f16_to_fp8(e0, output_fmt,\n+ ctx.scale, osc, &ctx.stat);\n+ d[H1(2 * i + 1)] = fcvt_f16_to_fp8(e1, output_fmt,\n+ ctx.scale, osc, &ctx.stat);\n+ }\n+\n+ fp8_finish(env, &ctx);\n+}\n+\n void HELPER(advsimd_fcvt_bs)(void *vd, void *vn, void *vm,\n CPUARMState *env, uint32_t desc)\n {\ndiff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c\nindex 7276d9c44a..c7fcf27183 100644\n--- a/target/arm/tcg/translate-sve.c\n+++ b/target/arm/tcg/translate-sve.c\n@@ -4099,6 +4099,8 @@ TRANS_FEAT(BF1CVTLT, aa64_sme2_or_sve2_f8cvt, do_f8cvt, a,\n TRANS_FEAT(BF2CVTLT, aa64_sme2_or_sve2_f8cvt, do_f8cvt, a,\n gen_helper_sve2_bfcvt, true, true)\n \n+TRANS_FEAT(FCVTN, aa64_sme2_or_sve2_f8cvt, do_f8cvt,\n+ a, gen_helper_sve2_fcvtn_bh, false, false)\n TRANS_FEAT(BFCVTN, aa64_sme2_or_sve2_f8cvt, do_f8cvt,\n a, gen_helper_sve2_bfcvtn_bh, false, false)\n \ndiff --git a/target/arm/tcg/sve.decode b/target/arm/tcg/sve.decode\nindex b6ef8ed8de..806953bc35 100644\n--- a/target/arm/tcg/sve.decode\n+++ b/target/arm/tcg/sve.decode\n@@ -1101,6 +1101,7 @@ BF2CVT 01100101 00 001 000 001111 ..... ..... @rd_rn_e0\n BF1CVTLT 01100101 00 001 001 001110 ..... ..... @rd_rn_e0\n BF2CVTLT 01100101 00 001 001 001111 ..... ..... @rd_rn_e0\n \n+FCVTN 01100101 00 001 010 001100 ....0 ..... @rd_rnx2 esz=1\n BFCVTN 01100101 00 001 010 001110 ....0 ..... @rd_rnx2 esz=1\n \n ### SVE FP Compare with Zero Group\n", "prefixes": [ "v4", "32/60" ] }