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GET /api/1.2/patches/2234664/?format=api
{ "id": 2234664, "url": "http://patchwork.ozlabs.org/api/1.2/patches/2234664/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260507234413.643512-27-richard.henderson@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.2/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260507234413.643512-27-richard.henderson@linaro.org>", "list_archive_url": null, "date": "2026-05-07T23:43:39", "name": "[v4,26/60] target/arm: Implement F1CVTL, F1CVTL2, F2CVTL, F2CVTL2 for AdvSIMD", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "b5175f7e4a93e7555a1a95bcb074dae10e8c9998", "submitter": { "id": 72104, "url": "http://patchwork.ozlabs.org/api/1.2/people/72104/?format=api", "name": "Richard Henderson", "email": "richard.henderson@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260507234413.643512-27-richard.henderson@linaro.org/mbox/", "series": [ { "id": 503296, "url": "http://patchwork.ozlabs.org/api/1.2/series/503296/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=503296", "date": "2026-05-07T23:43:14", "name": "target/arm: Implement FEAT_FP8", "version": 4, "mbox": "http://patchwork.ozlabs.org/series/503296/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2234664/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2234664/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=WqehD04a;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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helo=mail-ot1-x32d.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "Signed-off-by: Richard Henderson <richard.henderson@linaro.org>\n---\n target/arm/tcg/helper-fp8-defs.h | 2 ++\n target/arm/tcg/fp8_helper.c | 29 +++++++++++++++++++++++++++++\n target/arm/tcg/translate-a64.c | 3 +++\n target/arm/tcg/a64.decode | 3 +++\n 4 files changed, 37 insertions(+)", "diff": "diff --git a/target/arm/tcg/helper-fp8-defs.h b/target/arm/tcg/helper-fp8-defs.h\nindex 966f83d796..718463422b 100644\n--- a/target/arm/tcg/helper-fp8-defs.h\n+++ b/target/arm/tcg/helper-fp8-defs.h\n@@ -7,3 +7,5 @@ DEF_HELPER_FLAGS_4(advsimd_bfcvtl, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)\n DEF_HELPER_FLAGS_4(sve2_bfcvt, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)\n DEF_HELPER_FLAGS_4(sme2_bfcvt_hb, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)\n DEF_HELPER_FLAGS_4(sme2_bfcvtl_hb, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)\n+\n+DEF_HELPER_FLAGS_4(advsimd_fcvtl_hb, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)\ndiff --git a/target/arm/tcg/fp8_helper.c b/target/arm/tcg/fp8_helper.c\nindex 427ec4cc3d..90f17f9e10 100644\n--- a/target/arm/tcg/fp8_helper.c\n+++ b/target/arm/tcg/fp8_helper.c\n@@ -105,6 +105,14 @@ static bfloat16 fcvt_fp8_to_b16(uint8_t x, fp8_input_fn *f8fmt,\n return bfloat16_round_pack_canonical(&p, s);\n }\n \n+static float16 fcvt_fp8_to_f16(uint8_t x, fp8_input_fn *f8fmt,\n+ int scale, float_status *s)\n+{\n+ FloatParts64 p = f8fmt(x, s);\n+ p = parts64_scalbn(&p, scale, s);\n+ return float16_round_pack_canonical(&p, s);\n+}\n+\n void HELPER(advsimd_bfcvtl)(void *vd, void *vn, CPUARMState *env, uint32_t desc)\n {\n FP8Context ctx = fp8_src_start(env, desc, 0x3f);\n@@ -125,6 +133,27 @@ void HELPER(advsimd_bfcvtl)(void *vd, void *vn, CPUARMState *env, uint32_t desc)\n clear_tail(vd, 16, simd_maxsz(desc));\n }\n \n+void HELPER(advsimd_fcvtl_hb)(void *vd, void *vn,\n+ CPUARMState *env, uint32_t desc)\n+{\n+ FP8Context ctx = fp8_src_start(env, desc, 0xf);\n+ fp8_input_fn *input_fmt = fp8_input_fmt[ctx.f8fmt];\n+ uint8_t *n = vn, scratch[16];\n+ float16 *d = vd;\n+\n+ if (vd == vn) {\n+ n = memcpy(scratch, vn, 16);\n+ }\n+ n += ctx.high * 8;\n+\n+ for (size_t i = 0; i < 8; ++i) {\n+ d[H2(i)] = fcvt_fp8_to_f16(n[H1(i)], input_fmt, ctx.scale, &ctx.stat);\n+ }\n+\n+ fp8_finish(env, &ctx);\n+ clear_tail(vd, 16, simd_maxsz(desc));\n+}\n+\n void HELPER(sve2_bfcvt)(void *vd, void *vn, CPUARMState *env, uint32_t desc)\n {\n FP8Context ctx = fp8_src_start(env, desc, 0x3f);\ndiff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c\nindex 085e7e3b95..565053a1a4 100644\n--- a/target/arm/tcg/translate-a64.c\n+++ b/target/arm/tcg/translate-a64.c\n@@ -10643,6 +10643,9 @@ static bool do_f8cvt(DisasContext *s, arg_qrr_e *a,\n return true;\n }\n \n+TRANS_FEAT(F1CVTL, aa64_f8cvt, do_f8cvt, a, gen_helper_advsimd_fcvtl_hb, false)\n+TRANS_FEAT(F2CVTL, aa64_f8cvt, do_f8cvt, a, gen_helper_advsimd_fcvtl_hb, true)\n+\n TRANS_FEAT(BF1CVTL, aa64_f8cvt, do_f8cvt, a, gen_helper_advsimd_bfcvtl, false)\n TRANS_FEAT(BF2CVTL, aa64_f8cvt, do_f8cvt, a, gen_helper_advsimd_bfcvtl, true)\n \ndiff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode\nindex b7aac148f2..26d31d0a33 100644\n--- a/target/arm/tcg/a64.decode\n+++ b/target/arm/tcg/a64.decode\n@@ -1910,6 +1910,9 @@ URSQRTE_v 0.10 1110 101 00001 11001 0 ..... ..... @qrr_s\n \n FCVTL_v 0.00 1110 0.1 00001 01111 0 ..... ..... @qrr_sd\n \n+F1CVTL 0.10 1110 001 00001 01111 0 ..... ..... @qrr_h\n+F2CVTL 0.10 1110 011 00001 01111 0 ..... ..... @qrr_h\n+\n BF1CVTL 0.10 1110 101 00001 01111 0 ..... ..... @qrr_h\n BF2CVTL 0.10 1110 111 00001 01111 0 ..... ..... @qrr_h\n \n", "prefixes": [ "v4", "26/60" ] }