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GET /api/1.2/patches/2234662/?format=api
{ "id": 2234662, "url": "http://patchwork.ozlabs.org/api/1.2/patches/2234662/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260507234413.643512-7-richard.henderson@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.2/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260507234413.643512-7-richard.henderson@linaro.org>", "list_archive_url": null, "date": "2026-05-07T23:43:19", "name": "[v4,06/60] target/arm: Update SCR bits for Arm ARM M.a.a", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "80331f9d419d469f9b0646915f2742197f0c0380", "submitter": { "id": 72104, "url": "http://patchwork.ozlabs.org/api/1.2/people/72104/?format=api", "name": "Richard Henderson", "email": "richard.henderson@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260507234413.643512-7-richard.henderson@linaro.org/mbox/", "series": [ { "id": 503296, "url": "http://patchwork.ozlabs.org/api/1.2/series/503296/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=503296", "date": "2026-05-07T23:43:14", "name": "target/arm: Implement FEAT_FP8", "version": 4, "mbox": "http://patchwork.ozlabs.org/series/503296/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2234662/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2234662/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=Qb8laVCv;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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helo=mail-ot1-x32e.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "Signed-off-by: Richard Henderson <richard.henderson@linaro.org>\n---\n target/arm/cpu.h | 11 +++++++++++\n 1 file changed, 11 insertions(+)", "diff": "diff --git a/target/arm/cpu.h b/target/arm/cpu.h\nindex 0b9755533b..aeba70e6fc 100644\n--- a/target/arm/cpu.h\n+++ b/target/arm/cpu.h\n@@ -1795,6 +1795,17 @@ static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)\n #define SCR_AIEN (1ULL << 46)\n #define SCR_GPF (1ULL << 48)\n #define SCR_MECEN (1ULL << 49)\n+#define SCR_ENFPM (1ULL << 50)\n+#define SCR_TMEA (1ULL << 51)\n+#define SCR_TWERR (1ULL << 52)\n+#define SCR_PFAREN (1ULL << 53)\n+#define SCR_SRMASKEN (1ULL << 54)\n+#define SCR_ENIDCP128 (1ULL << 55)\n+#define SCR_DSE (1ULL << 57)\n+#define SCR_ENDSE (1ULL << 58)\n+#define SCR_FGTEN2 (1ULL << 59)\n+#define SCR_HDBSSEN (1ULL << 60)\n+#define SCR_HACEBSEN (1ULL << 61)\n #define SCR_NSE (1ULL << 62)\n \n /* GCSCR_ELx fields */\n", "prefixes": [ "v4", "06/60" ] }