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GET /api/1.2/patches/2234652/?format=api
{ "id": 2234652, "url": "http://patchwork.ozlabs.org/api/1.2/patches/2234652/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260507234413.643512-36-richard.henderson@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.2/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260507234413.643512-36-richard.henderson@linaro.org>", "list_archive_url": null, "date": "2026-05-07T23:43:48", "name": "[v4,35/60] target/arm: Implement FCVT, FCVTN (FP32 to FP8) for SME", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "191d4f9e6b4db43fc90f67dfd53ac724cffe649b", "submitter": { "id": 72104, "url": "http://patchwork.ozlabs.org/api/1.2/people/72104/?format=api", "name": "Richard Henderson", "email": "richard.henderson@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260507234413.643512-36-richard.henderson@linaro.org/mbox/", "series": [ { "id": 503296, "url": "http://patchwork.ozlabs.org/api/1.2/series/503296/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=503296", "date": "2026-05-07T23:43:14", "name": "target/arm: Implement FEAT_FP8", "version": 4, "mbox": "http://patchwork.ozlabs.org/series/503296/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2234652/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2234652/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=TbGH1QRC;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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helo=mail-ot1-x32a.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "Signed-off-by: Richard Henderson <richard.henderson@linaro.org>\n---\n target/arm/tcg/helper-fp8-defs.h | 2 ++\n target/arm/tcg/fp8_helper.c | 59 ++++++++++++++++++++++++++++++++\n target/arm/tcg/translate-sme.c | 3 ++\n target/arm/tcg/sme.decode | 3 ++\n 4 files changed, 67 insertions(+)", "diff": "diff --git a/target/arm/tcg/helper-fp8-defs.h b/target/arm/tcg/helper-fp8-defs.h\nindex 5863a6dbb8..36ae977431 100644\n--- a/target/arm/tcg/helper-fp8-defs.h\n+++ b/target/arm/tcg/helper-fp8-defs.h\n@@ -21,3 +21,5 @@ DEF_HELPER_FLAGS_4(sve2_fcvtn_bh, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)\n DEF_HELPER_FLAGS_5(advsimd_fcvt_bs, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32)\n DEF_HELPER_FLAGS_4(sve2_fcvtnb_bs, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)\n DEF_HELPER_FLAGS_4(sve2_fcvtnt_bs, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)\n+DEF_HELPER_FLAGS_4(sme2_fcvt_bs, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)\n+DEF_HELPER_FLAGS_4(sme2_fcvtn_bs, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)\ndiff --git a/target/arm/tcg/fp8_helper.c b/target/arm/tcg/fp8_helper.c\nindex 55b09c689c..d7c1ff97b7 100644\n--- a/target/arm/tcg/fp8_helper.c\n+++ b/target/arm/tcg/fp8_helper.c\n@@ -504,3 +504,62 @@ void HELPER(sve2_fcvtnt_bs)(void *vd, void *vn, CPUARMState *env, uint32_t desc)\n \n fp8_finish(env, &ctx);\n }\n+\n+void HELPER(sme2_fcvt_bs)(void *vd, void *vn, CPUARMState *env, uint32_t desc)\n+{\n+ ARMVectorReg scratch[4];\n+ FP8Context ctx = fp8_dst_start(env, desc);\n+ fcvt_fp8_output_fn *output_fmt = fcvt_fp8_output_fmt[ctx.f8fmt];\n+ uint32_t *n = vn;\n+ uint8_t *d = vd;\n+ bool osc = FIELD_EX64(env->vfp.fpmr, FPMR, OSC);\n+ size_t oprsz = simd_oprsz(desc);\n+ size_t nelem = oprsz / 4;\n+ size_t stride = sizeof(ARMVectorReg) / 4;\n+\n+ if (vectors_overlap(vd, 1, vn, 4)) {\n+ n = memcpy(scratch, vn, sizeof(scratch));\n+ }\n+\n+ for (size_t i = 0; i < nelem; i++) {\n+ for (size_t j = 0; j < 4; j++) {\n+ d[H1(i + nelem * j)] = fcvt_f32_to_fp8(n[H4(i) + stride * j],\n+ output_fmt, ctx.scale,\n+ osc, &ctx.stat);\n+ }\n+ }\n+\n+ fp8_finish(env, &ctx);\n+}\n+\n+void HELPER(sme2_fcvtn_bs)(void *vd, void *vn, CPUARMState *env, uint32_t desc)\n+{\n+ FP8Context ctx = fp8_dst_start(env, desc);\n+ fcvt_fp8_output_fn *output_fmt = fcvt_fp8_output_fmt[ctx.f8fmt];\n+ uint32_t *n0 = vn;\n+ uint32_t *n1 = vn + sizeof(ARMVectorReg);\n+ uint32_t *n2 = vn + sizeof(ARMVectorReg) * 2;\n+ uint32_t *n3 = vn + sizeof(ARMVectorReg) * 3;\n+ uint8_t *d = vd;\n+ bool osc = FIELD_EX64(env->vfp.fpmr, FPMR, OSC);\n+ size_t oprsz = simd_oprsz(desc);\n+ size_t nelem = oprsz / 4;\n+\n+ for (size_t i = 0; i < nelem; ++i) {\n+ float32 e0 = n0[H4(i)];\n+ float32 e1 = n1[H4(i)];\n+ float32 e2 = n2[H4(i)];\n+ float32 e3 = n3[H4(i)];\n+\n+ d[H1(4 * i + 0)] = fcvt_f32_to_fp8(e0, output_fmt,\n+ ctx.scale, osc, &ctx.stat);\n+ d[H1(4 * i + 1)] = fcvt_f32_to_fp8(e1, output_fmt,\n+ ctx.scale, osc, &ctx.stat);\n+ d[H1(4 * i + 2)] = fcvt_f32_to_fp8(e2, output_fmt,\n+ ctx.scale, osc, &ctx.stat);\n+ d[H1(4 * i + 3)] = fcvt_f32_to_fp8(e3, output_fmt,\n+ ctx.scale, osc, &ctx.stat);\n+ }\n+\n+ fp8_finish(env, &ctx);\n+}\ndiff --git a/target/arm/tcg/translate-sme.c b/target/arm/tcg/translate-sme.c\nindex 050c3cfefe..2f79c458e1 100644\n--- a/target/arm/tcg/translate-sme.c\n+++ b/target/arm/tcg/translate-sme.c\n@@ -1572,6 +1572,9 @@ static bool trans_FCVT_bh(DisasContext *s, arg_zz_n *a)\n return true;\n }\n \n+TRANS_FEAT(FCVT_bs, aa64_sme2_f8cvt, do_f8cvt, a, gen_helper_sme2_fcvt_bs, 0)\n+TRANS_FEAT(FCVTN_bs, aa64_sme2_f8cvt, do_f8cvt, a, gen_helper_sme2_fcvtn_bs, 0)\n+\n static bool do_zipuzp_4(DisasContext *s, arg_zz_e *a,\n gen_helper_gvec_2 * const fn[5])\n {\ndiff --git a/target/arm/tcg/sme.decode b/target/arm/tcg/sme.decode\nindex a02bcc0e22..2b9e41a75a 100644\n--- a/target/arm/tcg/sme.decode\n+++ b/target/arm/tcg/sme.decode\n@@ -865,6 +865,9 @@ BF2CVTL 11000001 111 00110 111000 ..... ....1 @zz_2x1\n \n FCVT_bh 11000001 001 00100 111000 ....0 ..... @zz_1x2\n \n+FCVT_bs 11000001 001 10100 111000 ...00 ..... @zz_1x4\n+FCVTN_bs 11000001 001 10100 111000 ...01 ..... @zz_1x4\n+\n ZIP_4 11000001 esz:2 1 10110 111000 ...00 ... 00 \\\n &zz_e zd=%zd_ax4 zn=%zn_ax4\n ZIP_4 11000001 001 10111 111000 ...00 ... 00 \\\n", "prefixes": [ "v4", "35/60" ] }