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GET /api/1.2/patches/2234639/?format=api
{ "id": 2234639, "url": "http://patchwork.ozlabs.org/api/1.2/patches/2234639/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260507234413.643512-11-richard.henderson@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.2/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260507234413.643512-11-richard.henderson@linaro.org>", "list_archive_url": null, "date": "2026-05-07T23:43:23", "name": "[v4,10/60] target/arm: Enable EnFPM bits for FEAT_FPMR", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "9d4b3a35a37fabb68d54fcc13a685340538be697", "submitter": { "id": 72104, "url": "http://patchwork.ozlabs.org/api/1.2/people/72104/?format=api", "name": "Richard Henderson", "email": "richard.henderson@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260507234413.643512-11-richard.henderson@linaro.org/mbox/", "series": [ { "id": 503296, "url": "http://patchwork.ozlabs.org/api/1.2/series/503296/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=503296", "date": "2026-05-07T23:43:14", "name": "target/arm: Implement FEAT_FP8", "version": 4, "mbox": "http://patchwork.ozlabs.org/series/503296/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2234639/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2234639/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=e3LzRDAb;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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helo=mail-ot1-x32f.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "Signed-off-by: Richard Henderson <richard.henderson@linaro.org>\n---\n target/arm/helper.c | 9 +++++++++\n 1 file changed, 9 insertions(+)", "diff": "diff --git a/target/arm/helper.c b/target/arm/helper.c\nindex 304db1a479..7a17fd39e5 100644\n--- a/target/arm/helper.c\n+++ b/target/arm/helper.c\n@@ -787,6 +787,9 @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)\n if (cpu_isar_feature(aa64_mec, cpu)) {\n valid_mask |= SCR_MECEN;\n }\n+ if (cpu_isar_feature(aa64_fpmr, cpu)) {\n+ valid_mask |= SCR_ENFPM;\n+ }\n } else {\n valid_mask &= ~(SCR_RW | SCR_ST);\n if (cpu_isar_feature(aa32_ras, cpu)) {\n@@ -3953,6 +3956,9 @@ static void hcrx_write(CPUARMState *env, const ARMCPRegInfo *ri,\n if (cpu_isar_feature(aa64_gcs, cpu)) {\n valid_mask |= HCRX_GCSEN;\n }\n+ if (cpu_isar_feature(aa64_fpmr, cpu)) {\n+ valid_mask |= HCRX_ENFPM;\n+ }\n \n /* Clear RES0 bits. */\n env->cp15.hcrx_el2 = value & valid_mask;\n@@ -4026,6 +4032,9 @@ uint64_t arm_hcrx_el2_eff(CPUARMState *env)\n if (cpu_isar_feature(aa64_gcs, cpu)) {\n hcrx |= HCRX_GCSEN;\n }\n+ if (cpu_isar_feature(aa64_fpmr, cpu)) {\n+ hcrx |= HCRX_ENFPM;\n+ }\n return hcrx;\n }\n if (arm_feature(env, ARM_FEATURE_EL3) && !(env->cp15.scr_el3 & SCR_HXEN)) {\n", "prefixes": [ "v4", "10/60" ] }