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GET /api/1.2/patches/2234556/?format=api
{ "id": 2234556, "url": "http://patchwork.ozlabs.org/api/1.2/patches/2234556/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20260507-b4-mmu-unmap-fixes-v3-4-aac7726d87d5@linaro.org/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/1.2/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260507-b4-mmu-unmap-fixes-v3-4-aac7726d87d5@linaro.org>", "list_archive_url": null, "date": "2026-05-07T19:58:11", "name": "[v3,4/4] armv8: mmu: fix and optimise explicitly unmapping regions", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "ad10eb4bec3e3c8e8f92032820a4ca23b1a0b6df", "submitter": { "id": 90679, "url": "http://patchwork.ozlabs.org/api/1.2/people/90679/?format=api", "name": "Casey Connolly", "email": "casey.connolly@linaro.org" }, "delegate": { "id": 3651, "url": "http://patchwork.ozlabs.org/api/1.2/users/3651/?format=api", "username": "trini", "first_name": "Tom", "last_name": "Rini", "email": "trini@ti.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20260507-b4-mmu-unmap-fixes-v3-4-aac7726d87d5@linaro.org/mbox/", "series": [ { "id": 503261, "url": "http://patchwork.ozlabs.org/api/1.2/series/503261/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=503261", "date": "2026-05-07T19:58:07", "name": "armv8: mmu: fix region unmapping and optimise set_one_region()", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/503261/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2234556/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2234556/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=cRHXTv1l;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; 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charset=\"utf-8\"", "Content-Transfer-Encoding": "7bit", "Message-Id": "<20260507-b4-mmu-unmap-fixes-v3-4-aac7726d87d5@linaro.org>", "References": "<20260507-b4-mmu-unmap-fixes-v3-0-aac7726d87d5@linaro.org>", "In-Reply-To": "<20260507-b4-mmu-unmap-fixes-v3-0-aac7726d87d5@linaro.org>", "To": "u-boot@lists.denx.de", "Cc": "Tom Rini <trini@konsulko.com>, Anshul Dalal <anshuld@ti.com>,\n Casey Connolly <casey.connolly@linaro.org>,\n Ilias Apalodimas <ilias.apalodimas@linaro.org>, Dhruva Gole <d-gole@ti.com>,\n Mark Kettenis <kettenis@openbsd.org>,\n Patrice Chotard <patrice.chotard@foss.st.com>,\n Sumit Garg <sumit.garg@kernel.org>", "X-Mailer": "b4 0.16-dev", "X-Developer-Signature": "v=1; a=openpgp-sha256; l=4030;\n i=casey.connolly@linaro.org; h=from:subject:message-id;\n bh=JyKcHG3CDm6TiD3xkCztln04+LiDUlSBDyQYtXKquSg=;\n b=owGbwMvMwCFYaeA6f6eBkTjjabUkhsw/7+4cFTn31sfzvB3nNA5Jd//DB7VWOiXrSlhkT45r7\n vbbmPiqo5SFQZCDQVZMkUX8xDLLprWX7TW2L7gAM4eVCWQIAxenAEzEqJGRYWPW3u13hc6UrV8z\n O5bb+N9CYa6lde09qfJT5zseFyx9/4Thf4Sc2/YJ2iuenPh9KvnBhBi2971CLcsE1h7/xVHU4Op\n wLxIA", "X-Developer-Key": "i=casey.connolly@linaro.org; a=openpgp;\n fpr=83B24DA7FE145076BC38BB250CD904EB673A7C47", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.39", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<https://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>", "X-Virus-Scanned": "clamav-milter 0.103.8 at phobos.denx.de", "X-Virus-Status": "Clean" }, "content": "As more platforms start ensuring they explicitly unmap reserved-memory\nregions a few issues have appeared with how the existing dynamic mapping\ncode works. Fix these and get a small optimisation as well.\n\n1. Teach pte_type() to actually respect the PTE_TYPE_VALID bit\n2. Don't walk the TLB a second time if we call mmu_change_region_attr()\n with PTE_TYPE_FAULT (since it would just be a slow nop)\n3. Fix how set_one_region() decides to split blocks.\n\nToday set_one_region() will always split blocks until it reaches the\nsmallest granule size (4k) and then update all of these pages. This\nappears to be due to a big in how is_aligned() is implemented, since\nit only evaluates to true if addr and size are both multiples of the\ncurrent granule size, so a mapping aligned to 2M which is 4M in size\nwill cleanly result in 2 blocks being set, but a mapping aligned to\n2M which is 4M + 8k in size will result in blocks being split and 1026\nindividual pages being set.\n\nWhile for the address it is correct to enforce that it is aligned to\nthe current granule size, we only need to check if the region size is\ngreater than the current granule size. This allows us to simplify our\nsecond example above to only 4 entries being updated (assuming no blocks\nhave to be split) since we only need to update 2 blocks to map the first\n4M, drastically improving the best-case performance.\n\nIn the case where the address is 4k aligned rather than 2M aligned we\nwill still be restricted to mapping 4k pages until we reach 2M alignment\nwhere we could then map a larger 2M granule which previously would never\nhappen.\n\nSigned-off-by: Casey Connolly <casey.connolly@linaro.org>\n---\n arch/arm/cpu/armv8/cache_v8.c | 18 ++++++++++++++----\n 1 file changed, 14 insertions(+), 4 deletions(-)", "diff": "diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c\nindex bd839b2addb4..c3dd1c24d18a 100644\n--- a/arch/arm/cpu/armv8/cache_v8.c\n+++ b/arch/arm/cpu/armv8/cache_v8.c\n@@ -162,9 +162,9 @@ u64 get_tcr(u64 *pips, u64 *pva_bits)\n #define MAX_PTE_ENTRIES 512\n \n static int pte_type(u64 *pte)\n {\n-\treturn *pte & PTE_TYPE_MASK;\n+\treturn *pte & PTE_TYPE_VALID ? *pte & PTE_TYPE_MASK : PTE_TYPE_FAULT;\n }\n \n /* Returns the LSB number for a PTE on level <level> */\n static int level2shift(int level)\n@@ -980,11 +980,12 @@ u64 *__weak arch_get_page_table(void) {\n \n \treturn NULL;\n }\n \n+/* Checks if the current PTE is an aligned subset of the region */\n static bool is_aligned(u64 addr, u64 size, u64 align)\n {\n-\treturn !(addr & (align - 1)) && !(size & (align - 1));\n+\treturn !(addr & (align - 1)) && size >= align;\n }\n \n /* Use flag to indicate if attrs has more than d-cache attributes */\n static u64 set_one_region(u64 start, u64 size, u64 attrs, bool flag, int level)\n@@ -992,11 +993,16 @@ static u64 set_one_region(u64 start, u64 size, u64 attrs, bool flag, int level)\n \tint levelshift = level2shift(level);\n \tu64 levelsize = 1ULL << levelshift;\n \tu64 *pte = find_pte(start, level);\n \n-\t/* Can we can just modify the current level block PTE? */\n+\t/* Can we can just modify the current level block/page? */\n \tif (is_aligned(start, size, levelsize)) {\n-\t\tif (flag) {\n+\t\tif (attrs == PTE_TYPE_FAULT) {\n+\t\t\tif (pte_type(pte) == PTE_TYPE_TABLE)\n+\t\t\t\t*pte &= ~0;\n+\t\t\telse\n+\t\t\t\t*pte &= ~(PMD_ATTRMASK | PTE_TYPE_MASK | PTE_BLOCK_INNER_SHARE);\n+\t\t} else if (flag) {\n \t\t\t*pte &= ~PMD_ATTRMASK;\n \t\t\t*pte |= attrs & PMD_ATTRMASK;\n \t\t} else {\n \t\t\t*pte &= ~PMD_ATTRINDX_MASK;\n@@ -1099,8 +1105,12 @@ void mmu_change_region_attr(phys_addr_t addr, size_t size, u64 attrs)\n \tflush_dcache_range(gd->arch.tlb_addr,\n \t\t\t gd->arch.tlb_addr + gd->arch.tlb_size);\n \t__asm_invalidate_tlb_all();\n \n+\t/* If we were unmapping a region then we have nothing to make and can return. */\n+\tif (attrs == PTE_TYPE_FAULT)\n+\t\treturn;\n+\n \tmmu_change_region_attr_nobreak(addr, size, attrs);\n }\n \n int pgprot_set_attrs(phys_addr_t addr, size_t size, enum pgprot_attrs perm)\n", "prefixes": [ "v3", "4/4" ] }