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GET /api/1.2/patches/2234555/?format=api
{ "id": 2234555, "url": "http://patchwork.ozlabs.org/api/1.2/patches/2234555/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20260507-b4-mmu-unmap-fixes-v3-3-aac7726d87d5@linaro.org/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/1.2/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260507-b4-mmu-unmap-fixes-v3-3-aac7726d87d5@linaro.org>", "list_archive_url": null, "date": "2026-05-07T19:58:10", "name": "[v3,3/4] armv8: mmu: commonize the set_one_region() loop", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "3d952c83818426341beb81c97012c21392e842bd", "submitter": { "id": 90679, "url": "http://patchwork.ozlabs.org/api/1.2/people/90679/?format=api", "name": "Casey Connolly", "email": "casey.connolly@linaro.org" }, "delegate": { "id": 3651, "url": "http://patchwork.ozlabs.org/api/1.2/users/3651/?format=api", "username": "trini", "first_name": "Tom", "last_name": "Rini", "email": "trini@ti.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20260507-b4-mmu-unmap-fixes-v3-3-aac7726d87d5@linaro.org/mbox/", "series": [ { "id": 503261, "url": "http://patchwork.ozlabs.org/api/1.2/series/503261/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=503261", "date": "2026-05-07T19:58:07", "name": "armv8: mmu: fix region unmapping and optimise set_one_region()", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/503261/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2234555/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2234555/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=iLezBmJO;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; 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charset=\"utf-8\"", "Content-Transfer-Encoding": "7bit", "Message-Id": "<20260507-b4-mmu-unmap-fixes-v3-3-aac7726d87d5@linaro.org>", "References": "<20260507-b4-mmu-unmap-fixes-v3-0-aac7726d87d5@linaro.org>", "In-Reply-To": "<20260507-b4-mmu-unmap-fixes-v3-0-aac7726d87d5@linaro.org>", "To": "u-boot@lists.denx.de", "Cc": "Tom Rini <trini@konsulko.com>, Anshul Dalal <anshuld@ti.com>,\n Casey Connolly <casey.connolly@linaro.org>,\n Ilias Apalodimas <ilias.apalodimas@linaro.org>, Dhruva Gole <d-gole@ti.com>,\n Mark Kettenis <kettenis@openbsd.org>,\n Patrice Chotard <patrice.chotard@foss.st.com>,\n Sumit Garg <sumit.garg@kernel.org>", "X-Mailer": "b4 0.16-dev", "X-Developer-Signature": "v=1; a=openpgp-sha256; l=4658;\n i=casey.connolly@linaro.org; h=from:subject:message-id;\n bh=4qKXa9Bg0heRd74dhwDpOUr88fzn35KNXO4NS+24ZLg=;\n b=owGbwMvMwCFYaeA6f6eBkTjjabUkhsw/7+54LMvb9GxpzhwHaSNFDl8Rn9NdS0O56rcL7nf4d\n k2szP9NRykLgyAHg6yYIov4iWWWTWsv22tsX3ABZg4rE8gQBi5OAZjI8iRGhvXcC361XFyieNz3\n dfSsK7+4St7uv//uVLPvt1Tt++cStkYy/M/8wu/mojDlWfZ5+UMCXM8/bBZJuhHMVpolXT59yq8\n qJw8A", "X-Developer-Key": "i=casey.connolly@linaro.org; a=openpgp;\n fpr=83B24DA7FE145076BC38BB250CD904EB673A7C47", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.39", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<https://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>", "X-Virus-Scanned": "clamav-milter 0.103.8 at phobos.denx.de", "X-Virus-Status": "Clean" }, "content": "This loop is duplicated 3 times, put it into its own function and call\nit instead. This simplifies the logic in a few functions.\n\nSigned-off-by: Casey Connolly <casey.connolly@linaro.org>\n---\n arch/arm/cpu/armv8/cache_v8.c | 97 ++++++++++++++-----------------------------\n 1 file changed, 31 insertions(+), 66 deletions(-)", "diff": "diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c\nindex 36d337378fcd..bd839b2addb4 100644\n--- a/arch/arm/cpu/armv8/cache_v8.c\n+++ b/arch/arm/cpu/armv8/cache_v8.c\n@@ -1022,8 +1022,33 @@ static u64 set_one_region(u64 start, u64 size, u64 attrs, bool flag, int level)\n \t/* Roll on to the next page table level */\n \treturn 0;\n }\n \n+static void set_regions(u64 start, u64 size, u64 attrs, bool flag)\n+{\n+\tint level, levelstart;\n+\tu64 r, va_bits;\n+\tget_tcr(NULL, &va_bits);\n+\n+\tlevelstart = va_bits < 39 ? 1 : 0;\n+\n+\t/*\n+\t * Loop through the address range until we find a page granule that fits\n+\t * our alignment constraints, then set it to the new cache attributes\n+\t */\n+\twhile (size > 0) {\n+\t\tfor (level = levelstart; level < 4; level++) {\n+\t\t\tr = set_one_region(start, size, attrs, flag, level);\n+\t\t\tif (r) {\n+\t\t\t\t/* PTE successfully replaced */\n+\t\t\t\tsize -= r;\n+\t\t\t\tstart += r;\n+\t\t\t\tbreak;\n+\t\t\t}\n+\t\t}\n+\t}\n+}\n+\n void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,\n \t\t\t\t enum dcache_option option)\n {\n \tu64 attrs = PMD_ATTRINDX(option >> 2);\n@@ -1041,28 +1066,9 @@ void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,\n \t * we can safely modify our primary page tables and then switch back\n \t */\n \t__asm_switch_ttbr(gd->arch.tlb_emerg);\n \n-\t/*\n-\t * Loop through the address range until we find a page granule that fits\n-\t * our alignment constraints, then set it to the new cache attributes\n-\t */\n-\twhile (size > 0) {\n-\t\tint level;\n-\t\tu64 r;\n-\n-\t\tfor (level = 1; level < 4; level++) {\n-\t\t\t/* Set d-cache attributes only */\n-\t\t\tr = set_one_region(start, size, attrs, false, level);\n-\t\t\tif (r) {\n-\t\t\t\t/* PTE successfully replaced */\n-\t\t\t\tsize -= r;\n-\t\t\t\tstart += r;\n-\t\t\t\tbreak;\n-\t\t\t}\n-\t\t}\n-\n-\t}\n+\tset_regions(start, size, attrs, false);\n \n \t/* We're done modifying page tables, switch back to our primary ones */\n \t__asm_switch_ttbr(gd->arch.tlb_addr);\n \n@@ -1072,31 +1078,11 @@ void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,\n \t */\n \tflush_dcache_range(real_start, real_start + real_size);\n }\n \n-void mmu_change_region_attr_nobreak(phys_addr_t addr, size_t siz, u64 attrs)\n+void mmu_change_region_attr_nobreak(phys_addr_t addr, size_t size, u64 attrs)\n {\n-\tint level;\n-\tu64 r, size, start;\n-\n-\t/*\n-\t * Loop through the address range until we find a page granule that fits\n-\t * our alignment constraints and set the new permissions\n-\t */\n-\tstart = addr;\n-\tsize = siz;\n-\twhile (size > 0) {\n-\t\tfor (level = 1; level < 4; level++) {\n-\t\t\t/* Set PTE to new attributes */\n-\t\t\tr = set_one_region(start, size, attrs, true, level);\n-\t\t\tif (r) {\n-\t\t\t\t/* PTE successfully updated */\n-\t\t\t\tsize -= r;\n-\t\t\t\tstart += r;\n-\t\t\t\tbreak;\n-\t\t\t}\n-\t\t}\n-\t}\n+\tset_regions(addr, size, attrs, true);\n \tflush_dcache_range(gd->arch.tlb_addr,\n \t\t\t gd->arch.tlb_addr + gd->arch.tlb_size);\n \t__asm_invalidate_tlb_all();\n }\n@@ -1105,38 +1091,17 @@ void mmu_change_region_attr_nobreak(phys_addr_t addr, size_t siz, u64 attrs)\n * Modify MMU table for a region with updated PXN/UXN/Memory type/valid bits.\n * The procecess is break-before-make. The target region will be marked as\n * invalid during the process of changing.\n */\n-void mmu_change_region_attr(phys_addr_t addr, size_t siz, u64 attrs)\n+void mmu_change_region_attr(phys_addr_t addr, size_t size, u64 attrs)\n {\n-\tint level;\n-\tu64 r, size, start;\n-\n-\tstart = addr;\n-\tsize = siz;\n-\t/*\n-\t * Loop through the address range until we find a page granule that fits\n-\t * our alignment constraints, then set it to \"invalid\".\n-\t */\n-\twhile (size > 0) {\n-\t\tfor (level = 1; level < 4; level++) {\n-\t\t\t/* Set PTE to fault */\n-\t\t\tr = set_one_region(start, size, PTE_TYPE_FAULT, true,\n-\t\t\t\t\t level);\n-\t\t\tif (r) {\n-\t\t\t\t/* PTE successfully invalidated */\n-\t\t\t\tsize -= r;\n-\t\t\t\tstart += r;\n-\t\t\t\tbreak;\n-\t\t\t}\n-\t\t}\n-\t}\n+\tset_regions(addr, size, PTE_TYPE_FAULT, true);\n \n \tflush_dcache_range(gd->arch.tlb_addr,\n \t\t\t gd->arch.tlb_addr + gd->arch.tlb_size);\n \t__asm_invalidate_tlb_all();\n \n-\tmmu_change_region_attr_nobreak(addr, siz, attrs);\n+\tmmu_change_region_attr_nobreak(addr, size, attrs);\n }\n \n int pgprot_set_attrs(phys_addr_t addr, size_t size, enum pgprot_attrs perm)\n {\n", "prefixes": [ "v3", "3/4" ] }