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{
    "id": 2234527,
    "url": "http://patchwork.ozlabs.org/api/1.2/patches/2234527/?format=api",
    "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/23ed0db2-b70c-4278-b9f3-0c7189f51336@gmail.com/",
    "project": {
        "id": 18,
        "url": "http://patchwork.ozlabs.org/api/1.2/projects/18/?format=api",
        "name": "U-Boot",
        "link_name": "uboot",
        "list_id": "u-boot.lists.denx.de",
        "list_email": "u-boot@lists.denx.de",
        "web_url": null,
        "scm_url": null,
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        "list_archive_url": "",
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        "commit_url_format": ""
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    "msgid": "<23ed0db2-b70c-4278-b9f3-0c7189f51336@gmail.com>",
    "list_archive_url": null,
    "date": "2026-05-07T18:38:33",
    "name": "[v2,4/5] rockchip: Switch rk3368 boards to upstream devicetree",
    "commit_ref": null,
    "pull_url": null,
    "state": "new",
    "archived": false,
    "hash": "b132f1b3bb643f4016b690d1abd2e0dfa96d53f8",
    "submitter": {
        "id": 75645,
        "url": "http://patchwork.ozlabs.org/api/1.2/people/75645/?format=api",
        "name": "Johan Jonker",
        "email": "jbx6244@gmail.com"
    },
    "delegate": {
        "id": 93623,
        "url": "http://patchwork.ozlabs.org/api/1.2/users/93623/?format=api",
        "username": "kevery",
        "first_name": "Kever",
        "last_name": "Yang",
        "email": "ykai007@gmail.com"
    },
    "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/23ed0db2-b70c-4278-b9f3-0c7189f51336@gmail.com/mbox/",
    "series": [
        {
            "id": 503246,
            "url": "http://patchwork.ozlabs.org/api/1.2/series/503246/?format=api",
            "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=503246",
            "date": "2026-05-07T18:34:48",
            "name": "rockchip: Switch remaining boards to upstream devicetree",
            "version": 2,
            "mbox": "http://patchwork.ozlabs.org/series/503246/mbox/"
        }
    ],
    "comments": "http://patchwork.ozlabs.org/api/patches/2234527/comments/",
    "check": "pending",
    "checks": "http://patchwork.ozlabs.org/api/patches/2234527/checks/",
    "tags": {},
    "related": [],
    "headers": {
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        "Message-ID": "<23ed0db2-b70c-4278-b9f3-0c7189f51336@gmail.com>",
        "Date": "Thu, 7 May 2026 20:38:33 +0200",
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        "From": "Johan Jonker <jbx6244@gmail.com>",
        "Subject": "[PATCH v2 4/5] rockchip: Switch rk3368 boards to upstream devicetree",
        "To": "kever.yang@rock-chips.com",
        "Cc": "philipp.tomsich@vrull.eu, sjg@chromium.org, trini@konsulko.com,\n afaerber@suse.de, andy.yan@rock-chips.com, u-boot@lists.denx.de,\n quentin.schulz@cherry.de",
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    "content": "Switch rk3368 boards to upstream devicetree.\n\nSigned-off-by: Johan Jonker <jbx6244@gmail.com>\n---\n\nChanged V2:\nremoval in a separate patch\n---\n arch/arm/dts/Makefile           |    4 -\n arch/arm/dts/rk3368-geekbox.dts |  281 -------\n arch/arm/dts/rk3368-px5-evb.dts |  277 -------\n arch/arm/dts/rk3368-u-boot.dtsi |    4 +\n arch/arm/dts/rk3368.dtsi        | 1218 -------------------------------\n arch/arm/mach-rockchip/Kconfig  |    1 +\n configs/evb-px5_defconfig       |    2 +-\n configs/geekbox_defconfig       |    2 +-\n 8 files changed, 7 insertions(+), 1782 deletions(-)\n delete mode 100644 arch/arm/dts/rk3368-geekbox.dts\n delete mode 100644 arch/arm/dts/rk3368-px5-evb.dts\n delete mode 100644 arch/arm/dts/rk3368.dtsi\n\n--\n2.39.5",
    "diff": "diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile\nindex 39ab188c5435..cba252489bb1 100644\n--- a/arch/arm/dts/Makefile\n+++ b/arch/arm/dts/Makefile\n@@ -52,10 +52,6 @@ dtb-$(CONFIG_MACH_S900) += \\\n dtb-$(CONFIG_MACH_S700) += \\\n \ts700-cubieboard7.dtb\n\n-dtb-$(CONFIG_ROCKCHIP_RK3368) += \\\n-\trk3368-geekbox.dtb \\\n-\trk3368-px5-evb.dtb \\\n-\n dtb-$(CONFIG_ARCH_S5P4418) += \\\n \ts5p4418-nanopi2.dtb\n\ndiff --git a/arch/arm/dts/rk3368-geekbox.dts b/arch/arm/dts/rk3368-geekbox.dts\ndeleted file mode 100644\nindex 62aa97a0b8c9..000000000000\n--- a/arch/arm/dts/rk3368-geekbox.dts\n+++ /dev/null\n@@ -1,281 +0,0 @@\n-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)\n-/*\n- * Copyright (c) 2016 Andreas Färber\n- */\n-\n-/dts-v1/;\n-#include \"rk3368.dtsi\"\n-#include <dt-bindings/input/input.h>\n-\n-/ {\n-\tmodel = \"GeekBox\";\n-\tcompatible = \"geekbuying,geekbox\", \"rockchip,rk3368\";\n-\n-\taliases {\n-\t\tmmc0 = &emmc;\n-\t};\n-\n-\tchosen {\n-\t\tstdout-path = \"serial2:115200n8\";\n-\t};\n-\n-\tmemory@0 {\n-\t\tdevice_type = \"memory\";\n-\t\treg = <0x0 0x0 0x0 0x80000000>;\n-\t};\n-\n-\text_gmac: gmac-clk {\n-\t\tcompatible = \"fixed-clock\";\n-\t\tclock-frequency = <125000000>;\n-\t\tclock-output-names = \"ext_gmac\";\n-\t\t#clock-cells = <0>;\n-\t};\n-\n-\tir: ir-receiver {\n-\t\tcompatible = \"gpio-ir-receiver\";\n-\t\tgpios = <&gpio3 RK_PD6 GPIO_ACTIVE_LOW>;\n-\t\tpinctrl-names = \"default\";\n-\t\tpinctrl-0 = <&ir_int>;\n-\t};\n-\n-\tkeys: gpio-keys {\n-\t\tcompatible = \"gpio-keys\";\n-\t\tpinctrl-names = \"default\";\n-\t\tpinctrl-0 = <&pwr_key>;\n-\n-\t\tpower {\n-\t\t\tgpios = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>;\n-\t\t\tlabel = \"GPIO Power\";\n-\t\t\tlinux,code = <KEY_POWER>;\n-\t\t\twakeup-source;\n-\t\t};\n-\t};\n-\n-\tleds: gpio-leds {\n-\t\tcompatible = \"gpio-leds\";\n-\n-\t\tblue_led: led-0 {\n-\t\t\tgpios = <&gpio2 RK_PA2 GPIO_ACTIVE_HIGH>;\n-\t\t\tlabel = \"geekbox:blue:led\";\n-\t\t\tdefault-state = \"on\";\n-\t\t};\n-\n-\t\tred_led: led-1 {\n-\t\t\tgpios = <&gpio2 RK_PA3 GPIO_ACTIVE_HIGH>;\n-\t\t\tlabel = \"geekbox:red:led\";\n-\t\t\tdefault-state = \"off\";\n-\t\t};\n-\t};\n-\n-\tvcc_sys: vcc-sys-regulator {\n-\t\tcompatible = \"regulator-fixed\";\n-\t\tregulator-name = \"vcc_sys\";\n-\t\tregulator-min-microvolt = <5000000>;\n-\t\tregulator-max-microvolt = <5000000>;\n-\t\tregulator-always-on;\n-\t\tregulator-boot-on;\n-\t};\n-};\n-\n-&emmc {\n-\tstatus = \"okay\";\n-\tbus-width = <8>;\n-\tcap-mmc-highspeed;\n-\tclock-frequency = <150000000>;\n-\tnon-removable;\n-\tvmmc-supply = <&vcc_io>;\n-\tvqmmc-supply = <&vcc18_flash>;\n-\tpinctrl-names = \"default\";\n-\tpinctrl-0 = <&emmc_clk>, <&emmc_cmd>, <&emmc_bus8>;\n-};\n-\n-&gmac {\n-\tstatus = \"okay\";\n-\tphy-supply = <&vcc_lan>;\n-\tphy-mode = \"rgmii\";\n-\tclock_in_out = \"input\";\n-\tassigned-clocks = <&cru SCLK_MAC>;\n-\tassigned-clock-parents = <&ext_gmac>;\n-\tpinctrl-names = \"default\";\n-\tpinctrl-0 = <&rgmii_pins>;\n-\ttx_delay = <0x30>;\n-\trx_delay = <0x10>;\n-};\n-\n-&i2c0 {\n-\tstatus = \"okay\";\n-\n-\trk808: pmic@1b {\n-\t\tcompatible = \"rockchip,rk808\";\n-\t\treg = <0x1b>;\n-\t\tpinctrl-names = \"default\";\n-\t\tpinctrl-0 = <&pmic_int>, <&pmic_sleep>;\n-\t\tinterrupt-parent = <&gpio0>;\n-\t\tinterrupts = <RK_PA5 IRQ_TYPE_LEVEL_LOW>;\n-\t\trockchip,system-power-controller;\n-\t\tvcc1-supply = <&vcc_sys>;\n-\t\tvcc2-supply = <&vcc_sys>;\n-\t\tvcc3-supply = <&vcc_sys>;\n-\t\tvcc4-supply = <&vcc_sys>;\n-\t\tvcc6-supply = <&vcc_sys>;\n-\t\tvcc7-supply = <&vcc_sys>;\n-\t\tvcc8-supply = <&vcc_io>;\n-\t\tvcc9-supply = <&vcc_sys>;\n-\t\tvcc10-supply = <&vcc_sys>;\n-\t\tvcc11-supply = <&vcc_sys>;\n-\t\tvcc12-supply = <&vcc_io>;\n-\t\tclock-output-names = \"xin32k\", \"rk808-clkout2\";\n-\t\t#clock-cells = <1>;\n-\n-\t\tregulators {\n-\t\t\tvdd_cpu: DCDC_REG1 {\n-\t\t\t\tregulator-always-on;\n-\t\t\t\tregulator-boot-on;\n-\t\t\t\tregulator-min-microvolt = <700000>;\n-\t\t\t\tregulator-max-microvolt = <1500000>;\n-\t\t\t\tregulator-name = \"vdd_cpu\";\n-\t\t\t};\n-\n-\t\t\tvdd_log: DCDC_REG2 {\n-\t\t\t\tregulator-always-on;\n-\t\t\t\tregulator-boot-on;\n-\t\t\t\tregulator-min-microvolt = <700000>;\n-\t\t\t\tregulator-max-microvolt = <1500000>;\n-\t\t\t\tregulator-name = \"vdd_log\";\n-\t\t\t};\n-\n-\t\t\tvcc_ddr: DCDC_REG3 {\n-\t\t\t\tregulator-always-on;\n-\t\t\t\tregulator-boot-on;\n-\t\t\t\tregulator-name = \"vcc_ddr\";\n-\t\t\t};\n-\n-\t\t\tvcc_io: DCDC_REG4 {\n-\t\t\t\tregulator-always-on;\n-\t\t\t\tregulator-boot-on;\n-\t\t\t\tregulator-min-microvolt = <3300000>;\n-\t\t\t\tregulator-max-microvolt = <3300000>;\n-\t\t\t\tregulator-name = \"vcc_io\";\n-\t\t\t};\n-\n-\t\t\tvcc18_flash: LDO_REG1 {\n-\t\t\t\tregulator-always-on;\n-\t\t\t\tregulator-boot-on;\n-\t\t\t\tregulator-min-microvolt = <1800000>;\n-\t\t\t\tregulator-max-microvolt = <1800000>;\n-\t\t\t\tregulator-name = \"vcc18_flash\";\n-\t\t\t};\n-\n-\t\t\tvcc33_lcd: LDO_REG2 {\n-\t\t\t\tregulator-always-on;\n-\t\t\t\tregulator-boot-on;\n-\t\t\t\tregulator-min-microvolt = <3300000>;\n-\t\t\t\tregulator-max-microvolt = <3300000>;\n-\t\t\t\tregulator-name = \"vcc33_lcd\";\n-\t\t\t};\n-\n-\t\t\tvdd_10: LDO_REG3 {\n-\t\t\t\tregulator-always-on;\n-\t\t\t\tregulator-boot-on;\n-\t\t\t\tregulator-min-microvolt = <1000000>;\n-\t\t\t\tregulator-max-microvolt = <1000000>;\n-\t\t\t\tregulator-name = \"vdd_10\";\n-\t\t\t};\n-\n-\t\t\tvcca_18: LDO_REG4 {\n-\t\t\t\tregulator-boot-on;\n-\t\t\t\tregulator-min-microvolt = <1800000>;\n-\t\t\t\tregulator-max-microvolt = <1800000>;\n-\t\t\t\tregulator-name = \"vcca_18\";\n-\t\t\t};\n-\n-\t\t\tvccio_sd: LDO_REG5 {\n-\t\t\t\tregulator-always-on;\n-\t\t\t\tregulator-boot-on;\n-\t\t\t\tregulator-min-microvolt = <1800000>;\n-\t\t\t\tregulator-max-microvolt = <3300000>;\n-\t\t\t\tregulator-name = \"vccio_sd\";\n-\t\t\t};\n-\n-\t\t\tvdd10_lcd: LDO_REG6 {\n-\t\t\t\tregulator-always-on;\n-\t\t\t\tregulator-boot-on;\n-\t\t\t\tregulator-min-microvolt = <1000000>;\n-\t\t\t\tregulator-max-microvolt = <1000000>;\n-\t\t\t\tregulator-name = \"vdd10_lcd\";\n-\t\t\t};\n-\n-\t\t\tvcc_18: LDO_REG7 {\n-\t\t\t\tregulator-always-on;\n-\t\t\t\tregulator-boot-on;\n-\t\t\t\tregulator-min-microvolt = <1800000>;\n-\t\t\t\tregulator-max-microvolt = <1800000>;\n-\t\t\t\tregulator-name = \"vcc_18\";\n-\t\t\t};\n-\n-\t\t\tvcc18_lcd: LDO_REG8 {\n-\t\t\t\tregulator-always-on;\n-\t\t\t\tregulator-boot-on;\n-\t\t\t\tregulator-min-microvolt = <1800000>;\n-\t\t\t\tregulator-max-microvolt = <1800000>;\n-\t\t\t\tregulator-name = \"vcc18_lcd\";\n-\t\t\t};\n-\n-\t\t\tvcc_sd: SWITCH_REG1 {\n-\t\t\t\tregulator-name = \"vcc_sd\";\n-\t\t\t};\n-\n-\t\t\tvcc_lan: SWITCH_REG2 {\n-\t\t\t\tregulator-always-on;\n-\t\t\t\tregulator-boot-on;\n-\t\t\t\tregulator-name = \"vcc_lan\";\n-\t\t\t};\n-\t\t};\n-\t};\n-};\n-\n-&pinctrl {\n-\tir {\n-\t\tir_int: ir-int {\n-\t\t\trockchip,pins = <3 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;\n-\t\t};\n-\t};\n-\n-\tkeys {\n-\t\tpwr_key: pwr-key {\n-\t\t\trockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;\n-\t\t};\n-\t};\n-\n-\tpmic {\n-\t\tpmic_sleep: pmic-sleep {\n-\t\t\trockchip,pins = <0 RK_PA0 2 &pcfg_pull_none>;\n-\t\t};\n-\n-\t\tpmic_int: pmic-int {\n-\t\t\trockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;\n-\t\t};\n-\t};\n-};\n-\n-&tsadc {\n-\tstatus = \"okay\";\n-\trockchip,hw-tshut-mode = <0>; /* CRU */\n-\trockchip,hw-tshut-polarity = <1>; /* high */\n-};\n-\n-&uart2 {\n-\tstatus = \"okay\";\n-};\n-\n-&usb_host0_ehci {\n-\tstatus = \"okay\";\n-};\n-\n-&usb_otg {\n-\tstatus = \"okay\";\n-};\n-\n-&wdt {\n-\tstatus = \"okay\";\n-};\ndiff --git a/arch/arm/dts/rk3368-px5-evb.dts b/arch/arm/dts/rk3368-px5-evb.dts\ndeleted file mode 100644\nindex 5ccaa5f7a370..000000000000\n--- a/arch/arm/dts/rk3368-px5-evb.dts\n+++ /dev/null\n@@ -1,277 +0,0 @@\n-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)\n-/*\n- * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd\n- */\n-\n-/dts-v1/;\n-#include \"rk3368.dtsi\"\n-#include <dt-bindings/input/input.h>\n-\n-/ {\n-\tmodel = \"Rockchip PX5 EVB\";\n-\tcompatible = \"rockchip,px5-evb\", \"rockchip,px5\", \"rockchip,rk3368\";\n-\n-\taliases {\n-\t\tmmc0 = &sdmmc;\n-\t\tmmc1 = &emmc;\n-\t};\n-\n-\tchosen {\n-\t\tstdout-path = \"serial4:115200n8\";\n-\t};\n-\n-\tmemory@0 {\n-\t\treg = <0x0 0x0 0x0 0x40000000>;\n-\t\tdevice_type = \"memory\";\n-\t};\n-\n-\tkeys: gpio-keys {\n-\t\tcompatible = \"gpio-keys\";\n-\t\tpinctrl-names = \"default\";\n-\t\tpinctrl-0 = <&pwr_key>;\n-\n-\t\tpower {\n-\t\t\tgpios = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>;\n-\t\t\tlabel = \"GPIO Power\";\n-\t\t\tlinux,code = <KEY_POWER>;\n-\t\t\twakeup-source;\n-\t\t};\n-\t};\n-\n-\tvcc_sys: vcc-sys-regulator {\n-\t\tcompatible = \"regulator-fixed\";\n-\t\tregulator-name = \"vcc_sys\";\n-\t\tregulator-min-microvolt = <5000000>;\n-\t\tregulator-max-microvolt = <5000000>;\n-\t\tregulator-always-on;\n-\t\tregulator-boot-on;\n-\t};\n-};\n-\n-&emmc {\n-\tstatus = \"okay\";\n-\tbus-width = <8>;\n-\tcap-mmc-highspeed;\n-\tclock-frequency = <150000000>;\n-\tmmc-hs200-1_8v;\n-\tno-sdio;\n-\tno-sd;\n-\tnon-removable;\n-\tpinctrl-names = \"default\";\n-\tpinctrl-0 = <&emmc_clk>, <&emmc_cmd>, <&emmc_bus8>;\n-\tvmmc-supply = <&vcc_io>;\n-\tvqmmc-supply = <&vcc18_flash>;\n-};\n-\n-&i2c0 {\n-\tstatus = \"okay\";\n-\n-\trk808: pmic@1b {\n-\t\tcompatible = \"rockchip,rk808\";\n-\t\treg = <0x1b>;\n-\t\tinterrupt-parent = <&gpio0>;\n-\t\tinterrupts = <RK_PA5 IRQ_TYPE_LEVEL_LOW>;\n-\t\tpinctrl-names = \"default\";\n-\t\tpinctrl-0 = <&pmic_int>, <&pmic_sleep>;\n-\t\trockchip,system-power-controller;\n-\t\tvcc1-supply = <&vcc_sys>;\n-\t\tvcc2-supply = <&vcc_sys>;\n-\t\tvcc3-supply = <&vcc_sys>;\n-\t\tvcc4-supply = <&vcc_sys>;\n-\t\tvcc6-supply = <&vcc_sys>;\n-\t\tvcc7-supply = <&vcc_sys>;\n-\t\tvcc8-supply = <&vcc_io>;\n-\t\tvcc9-supply = <&vcc_sys>;\n-\t\tvcc10-supply = <&vcc_sys>;\n-\t\tvcc11-supply = <&vcc_sys>;\n-\t\tvcc12-supply = <&vcc_io>;\n-\t\tclock-output-names = \"xin32k\", \"rk808-clkout2\";\n-\t\t#clock-cells = <1>;\n-\n-\t\tregulators {\n-\t\t\tvdd_cpu: DCDC_REG1 {\n-\t\t\t\tregulator-always-on;\n-\t\t\t\tregulator-boot-on;\n-\t\t\t\tregulator-min-microvolt = <700000>;\n-\t\t\t\tregulator-max-microvolt = <1500000>;\n-\t\t\t\tregulator-name = \"vdd_cpu\";\n-\t\t\t};\n-\n-\t\t\tvdd_log: DCDC_REG2 {\n-\t\t\t\tregulator-always-on;\n-\t\t\t\tregulator-boot-on;\n-\t\t\t\tregulator-min-microvolt = <700000>;\n-\t\t\t\tregulator-max-microvolt = <1500000>;\n-\t\t\t\tregulator-name = \"vdd_log\";\n-\t\t\t};\n-\n-\t\t\tvcc_ddr: DCDC_REG3 {\n-\t\t\t\tregulator-always-on;\n-\t\t\t\tregulator-boot-on;\n-\t\t\t\tregulator-name = \"vcc_ddr\";\n-\t\t\t};\n-\n-\t\t\tvcc_io: DCDC_REG4 {\n-\t\t\t\tregulator-always-on;\n-\t\t\t\tregulator-boot-on;\n-\t\t\t\tregulator-min-microvolt = <3300000>;\n-\t\t\t\tregulator-max-microvolt = <3300000>;\n-\t\t\t\tregulator-name = \"vcc_io\";\n-\t\t\t};\n-\n-\t\t\tvcc18_flash: LDO_REG1 {\n-\t\t\t\tregulator-always-on;\n-\t\t\t\tregulator-boot-on;\n-\t\t\t\tregulator-min-microvolt = <1800000>;\n-\t\t\t\tregulator-max-microvolt = <1800000>;\n-\t\t\t\tregulator-name = \"vcc18_flash\";\n-\t\t\t};\n-\n-\t\t\tvcca_33: LDO_REG2 {\n-\t\t\t\tregulator-always-on;\n-\t\t\t\tregulator-boot-on;\n-\t\t\t\tregulator-min-microvolt = <3300000>;\n-\t\t\t\tregulator-max-microvolt = <3300000>;\n-\t\t\t\tregulator-name = \"vcca_33\";\n-\t\t\t};\n-\n-\t\t\tvdd_10: LDO_REG3 {\n-\t\t\t\tregulator-always-on;\n-\t\t\t\tregulator-boot-on;\n-\t\t\t\tregulator-min-microvolt = <1000000>;\n-\t\t\t\tregulator-max-microvolt = <1000000>;\n-\t\t\t\tregulator-name = \"vdd_10\";\n-\t\t\t};\n-\n-\t\t\tavdd_33: LDO_REG4 {\n-\t\t\t\tregulator-min-microvolt = <3300000>;\n-\t\t\t\tregulator-max-microvolt = <3300000>;\n-\t\t\t\tregulator-name = \"avdd_33\";\n-\t\t\t};\n-\n-\t\t\tvccio_sd: LDO_REG5 {\n-\t\t\t\tregulator-always-on;\n-\t\t\t\tregulator-boot-on;\n-\t\t\t\tregulator-min-microvolt = <1800000>;\n-\t\t\t\tregulator-max-microvolt = <3300000>;\n-\t\t\t\tregulator-name = \"vccio_sd\";\n-\t\t\t};\n-\n-\t\t\tvdd10_lcd: LDO_REG6 {\n-\t\t\t\tregulator-always-on;\n-\t\t\t\tregulator-boot-on;\n-\t\t\t\tregulator-min-microvolt = <1000000>;\n-\t\t\t\tregulator-max-microvolt = <1000000>;\n-\t\t\t\tregulator-name = \"vdd10_lcd\";\n-\t\t\t};\n-\n-\t\t\tvcc_18: LDO_REG7 {\n-\t\t\t\tregulator-always-on;\n-\t\t\t\tregulator-boot-on;\n-\t\t\t\tregulator-min-microvolt = <1800000>;\n-\t\t\t\tregulator-max-microvolt = <1800000>;\n-\t\t\t\tregulator-name = \"vcc_18\";\n-\t\t\t};\n-\n-\t\t\tvcc18_lcd: LDO_REG8 {\n-\t\t\t\tregulator-always-on;\n-\t\t\t\tregulator-boot-on;\n-\t\t\t\tregulator-min-microvolt = <1800000>;\n-\t\t\t\tregulator-max-microvolt = <1800000>;\n-\t\t\t\tregulator-name = \"vcc18_lcd\";\n-\t\t\t};\n-\n-\t\t\tvcc_sd: SWITCH_REG1 {\n-\t\t\t\tregulator-name = \"vcc_sd\";\n-\t\t\t};\n-\n-\t\t\tvcc33_lcd: SWITCH_REG2 {\n-\t\t\t\tregulator-always-on;\n-\t\t\t\tregulator-boot-on;\n-\t\t\t\tregulator-name = \"vcc33_lcd\";\n-\t\t\t};\n-\t\t};\n-\t};\n-};\n-\n-&i2c1 {\n-\tstatus = \"okay\";\n-\n-\taccelerometer@18 {\n-\t\tcompatible = \"bosch,bma250\";\n-\t\treg = <0x18>;\n-\t\tinterrupt-parent = <&gpio2>;\n-\t\tinterrupts = <RK_PC1 IRQ_TYPE_LEVEL_LOW>;\n-\t};\n-};\n-\n-&i2c2 {\n-\tstatus = \"okay\";\n-\n-\tgsl1680: touchscreen@40 {\n-\t\tcompatible = \"silead,gsl1680\";\n-\t\treg = <0x40>;\n-\t\tinterrupt-parent = <&gpio3>;\n-\t\tinterrupts = <RK_PD4 IRQ_TYPE_EDGE_FALLING>;\n-\t\tpower-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_HIGH>;\n-\t\ttouchscreen-size-x = <800>;\n-\t\ttouchscreen-size-y = <1280>;\n-\t\tsilead,max-fingers = <5>;\n-\t};\n-};\n-\n-&pinctrl {\n-\tkeys {\n-\t\tpwr_key: pwr-key {\n-\t\t\trockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;\n-\t\t};\n-\t};\n-\n-\tpmic {\n-\t\tpmic_sleep: pmic-sleep {\n-\t\t\trockchip,pins = <0 RK_PA0 2 &pcfg_pull_none>;\n-\t\t};\n-\n-\t\tpmic_int: pmic-int {\n-\t\t\trockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;\n-\t\t};\n-\t};\n-};\n-\n-&sdmmc {\n-\tstatus = \"okay\";\n-\tbus-width = <4>;\n-\tcap-mmc-highspeed;\n-\tcap-sd-highspeed;\n-\tcard-detect-delay = <200>;\n-\tno-sdio;\n-\tsd-uhs-sdr12;\n-\tsd-uhs-sdr25;\n-\tpinctrl-names = \"default\";\n-\tpinctrl-0 = <&sdmmc_clk>, <&sdmmc_cmd>, <&sdmmc_bus4>, <&sdmmc_cd>;\n-\trockchip,default-sample-phase = <90>;\n-\tvmmc-supply = <&vcc_sd>;\n-\tvqmmc-supply = <&vccio_sd>;\n-};\n-\n-&tsadc {\n-\tstatus = \"okay\";\n-\trockchip,hw-tshut-mode = <0>; /* CRU */\n-\trockchip,hw-tshut-polarity = <1>; /* high */\n-};\n-\n-&uart4 {\n-\tstatus = \"okay\";\n-};\n-\n-&usb_host0_ehci {\n-\tstatus = \"okay\";\n-};\n-\n-&usb_otg {\n-\tstatus = \"okay\";\n-};\n-\n-&wdt {\n-\tstatus = \"okay\";\n-};\ndiff --git a/arch/arm/dts/rk3368-u-boot.dtsi b/arch/arm/dts/rk3368-u-boot.dtsi\nindex 811d59ac346e..16c434b944da 100644\n--- a/arch/arm/dts/rk3368-u-boot.dtsi\n+++ b/arch/arm/dts/rk3368-u-boot.dtsi\n@@ -26,3 +26,7 @@\n \t\treg = <0x0 0xff740000 0x0 0x1000>;\n \t};\n };\n+\n+&xin24m {\n+\tbootph-all;\n+};\ndiff --git a/arch/arm/dts/rk3368.dtsi b/arch/arm/dts/rk3368.dtsi\ndeleted file mode 100644\nindex 4c64fbefb483..000000000000\n--- a/arch/arm/dts/rk3368.dtsi\n+++ /dev/null\n@@ -1,1218 +0,0 @@\n-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)\n-/*\n- * Copyright (c) 2015 Heiko Stuebner <heiko@sntech.de>\n- */\n-\n-#include <dt-bindings/clock/rk3368-cru.h>\n-#include <dt-bindings/gpio/gpio.h>\n-#include <dt-bindings/interrupt-controller/irq.h>\n-#include <dt-bindings/interrupt-controller/arm-gic.h>\n-#include <dt-bindings/pinctrl/rockchip.h>\n-#include <dt-bindings/soc/rockchip,boot-mode.h>\n-#include <dt-bindings/thermal/thermal.h>\n-\n-/ {\n-\tcompatible = \"rockchip,rk3368\";\n-\tinterrupt-parent = <&gic>;\n-\t#address-cells = <2>;\n-\t#size-cells = <2>;\n-\n-\taliases {\n-\t\tethernet0 = &gmac;\n-\t\ti2c0 = &i2c0;\n-\t\ti2c1 = &i2c1;\n-\t\ti2c2 = &i2c2;\n-\t\ti2c3 = &i2c3;\n-\t\ti2c4 = &i2c4;\n-\t\ti2c5 = &i2c5;\n-\t\tserial0 = &uart0;\n-\t\tserial1 = &uart1;\n-\t\tserial2 = &uart2;\n-\t\tserial3 = &uart3;\n-\t\tserial4 = &uart4;\n-\t\tspi0 = &spi0;\n-\t\tspi1 = &spi1;\n-\t\tspi2 = &spi2;\n-\t};\n-\n-\tcpus {\n-\t\t#address-cells = <0x2>;\n-\t\t#size-cells = <0x0>;\n-\n-\t\tcpu-map {\n-\t\t\tcluster0 {\n-\t\t\t\tcore0 {\n-\t\t\t\t\tcpu = <&cpu_b0>;\n-\t\t\t\t};\n-\t\t\t\tcore1 {\n-\t\t\t\t\tcpu = <&cpu_b1>;\n-\t\t\t\t};\n-\t\t\t\tcore2 {\n-\t\t\t\t\tcpu = <&cpu_b2>;\n-\t\t\t\t};\n-\t\t\t\tcore3 {\n-\t\t\t\t\tcpu = <&cpu_b3>;\n-\t\t\t\t};\n-\t\t\t};\n-\n-\t\t\tcluster1 {\n-\t\t\t\tcore0 {\n-\t\t\t\t\tcpu = <&cpu_l0>;\n-\t\t\t\t};\n-\t\t\t\tcore1 {\n-\t\t\t\t\tcpu = <&cpu_l1>;\n-\t\t\t\t};\n-\t\t\t\tcore2 {\n-\t\t\t\t\tcpu = <&cpu_l2>;\n-\t\t\t\t};\n-\t\t\t\tcore3 {\n-\t\t\t\t\tcpu = <&cpu_l3>;\n-\t\t\t\t};\n-\t\t\t};\n-\t\t};\n-\n-\t\tcpu_l0: cpu@0 {\n-\t\t\tdevice_type = \"cpu\";\n-\t\t\tcompatible = \"arm,cortex-a53\";\n-\t\t\treg = <0x0 0x0>;\n-\t\t\tenable-method = \"psci\";\n-\t\t\t#cooling-cells = <2>; /* min followed by max */\n-\t\t};\n-\n-\t\tcpu_l1: cpu@1 {\n-\t\t\tdevice_type = \"cpu\";\n-\t\t\tcompatible = \"arm,cortex-a53\";\n-\t\t\treg = <0x0 0x1>;\n-\t\t\tenable-method = \"psci\";\n-\t\t\t#cooling-cells = <2>; /* min followed by max */\n-\t\t};\n-\n-\t\tcpu_l2: cpu@2 {\n-\t\t\tdevice_type = \"cpu\";\n-\t\t\tcompatible = \"arm,cortex-a53\";\n-\t\t\treg = <0x0 0x2>;\n-\t\t\tenable-method = \"psci\";\n-\t\t\t#cooling-cells = <2>; /* min followed by max */\n-\t\t};\n-\n-\t\tcpu_l3: cpu@3 {\n-\t\t\tdevice_type = \"cpu\";\n-\t\t\tcompatible = \"arm,cortex-a53\";\n-\t\t\treg = <0x0 0x3>;\n-\t\t\tenable-method = \"psci\";\n-\t\t\t#cooling-cells = <2>; /* min followed by max */\n-\t\t};\n-\n-\t\tcpu_b0: cpu@100 {\n-\t\t\tdevice_type = \"cpu\";\n-\t\t\tcompatible = \"arm,cortex-a53\";\n-\t\t\treg = <0x0 0x100>;\n-\t\t\tenable-method = \"psci\";\n-\t\t\t#cooling-cells = <2>; /* min followed by max */\n-\t\t};\n-\n-\t\tcpu_b1: cpu@101 {\n-\t\t\tdevice_type = \"cpu\";\n-\t\t\tcompatible = \"arm,cortex-a53\";\n-\t\t\treg = <0x0 0x101>;\n-\t\t\tenable-method = \"psci\";\n-\t\t\t#cooling-cells = <2>; /* min followed by max */\n-\t\t};\n-\n-\t\tcpu_b2: cpu@102 {\n-\t\t\tdevice_type = \"cpu\";\n-\t\t\tcompatible = \"arm,cortex-a53\";\n-\t\t\treg = <0x0 0x102>;\n-\t\t\tenable-method = \"psci\";\n-\t\t\t#cooling-cells = <2>; /* min followed by max */\n-\t\t};\n-\n-\t\tcpu_b3: cpu@103 {\n-\t\t\tdevice_type = \"cpu\";\n-\t\t\tcompatible = \"arm,cortex-a53\";\n-\t\t\treg = <0x0 0x103>;\n-\t\t\tenable-method = \"psci\";\n-\t\t\t#cooling-cells = <2>; /* min followed by max */\n-\t\t};\n-\t};\n-\n-\tarm-pmu {\n-\t\tcompatible = \"arm,armv8-pmuv3\";\n-\t\tinterrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,\n-\t\t\t     <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,\n-\t\t\t     <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,\n-\t\t\t     <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,\n-\t\t\t     <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,\n-\t\t\t     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,\n-\t\t\t     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,\n-\t\t\t     <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;\n-\t\tinterrupt-affinity = <&cpu_l0>, <&cpu_l1>, <&cpu_l2>,\n-\t\t\t\t     <&cpu_l3>, <&cpu_b0>, <&cpu_b1>,\n-\t\t\t\t     <&cpu_b2>, <&cpu_b3>;\n-\t};\n-\n-\tpsci {\n-\t\tcompatible = \"arm,psci-0.2\";\n-\t\tmethod = \"smc\";\n-\t};\n-\n-\ttimer {\n-\t\tcompatible = \"arm,armv8-timer\";\n-\t\tinterrupts = <GIC_PPI 13\n-\t\t\t(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,\n-\t\t\t     <GIC_PPI 14\n-\t\t\t(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,\n-\t\t\t     <GIC_PPI 11\n-\t\t\t(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,\n-\t\t\t     <GIC_PPI 10\n-\t\t\t(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;\n-\t};\n-\n-\txin24m: oscillator {\n-\t\tcompatible = \"fixed-clock\";\n-\t\tclock-frequency = <24000000>;\n-\t\tclock-output-names = \"xin24m\";\n-\t\t#clock-cells = <0>;\n-\t};\n-\n-\tsdmmc: mmc@ff0c0000 {\n-\t\tcompatible = \"rockchip,rk3368-dw-mshc\", \"rockchip,rk3288-dw-mshc\";\n-\t\treg = <0x0 0xff0c0000 0x0 0x4000>;\n-\t\tmax-frequency = <150000000>;\n-\t\tclocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,\n-\t\t\t <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;\n-\t\tclock-names = \"biu\", \"ciu\", \"ciu-drive\", \"ciu-sample\";\n-\t\tfifo-depth = <0x100>;\n-\t\tinterrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;\n-\t\tresets = <&cru SRST_MMC0>;\n-\t\treset-names = \"reset\";\n-\t\tstatus = \"disabled\";\n-\t};\n-\n-\tsdio0: mmc@ff0d0000 {\n-\t\tcompatible = \"rockchip,rk3368-dw-mshc\", \"rockchip,rk3288-dw-mshc\";\n-\t\treg = <0x0 0xff0d0000 0x0 0x4000>;\n-\t\tmax-frequency = <150000000>;\n-\t\tclocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,\n-\t\t\t <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;\n-\t\tclock-names = \"biu\", \"ciu\", \"ciu-drive\", \"ciu-sample\";\n-\t\tfifo-depth = <0x100>;\n-\t\tinterrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;\n-\t\tresets = <&cru SRST_SDIO0>;\n-\t\treset-names = \"reset\";\n-\t\tstatus = \"disabled\";\n-\t};\n-\n-\temmc: mmc@ff0f0000 {\n-\t\tcompatible = \"rockchip,rk3368-dw-mshc\", \"rockchip,rk3288-dw-mshc\";\n-\t\treg = <0x0 0xff0f0000 0x0 0x4000>;\n-\t\tmax-frequency = <150000000>;\n-\t\tclocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,\n-\t\t\t <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;\n-\t\tclock-names = \"biu\", \"ciu\", \"ciu-drive\", \"ciu-sample\";\n-\t\tfifo-depth = <0x100>;\n-\t\tinterrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;\n-\t\tresets = <&cru SRST_EMMC>;\n-\t\treset-names = \"reset\";\n-\t\tstatus = \"disabled\";\n-\t};\n-\n-\tsaradc: saradc@ff100000 {\n-\t\tcompatible = \"rockchip,saradc\";\n-\t\treg = <0x0 0xff100000 0x0 0x100>;\n-\t\tinterrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;\n-\t\t#io-channel-cells = <1>;\n-\t\tclocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;\n-\t\tclock-names = \"saradc\", \"apb_pclk\";\n-\t\tresets = <&cru SRST_SARADC>;\n-\t\treset-names = \"saradc-apb\";\n-\t\tstatus = \"disabled\";\n-\t};\n-\n-\tspi0: spi@ff110000 {\n-\t\tcompatible = \"rockchip,rk3368-spi\", \"rockchip,rk3066-spi\";\n-\t\treg = <0x0 0xff110000 0x0 0x1000>;\n-\t\tclocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;\n-\t\tclock-names = \"spiclk\", \"apb_pclk\";\n-\t\tinterrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;\n-\t\tpinctrl-names = \"default\";\n-\t\tpinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;\n-\t\t#address-cells = <1>;\n-\t\t#size-cells = <0>;\n-\t\tstatus = \"disabled\";\n-\t};\n-\n-\tspi1: spi@ff120000 {\n-\t\tcompatible = \"rockchip,rk3368-spi\", \"rockchip,rk3066-spi\";\n-\t\treg = <0x0 0xff120000 0x0 0x1000>;\n-\t\tclocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;\n-\t\tclock-names = \"spiclk\", \"apb_pclk\";\n-\t\tinterrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;\n-\t\tpinctrl-names = \"default\";\n-\t\tpinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;\n-\t\t#address-cells = <1>;\n-\t\t#size-cells = <0>;\n-\t\tstatus = \"disabled\";\n-\t};\n-\n-\tspi2: spi@ff130000 {\n-\t\tcompatible = \"rockchip,rk3368-spi\", \"rockchip,rk3066-spi\";\n-\t\treg = <0x0 0xff130000 0x0 0x1000>;\n-\t\tclocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;\n-\t\tclock-names = \"spiclk\", \"apb_pclk\";\n-\t\tinterrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;\n-\t\tpinctrl-names = \"default\";\n-\t\tpinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;\n-\t\t#address-cells = <1>;\n-\t\t#size-cells = <0>;\n-\t\tstatus = \"disabled\";\n-\t};\n-\n-\ti2c2: i2c@ff140000 {\n-\t\tcompatible = \"rockchip,rk3368-i2c\", \"rockchip,rk3288-i2c\";\n-\t\treg = <0x0 0xff140000 0x0 0x1000>;\n-\t\tinterrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;\n-\t\t#address-cells = <1>;\n-\t\t#size-cells = <0>;\n-\t\tclock-names = \"i2c\";\n-\t\tclocks = <&cru PCLK_I2C2>;\n-\t\tpinctrl-names = \"default\";\n-\t\tpinctrl-0 = <&i2c2_xfer>;\n-\t\tstatus = \"disabled\";\n-\t};\n-\n-\ti2c3: i2c@ff150000 {\n-\t\tcompatible = \"rockchip,rk3368-i2c\", \"rockchip,rk3288-i2c\";\n-\t\treg = <0x0 0xff150000 0x0 0x1000>;\n-\t\tinterrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;\n-\t\t#address-cells = <1>;\n-\t\t#size-cells = <0>;\n-\t\tclock-names = \"i2c\";\n-\t\tclocks = <&cru PCLK_I2C3>;\n-\t\tpinctrl-names = \"default\";\n-\t\tpinctrl-0 = <&i2c3_xfer>;\n-\t\tstatus = \"disabled\";\n-\t};\n-\n-\ti2c4: i2c@ff160000 {\n-\t\tcompatible = \"rockchip,rk3368-i2c\", \"rockchip,rk3288-i2c\";\n-\t\treg = <0x0 0xff160000 0x0 0x1000>;\n-\t\tinterrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;\n-\t\t#address-cells = <1>;\n-\t\t#size-cells = <0>;\n-\t\tclock-names = \"i2c\";\n-\t\tclocks = <&cru PCLK_I2C4>;\n-\t\tpinctrl-names = \"default\";\n-\t\tpinctrl-0 = <&i2c4_xfer>;\n-\t\tstatus = \"disabled\";\n-\t};\n-\n-\ti2c5: i2c@ff170000 {\n-\t\tcompatible = \"rockchip,rk3368-i2c\", \"rockchip,rk3288-i2c\";\n-\t\treg = <0x0 0xff170000 0x0 0x1000>;\n-\t\tinterrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;\n-\t\t#address-cells = <1>;\n-\t\t#size-cells = <0>;\n-\t\tclock-names = \"i2c\";\n-\t\tclocks = <&cru PCLK_I2C5>;\n-\t\tpinctrl-names = \"default\";\n-\t\tpinctrl-0 = <&i2c5_xfer>;\n-\t\tstatus = \"disabled\";\n-\t};\n-\n-\tuart0: serial@ff180000 {\n-\t\tcompatible = \"rockchip,rk3368-uart\", \"snps,dw-apb-uart\";\n-\t\treg = <0x0 0xff180000 0x0 0x100>;\n-\t\tclock-frequency = <24000000>;\n-\t\tclocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;\n-\t\tclock-names = \"baudclk\", \"apb_pclk\";\n-\t\tinterrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;\n-\t\treg-shift = <2>;\n-\t\treg-io-width = <4>;\n-\t\tstatus = \"disabled\";\n-\t};\n-\n-\tuart1: serial@ff190000 {\n-\t\tcompatible = \"rockchip,rk3368-uart\", \"snps,dw-apb-uart\";\n-\t\treg = <0x0 0xff190000 0x0 0x100>;\n-\t\tclock-frequency = <24000000>;\n-\t\tclocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;\n-\t\tclock-names = \"baudclk\", \"apb_pclk\";\n-\t\tinterrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;\n-\t\treg-shift = <2>;\n-\t\treg-io-width = <4>;\n-\t\tstatus = \"disabled\";\n-\t};\n-\n-\tuart3: serial@ff1b0000 {\n-\t\tcompatible = \"rockchip,rk3368-uart\", \"snps,dw-apb-uart\";\n-\t\treg = <0x0 0xff1b0000 0x0 0x100>;\n-\t\tclock-frequency = <24000000>;\n-\t\tclocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;\n-\t\tclock-names = \"baudclk\", \"apb_pclk\";\n-\t\tinterrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;\n-\t\treg-shift = <2>;\n-\t\treg-io-width = <4>;\n-\t\tstatus = \"disabled\";\n-\t};\n-\n-\tuart4: serial@ff1c0000 {\n-\t\tcompatible = \"rockchip,rk3368-uart\", \"snps,dw-apb-uart\";\n-\t\treg = <0x0 0xff1c0000 0x0 0x100>;\n-\t\tclock-frequency = <24000000>;\n-\t\tclocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;\n-\t\tclock-names = \"baudclk\", \"apb_pclk\";\n-\t\tinterrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;\n-\t\treg-shift = <2>;\n-\t\treg-io-width = <4>;\n-\t\tstatus = \"disabled\";\n-\t};\n-\n-\tdmac_peri: dma-controller@ff250000 {\n-\t\tcompatible = \"arm,pl330\", \"arm,primecell\";\n-\t\treg = <0x0 0xff250000 0x0 0x4000>;\n-\t\tinterrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,\n-\t\t\t     <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;\n-\t\t#dma-cells = <1>;\n-\t\tarm,pl330-broken-no-flushp;\n-\t\tarm,pl330-periph-burst;\n-\t\tclocks = <&cru ACLK_DMAC_PERI>;\n-\t\tclock-names = \"apb_pclk\";\n-\t};\n-\n-\tthermal-zones {\n-\t\tcpu_thermal: cpu-thermal {\n-\t\t\tpolling-delay-passive = <100>; /* milliseconds */\n-\t\t\tpolling-delay = <5000>; /* milliseconds */\n-\n-\t\t\tthermal-sensors = <&tsadc 0>;\n-\n-\t\t\ttrips {\n-\t\t\t\tcpu_alert0: cpu_alert0 {\n-\t\t\t\t\ttemperature = <75000>; /* millicelsius */\n-\t\t\t\t\thysteresis = <2000>; /* millicelsius */\n-\t\t\t\t\ttype = \"passive\";\n-\t\t\t\t};\n-\t\t\t\tcpu_alert1: cpu_alert1 {\n-\t\t\t\t\ttemperature = <80000>; /* millicelsius */\n-\t\t\t\t\thysteresis = <2000>; /* millicelsius */\n-\t\t\t\t\ttype = \"passive\";\n-\t\t\t\t};\n-\t\t\t\tcpu_crit: cpu_crit {\n-\t\t\t\t\ttemperature = <95000>; /* millicelsius */\n-\t\t\t\t\thysteresis = <2000>; /* millicelsius */\n-\t\t\t\t\ttype = \"critical\";\n-\t\t\t\t};\n-\t\t\t};\n-\n-\t\t\tcooling-maps {\n-\t\t\t\tmap0 {\n-\t\t\t\t\ttrip = <&cpu_alert0>;\n-\t\t\t\t\tcooling-device =\n-\t\t\t\t\t<&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,\n-\t\t\t\t\t<&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,\n-\t\t\t\t\t<&cpu_b2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,\n-\t\t\t\t\t<&cpu_b3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;\n-\t\t\t\t};\n-\t\t\t\tmap1 {\n-\t\t\t\t\ttrip = <&cpu_alert1>;\n-\t\t\t\t\tcooling-device =\n-\t\t\t\t\t<&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,\n-\t\t\t\t\t<&cpu_l1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,\n-\t\t\t\t\t<&cpu_l2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,\n-\t\t\t\t\t<&cpu_l3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;\n-\t\t\t\t};\n-\t\t\t};\n-\t\t};\n-\n-\t\tgpu_thermal: gpu-thermal {\n-\t\t\tpolling-delay-passive = <100>; /* milliseconds */\n-\t\t\tpolling-delay = <5000>; /* milliseconds */\n-\n-\t\t\tthermal-sensors = <&tsadc 1>;\n-\n-\t\t\ttrips {\n-\t\t\t\tgpu_alert0: gpu_alert0 {\n-\t\t\t\t\ttemperature = <80000>; /* millicelsius */\n-\t\t\t\t\thysteresis = <2000>; /* millicelsius */\n-\t\t\t\t\ttype = \"passive\";\n-\t\t\t\t};\n-\t\t\t\tgpu_crit: gpu_crit {\n-\t\t\t\t\ttemperature = <115000>; /* millicelsius */\n-\t\t\t\t\thysteresis = <2000>; /* millicelsius */\n-\t\t\t\t\ttype = \"critical\";\n-\t\t\t\t};\n-\t\t\t};\n-\n-\t\t\tcooling-maps {\n-\t\t\t\tmap0 {\n-\t\t\t\t\ttrip = <&gpu_alert0>;\n-\t\t\t\t\tcooling-device =\n-\t\t\t\t\t<&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,\n-\t\t\t\t\t<&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,\n-\t\t\t\t\t<&cpu_b2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,\n-\t\t\t\t\t<&cpu_b3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;\n-\t\t\t\t};\n-\t\t\t};\n-\t\t};\n-\t};\n-\n-\ttsadc: tsadc@ff280000 {\n-\t\tcompatible = \"rockchip,rk3368-tsadc\";\n-\t\treg = <0x0 0xff280000 0x0 0x100>;\n-\t\tinterrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;\n-\t\tclocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;\n-\t\tclock-names = \"tsadc\", \"apb_pclk\";\n-\t\tresets = <&cru SRST_TSADC>;\n-\t\treset-names = \"tsadc-apb\";\n-\t\tpinctrl-names = \"init\", \"default\", \"sleep\";\n-\t\tpinctrl-0 = <&otp_pin>;\n-\t\tpinctrl-1 = <&otp_out>;\n-\t\tpinctrl-2 = <&otp_pin>;\n-\t\t#thermal-sensor-cells = <1>;\n-\t\trockchip,hw-tshut-temp = <95000>;\n-\t\tstatus = \"disabled\";\n-\t};\n-\n-\tgmac: ethernet@ff290000 {\n-\t\tcompatible = \"rockchip,rk3368-gmac\";\n-\t\treg = <0x0 0xff290000 0x0 0x10000>;\n-\t\tinterrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;\n-\t\tinterrupt-names = \"macirq\";\n-\t\trockchip,grf = <&grf>;\n-\t\tclocks = <&cru SCLK_MAC>,\n-\t\t\t<&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,\n-\t\t\t<&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,\n-\t\t\t<&cru ACLK_GMAC>, <&cru PCLK_GMAC>;\n-\t\tclock-names = \"stmmaceth\",\n-\t\t\t\"mac_clk_rx\", \"mac_clk_tx\",\n-\t\t\t\"clk_mac_ref\", \"clk_mac_refout\",\n-\t\t\t\"aclk_mac\", \"pclk_mac\";\n-\t\tstatus = \"disabled\";\n-\t};\n-\n-\tusb_host0_ehci: usb@ff500000 {\n-\t\tcompatible = \"generic-ehci\";\n-\t\treg = <0x0 0xff500000 0x0 0x100>;\n-\t\tinterrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;\n-\t\tclocks = <&cru HCLK_HOST0>;\n-\t\tstatus = \"disabled\";\n-\t};\n-\n-\tusb_otg: usb@ff580000 {\n-\t\tcompatible = \"rockchip,rk3368-usb\", \"rockchip,rk3066-usb\",\n-\t\t\t\t\"snps,dwc2\";\n-\t\treg = <0x0 0xff580000 0x0 0x40000>;\n-\t\tinterrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;\n-\t\tclocks = <&cru HCLK_OTG0>;\n-\t\tclock-names = \"otg\";\n-\t\tdr_mode = \"otg\";\n-\t\tg-np-tx-fifo-size = <16>;\n-\t\tg-rx-fifo-size = <275>;\n-\t\tg-tx-fifo-size = <256 128 128 64 64 32>;\n-\t\tstatus = \"disabled\";\n-\t};\n-\n-\tdmac_bus: dma-controller@ff600000 {\n-\t\tcompatible = \"arm,pl330\", \"arm,primecell\";\n-\t\treg = <0x0 0xff600000 0x0 0x4000>;\n-\t\tinterrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,\n-\t\t\t     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;\n-\t\t#dma-cells = <1>;\n-\t\tarm,pl330-broken-no-flushp;\n-\t\tarm,pl330-periph-burst;\n-\t\tclocks = <&cru ACLK_DMAC_BUS>;\n-\t\tclock-names = \"apb_pclk\";\n-\t};\n-\n-\ti2c0: i2c@ff650000 {\n-\t\tcompatible = \"rockchip,rk3368-i2c\", \"rockchip,rk3288-i2c\";\n-\t\treg = <0x0 0xff650000 0x0 0x1000>;\n-\t\tclocks = <&cru PCLK_I2C0>;\n-\t\tclock-names = \"i2c\";\n-\t\tinterrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;\n-\t\tpinctrl-names = \"default\";\n-\t\tpinctrl-0 = <&i2c0_xfer>;\n-\t\t#address-cells = <1>;\n-\t\t#size-cells = <0>;\n-\t\tstatus = \"disabled\";\n-\t};\n-\n-\ti2c1: i2c@ff660000 {\n-\t\tcompatible = \"rockchip,rk3368-i2c\", \"rockchip,rk3288-i2c\";\n-\t\treg = <0x0 0xff660000 0x0 0x1000>;\n-\t\tinterrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;\n-\t\t#address-cells = <1>;\n-\t\t#size-cells = <0>;\n-\t\tclock-names = \"i2c\";\n-\t\tclocks = <&cru PCLK_I2C1>;\n-\t\tpinctrl-names = \"default\";\n-\t\tpinctrl-0 = <&i2c1_xfer>;\n-\t\tstatus = \"disabled\";\n-\t};\n-\n-\tpwm0: pwm@ff680000 {\n-\t\tcompatible = \"rockchip,rk3368-pwm\", \"rockchip,rk3288-pwm\";\n-\t\treg = <0x0 0xff680000 0x0 0x10>;\n-\t\t#pwm-cells = <3>;\n-\t\tpinctrl-names = \"default\";\n-\t\tpinctrl-0 = <&pwm0_pin>;\n-\t\tclocks = <&cru PCLK_PWM1>;\n-\t\tstatus = \"disabled\";\n-\t};\n-\n-\tpwm1: pwm@ff680010 {\n-\t\tcompatible = \"rockchip,rk3368-pwm\", \"rockchip,rk3288-pwm\";\n-\t\treg = <0x0 0xff680010 0x0 0x10>;\n-\t\t#pwm-cells = <3>;\n-\t\tpinctrl-names = \"default\";\n-\t\tpinctrl-0 = <&pwm1_pin>;\n-\t\tclocks = <&cru PCLK_PWM1>;\n-\t\tstatus = \"disabled\";\n-\t};\n-\n-\tpwm2: pwm@ff680020 {\n-\t\tcompatible = \"rockchip,rk3368-pwm\", \"rockchip,rk3288-pwm\";\n-\t\treg = <0x0 0xff680020 0x0 0x10>;\n-\t\t#pwm-cells = <3>;\n-\t\tclocks = <&cru PCLK_PWM1>;\n-\t\tstatus = \"disabled\";\n-\t};\n-\n-\tpwm3: pwm@ff680030 {\n-\t\tcompatible = \"rockchip,rk3368-pwm\", \"rockchip,rk3288-pwm\";\n-\t\treg = <0x0 0xff680030 0x0 0x10>;\n-\t\t#pwm-cells = <3>;\n-\t\tpinctrl-names = \"default\";\n-\t\tpinctrl-0 = <&pwm3_pin>;\n-\t\tclocks = <&cru PCLK_PWM1>;\n-\t\tstatus = \"disabled\";\n-\t};\n-\n-\tuart2: serial@ff690000 {\n-\t\tcompatible = \"rockchip,rk3368-uart\", \"snps,dw-apb-uart\";\n-\t\treg = <0x0 0xff690000 0x0 0x100>;\n-\t\tclocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;\n-\t\tclock-names = \"baudclk\", \"apb_pclk\";\n-\t\tinterrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;\n-\t\tpinctrl-names = \"default\";\n-\t\tpinctrl-0 = <&uart2_xfer>;\n-\t\treg-shift = <2>;\n-\t\treg-io-width = <4>;\n-\t\tstatus = \"disabled\";\n-\t};\n-\n-\tmbox: mbox@ff6b0000 {\n-\t\tcompatible = \"rockchip,rk3368-mailbox\";\n-\t\treg = <0x0 0xff6b0000 0x0 0x1000>;\n-\t\tinterrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,\n-\t\t\t     <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,\n-\t\t\t     <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,\n-\t\t\t     <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;\n-\t\tclocks = <&cru PCLK_MAILBOX>;\n-\t\tclock-names = \"pclk_mailbox\";\n-\t\t#mbox-cells = <1>;\n-\t\tstatus = \"disabled\";\n-\t};\n-\n-\tpmugrf: syscon@ff738000 {\n-\t\tcompatible = \"rockchip,rk3368-pmugrf\", \"syscon\", \"simple-mfd\";\n-\t\treg = <0x0 0xff738000 0x0 0x1000>;\n-\n-\t\tpmu_io_domains: io-domains {\n-\t\t\tcompatible = \"rockchip,rk3368-pmu-io-voltage-domain\";\n-\t\t\tstatus = \"disabled\";\n-\t\t};\n-\n-\t\treboot-mode {\n-\t\t\tcompatible = \"syscon-reboot-mode\";\n-\t\t\toffset = <0x200>;\n-\t\t\tmode-normal = <BOOT_NORMAL>;\n-\t\t\tmode-recovery = <BOOT_RECOVERY>;\n-\t\t\tmode-bootloader = <BOOT_FASTBOOT>;\n-\t\t\tmode-loader = <BOOT_BL_DOWNLOAD>;\n-\t\t};\n-\t};\n-\n-\tcru: clock-controller@ff760000 {\n-\t\tcompatible = \"rockchip,rk3368-cru\";\n-\t\treg = <0x0 0xff760000 0x0 0x1000>;\n-\t\trockchip,grf = <&grf>;\n-\t\t#clock-cells = <1>;\n-\t\t#reset-cells = <1>;\n-\t};\n-\n-\tgrf: syscon@ff770000 {\n-\t\tcompatible = \"rockchip,rk3368-grf\", \"syscon\", \"simple-mfd\";\n-\t\treg = <0x0 0xff770000 0x0 0x1000>;\n-\n-\t\tio_domains: io-domains {\n-\t\t\tcompatible = \"rockchip,rk3368-io-voltage-domain\";\n-\t\t\tstatus = \"disabled\";\n-\t\t};\n-\t};\n-\n-\twdt: watchdog@ff800000 {\n-\t\tcompatible = \"rockchip,rk3368-wdt\", \"snps,dw-wdt\";\n-\t\treg = <0x0 0xff800000 0x0 0x100>;\n-\t\tclocks = <&cru PCLK_WDT>;\n-\t\tinterrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;\n-\t\tstatus = \"disabled\";\n-\t};\n-\n-\ttimer0: timer@ff810000 {\n-\t\tcompatible = \"rockchip,rk3368-timer\", \"rockchip,rk3288-timer\";\n-\t\treg = <0x0 0xff810000 0x0 0x20>;\n-\t\tinterrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;\n-\t\tclocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>;\n-\t\tclock-names = \"pclk\", \"timer\";\n-\t};\n-\n-\tspdif: spdif@ff880000 {\n-\t\tcompatible = \"rockchip,rk3368-spdif\";\n-\t\treg = <0x0 0xff880000 0x0 0x1000>;\n-\t\tinterrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;\n-\t\tclocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;\n-\t\tclock-names = \"mclk\", \"hclk\";\n-\t\tdmas = <&dmac_bus 3>;\n-\t\tdma-names = \"tx\";\n-\t\tpinctrl-names = \"default\";\n-\t\tpinctrl-0 = <&spdif_tx>;\n-\t\tstatus = \"disabled\";\n-\t};\n-\n-\ti2s_2ch: i2s-2ch@ff890000 {\n-\t\tcompatible = \"rockchip,rk3368-i2s\", \"rockchip,rk3066-i2s\";\n-\t\treg = <0x0 0xff890000 0x0 0x1000>;\n-\t\tinterrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;\n-\t\tclock-names = \"i2s_clk\", \"i2s_hclk\";\n-\t\tclocks = <&cru SCLK_I2S_2CH>, <&cru HCLK_I2S_2CH>;\n-\t\tdmas = <&dmac_bus 6>, <&dmac_bus 7>;\n-\t\tdma-names = \"tx\", \"rx\";\n-\t\tstatus = \"disabled\";\n-\t};\n-\n-\ti2s_8ch: i2s-8ch@ff898000 {\n-\t\tcompatible = \"rockchip,rk3368-i2s\", \"rockchip,rk3066-i2s\";\n-\t\treg = <0x0 0xff898000 0x0 0x1000>;\n-\t\tinterrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;\n-\t\tclock-names = \"i2s_clk\", \"i2s_hclk\";\n-\t\tclocks = <&cru SCLK_I2S_8CH>, <&cru HCLK_I2S_8CH>;\n-\t\tdmas = <&dmac_bus 0>, <&dmac_bus 1>;\n-\t\tdma-names = \"tx\", \"rx\";\n-\t\tpinctrl-names = \"default\";\n-\t\tpinctrl-0 = <&i2s_8ch_bus>;\n-\t\tstatus = \"disabled\";\n-\t};\n-\n-\tiep_mmu: iommu@ff900800 {\n-\t\tcompatible = \"rockchip,iommu\";\n-\t\treg = <0x0 0xff900800 0x0 0x100>;\n-\t\tinterrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;\n-\t\tinterrupt-names = \"iep_mmu\";\n-\t\tclocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;\n-\t\tclock-names = \"aclk\", \"iface\";\n-\t\t#iommu-cells = <0>;\n-\t\tstatus = \"disabled\";\n-\t};\n-\n-\tisp_mmu: iommu@ff914000 {\n-\t\tcompatible = \"rockchip,iommu\";\n-\t\treg = <0x0 0xff914000 0x0 0x100>,\n-\t\t      <0x0 0xff915000 0x0 0x100>;\n-\t\tinterrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;\n-\t\tinterrupt-names = \"isp_mmu\";\n-\t\tclocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>;\n-\t\tclock-names = \"aclk\", \"iface\";\n-\t\t#iommu-cells = <0>;\n-\t\trockchip,disable-mmu-reset;\n-\t\tstatus = \"disabled\";\n-\t};\n-\n-\tvop_mmu: iommu@ff930300 {\n-\t\tcompatible = \"rockchip,iommu\";\n-\t\treg = <0x0 0xff930300 0x0 0x100>;\n-\t\tinterrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;\n-\t\tinterrupt-names = \"vop_mmu\";\n-\t\tclocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;\n-\t\tclock-names = \"aclk\", \"iface\";\n-\t\t#iommu-cells = <0>;\n-\t\tstatus = \"disabled\";\n-\t};\n-\n-\thevc_mmu: iommu@ff9a0440 {\n-\t\tcompatible = \"rockchip,iommu\";\n-\t\treg = <0x0 0xff9a0440 0x0 0x40>,\n-\t\t      <0x0 0xff9a0480 0x0 0x40>;\n-\t\tinterrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;\n-\t\tinterrupt-names = \"hevc_mmu\";\n-\t\tclocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>;\n-\t\tclock-names = \"aclk\", \"iface\";\n-\t\t#iommu-cells = <0>;\n-\t\tstatus = \"disabled\";\n-\t};\n-\n-\tvpu_mmu: iommu@ff9a0800 {\n-\t\tcompatible = \"rockchip,iommu\";\n-\t\treg = <0x0 0xff9a0800 0x0 0x100>;\n-\t\tinterrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,\n-\t\t\t     <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;\n-\t\tinterrupt-names = \"vepu_mmu\", \"vdpu_mmu\";\n-\t\tclocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>;\n-\t\tclock-names = \"aclk\", \"iface\";\n-\t\t#iommu-cells = <0>;\n-\t\tstatus = \"disabled\";\n-\t};\n-\n-\tefuse256: efuse@ffb00000 {\n-\t\tcompatible = \"rockchip,rk3368-efuse\";\n-\t\treg = <0x0 0xffb00000 0x0 0x20>;\n-\t\t#address-cells = <1>;\n-\t\t#size-cells = <1>;\n-\t\tclocks = <&cru PCLK_EFUSE256>;\n-\t\tclock-names = \"pclk_efuse\";\n-\n-\t\tcpu_leakage: cpu-leakage@17 {\n-\t\t\treg = <0x17 0x1>;\n-\t\t};\n-\t\ttemp_adjust: temp-adjust@1f {\n-\t\t\treg = <0x1f 0x1>;\n-\t\t};\n-\t};\n-\n-\tgic: interrupt-controller@ffb71000 {\n-\t\tcompatible = \"arm,gic-400\";\n-\t\tinterrupt-controller;\n-\t\t#interrupt-cells = <3>;\n-\t\t#address-cells = <0>;\n-\n-\t\treg = <0x0 0xffb71000 0x0 0x1000>,\n-\t\t      <0x0 0xffb72000 0x0 0x2000>,\n-\t\t      <0x0 0xffb74000 0x0 0x2000>,\n-\t\t      <0x0 0xffb76000 0x0 0x2000>;\n-\t\tinterrupts = <GIC_PPI 9\n-\t\t      (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;\n-\t};\n-\n-\tpinctrl: pinctrl {\n-\t\tcompatible = \"rockchip,rk3368-pinctrl\";\n-\t\trockchip,grf = <&grf>;\n-\t\trockchip,pmu = <&pmugrf>;\n-\t\t#address-cells = <0x2>;\n-\t\t#size-cells = <0x2>;\n-\t\tranges;\n-\n-\t\tgpio0: gpio0@ff750000 {\n-\t\t\tcompatible = \"rockchip,gpio-bank\";\n-\t\t\treg = <0x0 0xff750000 0x0 0x100>;\n-\t\t\tclocks = <&cru PCLK_GPIO0>;\n-\t\t\tinterrupts = <GIC_SPI 0x51 IRQ_TYPE_LEVEL_HIGH>;\n-\n-\t\t\tgpio-controller;\n-\t\t\t#gpio-cells = <0x2>;\n-\n-\t\t\tinterrupt-controller;\n-\t\t\t#interrupt-cells = <0x2>;\n-\t\t};\n-\n-\t\tgpio1: gpio1@ff780000 {\n-\t\t\tcompatible = \"rockchip,gpio-bank\";\n-\t\t\treg = <0x0 0xff780000 0x0 0x100>;\n-\t\t\tclocks = <&cru PCLK_GPIO1>;\n-\t\t\tinterrupts = <GIC_SPI 0x52 IRQ_TYPE_LEVEL_HIGH>;\n-\n-\t\t\tgpio-controller;\n-\t\t\t#gpio-cells = <0x2>;\n-\n-\t\t\tinterrupt-controller;\n-\t\t\t#interrupt-cells = <0x2>;\n-\t\t};\n-\n-\t\tgpio2: gpio2@ff790000 {\n-\t\t\tcompatible = \"rockchip,gpio-bank\";\n-\t\t\treg = <0x0 0xff790000 0x0 0x100>;\n-\t\t\tclocks = <&cru PCLK_GPIO2>;\n-\t\t\tinterrupts = <GIC_SPI 0x53 IRQ_TYPE_LEVEL_HIGH>;\n-\n-\t\t\tgpio-controller;\n-\t\t\t#gpio-cells = <0x2>;\n-\n-\t\t\tinterrupt-controller;\n-\t\t\t#interrupt-cells = <0x2>;\n-\t\t};\n-\n-\t\tgpio3: gpio3@ff7a0000 {\n-\t\t\tcompatible = \"rockchip,gpio-bank\";\n-\t\t\treg = <0x0 0xff7a0000 0x0 0x100>;\n-\t\t\tclocks = <&cru PCLK_GPIO3>;\n-\t\t\tinterrupts = <GIC_SPI 0x54 IRQ_TYPE_LEVEL_HIGH>;\n-\n-\t\t\tgpio-controller;\n-\t\t\t#gpio-cells = <0x2>;\n-\n-\t\t\tinterrupt-controller;\n-\t\t\t#interrupt-cells = <0x2>;\n-\t\t};\n-\n-\t\tpcfg_pull_up: pcfg-pull-up {\n-\t\t\tbias-pull-up;\n-\t\t};\n-\n-\t\tpcfg_pull_down: pcfg-pull-down {\n-\t\t\tbias-pull-down;\n-\t\t};\n-\n-\t\tpcfg_pull_none: pcfg-pull-none {\n-\t\t\tbias-disable;\n-\t\t};\n-\n-\t\tpcfg_pull_none_12ma: pcfg-pull-none-12ma {\n-\t\t\tbias-disable;\n-\t\t\tdrive-strength = <12>;\n-\t\t};\n-\n-\t\temmc {\n-\t\t\temmc_clk: emmc-clk {\n-\t\t\t\trockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>;\n-\t\t\t};\n-\n-\t\t\temmc_cmd: emmc-cmd {\n-\t\t\t\trockchip,pins = <1 RK_PD2 2 &pcfg_pull_up>;\n-\t\t\t};\n-\n-\t\t\temmc_pwr: emmc-pwr {\n-\t\t\t\trockchip,pins = <1 RK_PD3 2 &pcfg_pull_up>;\n-\t\t\t};\n-\n-\t\t\temmc_bus1: emmc-bus1 {\n-\t\t\t\trockchip,pins = <1 RK_PC2 2 &pcfg_pull_up>;\n-\t\t\t};\n-\n-\t\t\temmc_bus4: emmc-bus4 {\n-\t\t\t\trockchip,pins = <1 RK_PC2 2 &pcfg_pull_up>,\n-\t\t\t\t\t\t<1 RK_PC3 2 &pcfg_pull_up>,\n-\t\t\t\t\t\t<1 RK_PC4 2 &pcfg_pull_up>,\n-\t\t\t\t\t\t<1 RK_PC5 2 &pcfg_pull_up>;\n-\t\t\t};\n-\n-\t\t\temmc_bus8: emmc-bus8 {\n-\t\t\t\trockchip,pins = <1 RK_PC2 2 &pcfg_pull_up>,\n-\t\t\t\t\t\t<1 RK_PC3 2 &pcfg_pull_up>,\n-\t\t\t\t\t\t<1 RK_PC4 2 &pcfg_pull_up>,\n-\t\t\t\t\t\t<1 RK_PC5 2 &pcfg_pull_up>,\n-\t\t\t\t\t\t<1 RK_PC6 2 &pcfg_pull_up>,\n-\t\t\t\t\t\t<1 RK_PC7 2 &pcfg_pull_up>,\n-\t\t\t\t\t\t<1 RK_PD0 2 &pcfg_pull_up>,\n-\t\t\t\t\t\t<1 RK_PD1 2 &pcfg_pull_up>;\n-\t\t\t};\n-\t\t};\n-\n-\t\tgmac {\n-\t\t\trgmii_pins: rgmii-pins {\n-\t\t\t\trockchip,pins =\t<3 RK_PC6 1 &pcfg_pull_none>,\n-\t\t\t\t\t\t<3 RK_PD0 1 &pcfg_pull_none>,\n-\t\t\t\t\t\t<3 RK_PC3 1 &pcfg_pull_none>,\n-\t\t\t\t\t\t<3 RK_PB0 1 &pcfg_pull_none_12ma>,\n-\t\t\t\t\t\t<3 RK_PB1 1 &pcfg_pull_none_12ma>,\n-\t\t\t\t\t\t<3 RK_PB2 1 &pcfg_pull_none_12ma>,\n-\t\t\t\t\t\t<3 RK_PB6 1 &pcfg_pull_none_12ma>,\n-\t\t\t\t\t\t<3 RK_PD4 1 &pcfg_pull_none_12ma>,\n-\t\t\t\t\t\t<3 RK_PB5 1 &pcfg_pull_none_12ma>,\n-\t\t\t\t\t\t<3 RK_PB7 1 &pcfg_pull_none>,\n-\t\t\t\t\t\t<3 RK_PC0 1 &pcfg_pull_none>,\n-\t\t\t\t\t\t<3 RK_PC1 1 &pcfg_pull_none>,\n-\t\t\t\t\t\t<3 RK_PC2 1 &pcfg_pull_none>,\n-\t\t\t\t\t\t<3 RK_PD1 1 &pcfg_pull_none>,\n-\t\t\t\t\t\t<3 RK_PC4 1 &pcfg_pull_none>;\n-\t\t\t};\n-\n-\t\t\trmii_pins: rmii-pins {\n-\t\t\t\trockchip,pins =\t<3 RK_PC6 1 &pcfg_pull_none>,\n-\t\t\t\t\t\t<3 RK_PD0 1 &pcfg_pull_none>,\n-\t\t\t\t\t\t<3 RK_PC3 1 &pcfg_pull_none>,\n-\t\t\t\t\t\t<3 RK_PB0 1 &pcfg_pull_none_12ma>,\n-\t\t\t\t\t\t<3 RK_PB1 1 &pcfg_pull_none_12ma>,\n-\t\t\t\t\t\t<3 RK_PB5 1 &pcfg_pull_none_12ma>,\n-\t\t\t\t\t\t<3 RK_PB7 1 &pcfg_pull_none>,\n-\t\t\t\t\t\t<3 RK_PC0 1 &pcfg_pull_none>,\n-\t\t\t\t\t\t<3 RK_PC4 1 &pcfg_pull_none>,\n-\t\t\t\t\t\t<3 RK_PC5 1 &pcfg_pull_none>;\n-\t\t\t};\n-\t\t};\n-\n-\t\ti2c0 {\n-\t\t\ti2c0_xfer: i2c0-xfer {\n-\t\t\t\trockchip,pins = <0 RK_PA6 1 &pcfg_pull_none>,\n-\t\t\t\t\t\t<0 RK_PA7 1 &pcfg_pull_none>;\n-\t\t\t};\n-\t\t};\n-\n-\t\ti2c1 {\n-\t\t\ti2c1_xfer: i2c1-xfer {\n-\t\t\t\trockchip,pins = <2 RK_PC5 1 &pcfg_pull_none>,\n-\t\t\t\t\t\t<2 RK_PC6 1 &pcfg_pull_none>;\n-\t\t\t};\n-\t\t};\n-\n-\t\ti2c2 {\n-\t\t\ti2c2_xfer: i2c2-xfer {\n-\t\t\t\trockchip,pins = <0 RK_PB1 2 &pcfg_pull_none>,\n-\t\t\t\t\t\t<3 RK_PD7 2 &pcfg_pull_none>;\n-\t\t\t};\n-\t\t};\n-\n-\t\ti2c3 {\n-\t\t\ti2c3_xfer: i2c3-xfer {\n-\t\t\t\trockchip,pins = <1 RK_PC0 1 &pcfg_pull_none>,\n-\t\t\t\t\t\t<1 RK_PC1 1 &pcfg_pull_none>;\n-\t\t\t};\n-\t\t};\n-\n-\t\ti2c4 {\n-\t\t\ti2c4_xfer: i2c4-xfer {\n-\t\t\t\trockchip,pins = <3 RK_PD0 2 &pcfg_pull_none>,\n-\t\t\t\t\t\t<3 RK_PD1 2 &pcfg_pull_none>;\n-\t\t\t};\n-\t\t};\n-\n-\t\ti2c5 {\n-\t\t\ti2c5_xfer: i2c5-xfer {\n-\t\t\t\trockchip,pins = <3 RK_PD2 2 &pcfg_pull_none>,\n-\t\t\t\t\t\t<3 RK_PD3 2 &pcfg_pull_none>;\n-\t\t\t};\n-\t\t};\n-\n-\t\ti2s {\n-\t\t\ti2s_8ch_bus: i2s-8ch-bus {\n-\t\t\t\trockchip,pins = <2 RK_PB4 1 &pcfg_pull_none>,\n-\t\t\t\t\t\t<2 RK_PB5 1 &pcfg_pull_none>,\n-\t\t\t\t\t\t<2 RK_PB6 1 &pcfg_pull_none>,\n-\t\t\t\t\t\t<2 RK_PB7 1 &pcfg_pull_none>,\n-\t\t\t\t\t\t<2 RK_PC0 1 &pcfg_pull_none>,\n-\t\t\t\t\t\t<2 RK_PC1 1 &pcfg_pull_none>,\n-\t\t\t\t\t\t<2 RK_PC2 1 &pcfg_pull_none>,\n-\t\t\t\t\t\t<2 RK_PC3 1 &pcfg_pull_none>,\n-\t\t\t\t\t\t<2 RK_PC4 1 &pcfg_pull_none>;\n-\t\t\t};\n-\t\t};\n-\n-\t\tpwm0 {\n-\t\t\tpwm0_pin: pwm0-pin {\n-\t\t\t\trockchip,pins = <3 RK_PB0 2 &pcfg_pull_none>;\n-\t\t\t};\n-\t\t};\n-\n-\t\tpwm1 {\n-\t\t\tpwm1_pin: pwm1-pin {\n-\t\t\t\trockchip,pins = <0 RK_PB0 2 &pcfg_pull_none>;\n-\t\t\t};\n-\t\t};\n-\n-\t\tpwm3 {\n-\t\t\tpwm3_pin: pwm3-pin {\n-\t\t\t\trockchip,pins = <3 RK_PD5 3 &pcfg_pull_none>;\n-\t\t\t};\n-\t\t};\n-\n-\t\tsdio0 {\n-\t\t\tsdio0_bus1: sdio0-bus1 {\n-\t\t\t\trockchip,pins = <2 RK_PD4 1 &pcfg_pull_up>;\n-\t\t\t};\n-\n-\t\t\tsdio0_bus4: sdio0-bus4 {\n-\t\t\t\trockchip,pins = <2 RK_PD4 1 &pcfg_pull_up>,\n-\t\t\t\t\t\t<2 RK_PD5 1 &pcfg_pull_up>,\n-\t\t\t\t\t\t<2 RK_PD6 1 &pcfg_pull_up>,\n-\t\t\t\t\t\t<2 RK_PD7 1 &pcfg_pull_up>;\n-\t\t\t};\n-\n-\t\t\tsdio0_cmd: sdio0-cmd {\n-\t\t\t\trockchip,pins = <3 RK_PA0 1 &pcfg_pull_up>;\n-\t\t\t};\n-\n-\t\t\tsdio0_clk: sdio0-clk {\n-\t\t\t\trockchip,pins = <3 RK_PA1 1 &pcfg_pull_none>;\n-\t\t\t};\n-\n-\t\t\tsdio0_cd: sdio0-cd {\n-\t\t\t\trockchip,pins = <3 RK_PA2 1 &pcfg_pull_up>;\n-\t\t\t};\n-\n-\t\t\tsdio0_wp: sdio0-wp {\n-\t\t\t\trockchip,pins = <3 RK_PA3 1 &pcfg_pull_up>;\n-\t\t\t};\n-\n-\t\t\tsdio0_pwr: sdio0-pwr {\n-\t\t\t\trockchip,pins = <3 RK_PA4 1 &pcfg_pull_up>;\n-\t\t\t};\n-\n-\t\t\tsdio0_bkpwr: sdio0-bkpwr {\n-\t\t\t\trockchip,pins = <3 RK_PA5 1 &pcfg_pull_up>;\n-\t\t\t};\n-\n-\t\t\tsdio0_int: sdio0-int {\n-\t\t\t\trockchip,pins = <3 RK_PA6 1 &pcfg_pull_up>;\n-\t\t\t};\n-\t\t};\n-\n-\t\tsdmmc {\n-\t\t\tsdmmc_clk: sdmmc-clk {\n-\t\t\t\trockchip,pins = <2 RK_PB1 1 &pcfg_pull_none>;\n-\t\t\t};\n-\n-\t\t\tsdmmc_cmd: sdmmc-cmd {\n-\t\t\t\trockchip,pins = <2 RK_PB2 1 &pcfg_pull_up>;\n-\t\t\t};\n-\n-\t\t\tsdmmc_cd: sdmmc-cd {\n-\t\t\t\trockchip,pins = <2 RK_PB3 1 &pcfg_pull_up>;\n-\t\t\t};\n-\n-\t\t\tsdmmc_bus1: sdmmc-bus1 {\n-\t\t\t\trockchip,pins = <2 RK_PA5 1 &pcfg_pull_up>;\n-\t\t\t};\n-\n-\t\t\tsdmmc_bus4: sdmmc-bus4 {\n-\t\t\t\trockchip,pins = <2 RK_PA5 1 &pcfg_pull_up>,\n-\t\t\t\t\t\t<2 RK_PA6 1 &pcfg_pull_up>,\n-\t\t\t\t\t\t<2 RK_PA7 1 &pcfg_pull_up>,\n-\t\t\t\t\t\t<2 RK_PB0 1 &pcfg_pull_up>;\n-\t\t\t};\n-\t\t};\n-\n-\t\tspdif {\n-\t\t\tspdif_tx: spdif-tx {\n-\t\t\t\trockchip,pins =\t<2 RK_PC7 1 &pcfg_pull_none>;\n-\t\t\t};\n-\t\t};\n-\n-\t\tspi0 {\n-\t\t\tspi0_clk: spi0-clk {\n-\t\t\t\trockchip,pins = <1 RK_PD5 2 &pcfg_pull_up>;\n-\t\t\t};\n-\t\t\tspi0_cs0: spi0-cs0 {\n-\t\t\t\trockchip,pins = <1 RK_PD0 3 &pcfg_pull_up>;\n-\t\t\t};\n-\t\t\tspi0_cs1: spi0-cs1 {\n-\t\t\t\trockchip,pins = <1 RK_PD1 3 &pcfg_pull_up>;\n-\t\t\t};\n-\t\t\tspi0_tx: spi0-tx {\n-\t\t\t\trockchip,pins = <1 RK_PC7 3 &pcfg_pull_up>;\n-\t\t\t};\n-\t\t\tspi0_rx: spi0-rx {\n-\t\t\t\trockchip,pins = <1 RK_PC6 3 &pcfg_pull_up>;\n-\t\t\t};\n-\t\t};\n-\n-\t\tspi1 {\n-\t\t\tspi1_clk: spi1-clk {\n-\t\t\t\trockchip,pins = <1 RK_PB6 2 &pcfg_pull_up>;\n-\t\t\t};\n-\t\t\tspi1_cs0: spi1-cs0 {\n-\t\t\t\trockchip,pins = <1 RK_PB7 2 &pcfg_pull_up>;\n-\t\t\t};\n-\t\t\tspi1_cs1: spi1-cs1 {\n-\t\t\t\trockchip,pins = <3 RK_PD4 2 &pcfg_pull_up>;\n-\t\t\t};\n-\t\t\tspi1_rx: spi1-rx {\n-\t\t\t\trockchip,pins = <1 RK_PC0 2 &pcfg_pull_up>;\n-\t\t\t};\n-\t\t\tspi1_tx: spi1-tx {\n-\t\t\t\trockchip,pins = <1 RK_PC1 2 &pcfg_pull_up>;\n-\t\t\t};\n-\t\t};\n-\n-\t\tspi2 {\n-\t\t\tspi2_clk: spi2-clk {\n-\t\t\t\trockchip,pins = <0 RK_PB4 2 &pcfg_pull_up>;\n-\t\t\t};\n-\t\t\tspi2_cs0: spi2-cs0 {\n-\t\t\t\trockchip,pins = <0 RK_PB5 2 &pcfg_pull_up>;\n-\t\t\t};\n-\t\t\tspi2_rx: spi2-rx {\n-\t\t\t\trockchip,pins = <0 RK_PB2 2 &pcfg_pull_up>;\n-\t\t\t};\n-\t\t\tspi2_tx: spi2-tx {\n-\t\t\t\trockchip,pins = <0 RK_PB3 2 &pcfg_pull_up>;\n-\t\t\t};\n-\t\t};\n-\n-\t\ttsadc {\n-\t\t\totp_pin: otp-pin {\n-\t\t\t\trockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;\n-\t\t\t};\n-\n-\t\t\totp_out: otp-out {\n-\t\t\t\trockchip,pins = <0 RK_PA3 1 &pcfg_pull_none>;\n-\t\t\t};\n-\t\t};\n-\n-\t\tuart0 {\n-\t\t\tuart0_xfer: uart0-xfer {\n-\t\t\t\trockchip,pins = <2 RK_PD0 1 &pcfg_pull_up>,\n-\t\t\t\t\t\t<2 RK_PD1 1 &pcfg_pull_none>;\n-\t\t\t};\n-\n-\t\t\tuart0_cts: uart0-cts {\n-\t\t\t\trockchip,pins = <2 RK_PD2 1 &pcfg_pull_none>;\n-\t\t\t};\n-\n-\t\t\tuart0_rts: uart0-rts {\n-\t\t\t\trockchip,pins = <2 RK_PD3 1 &pcfg_pull_none>;\n-\t\t\t};\n-\t\t};\n-\n-\t\tuart1 {\n-\t\t\tuart1_xfer: uart1-xfer {\n-\t\t\t\trockchip,pins = <0 RK_PC4 3 &pcfg_pull_up>,\n-\t\t\t\t\t\t<0 RK_PC5 3 &pcfg_pull_none>;\n-\t\t\t};\n-\n-\t\t\tuart1_cts: uart1-cts {\n-\t\t\t\trockchip,pins = <0 RK_PC6 3 &pcfg_pull_none>;\n-\t\t\t};\n-\n-\t\t\tuart1_rts: uart1-rts {\n-\t\t\t\trockchip,pins = <0 RK_PC7 3 &pcfg_pull_none>;\n-\t\t\t};\n-\t\t};\n-\n-\t\tuart2 {\n-\t\t\tuart2_xfer: uart2-xfer {\n-\t\t\t\trockchip,pins = <2 RK_PA6 2 &pcfg_pull_up>,\n-\t\t\t\t\t\t<2 RK_PA5 2 &pcfg_pull_none>;\n-\t\t\t};\n-\t\t\t/* no rts / cts for uart2 */\n-\t\t};\n-\n-\t\tuart3 {\n-\t\t\tuart3_xfer: uart3-xfer {\n-\t\t\t\trockchip,pins = <3 RK_PD5 2 &pcfg_pull_up>,\n-\t\t\t\t\t\t<3 RK_PD6 3 &pcfg_pull_none>;\n-\t\t\t};\n-\n-\t\t\tuart3_cts: uart3-cts {\n-\t\t\t\trockchip,pins = <3 RK_PC0 2 &pcfg_pull_none>;\n-\t\t\t};\n-\n-\t\t\tuart3_rts: uart3-rts {\n-\t\t\t\trockchip,pins = <3 RK_PC1 2 &pcfg_pull_none>;\n-\t\t\t};\n-\t\t};\n-\n-\t\tuart4 {\n-\t\t\tuart4_xfer: uart4-xfer {\n-\t\t\t\trockchip,pins = <0 RK_PD3 3 &pcfg_pull_up>,\n-\t\t\t\t\t\t<0 RK_PD2 3 &pcfg_pull_none>;\n-\t\t\t};\n-\n-\t\t\tuart4_cts: uart4-cts {\n-\t\t\t\trockchip,pins = <0 RK_PD0 3 &pcfg_pull_none>;\n-\t\t\t};\n-\n-\t\t\tuart4_rts: uart4-rts {\n-\t\t\t\trockchip,pins = <0 RK_PD1 3 &pcfg_pull_none>;\n-\t\t\t};\n-\t\t};\n-\t};\n-};\ndiff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig\nindex d92fcae2bb56..1cb19f2c909e 100644\n--- a/arch/arm/mach-rockchip/Kconfig\n+++ b/arch/arm/mach-rockchip/Kconfig\n@@ -233,6 +233,7 @@ config ROCKCHIP_RK3368\n \tselect SUPPORT_SPL\n \tselect SUPPORT_TPL\n \tselect TPL_HAVE_INIT_STACK if TPL\n+\timply OF_UPSTREAM\n \timply ROCKCHIP_COMMON_BOARD\n \timply SPL_ROCKCHIP_COMMON_BOARD\n \timply SPL_SEPARATE_BSS\ndiff --git a/configs/evb-px5_defconfig b/configs/evb-px5_defconfig\nindex aac352113699..41564e484fb9 100644\n--- a/configs/evb-px5_defconfig\n+++ b/configs/evb-px5_defconfig\n@@ -7,7 +7,7 @@ CONFIG_NR_DRAM_BANKS=1\n CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y\n CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000\n CONFIG_ENV_OFFSET=0x3F8000\n-CONFIG_DEFAULT_DEVICE_TREE=\"rk3368-px5-evb\"\n+CONFIG_DEFAULT_DEVICE_TREE=\"rockchip/rk3368-px5-evb\"\n CONFIG_DM_RESET=y\n CONFIG_ROCKCHIP_RK3368=y\n CONFIG_TPL_LDSCRIPT=\"arch/arm/mach-rockchip/u-boot-tpl-v8.lds\"\ndiff --git a/configs/geekbox_defconfig b/configs/geekbox_defconfig\nindex 42b5c0c38a88..c2fd98d43e52 100644\n--- a/configs/geekbox_defconfig\n+++ b/configs/geekbox_defconfig\n@@ -7,7 +7,7 @@ CONFIG_SYS_MALLOC_F_LEN=0x1000\n CONFIG_NR_DRAM_BANKS=1\n CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y\n CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000\n-CONFIG_DEFAULT_DEVICE_TREE=\"rk3368-geekbox\"\n+CONFIG_DEFAULT_DEVICE_TREE=\"rockchip/rk3368-geekbox\"\n CONFIG_ROCKCHIP_RK3368=y\n CONFIG_TARGET_GEEKBOX=y\n CONFIG_SYS_LOAD_ADDR=0x800800\n",
    "prefixes": [
        "v2",
        "4/5"
    ]
}