Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/1.2/patches/2234525/?format=api
{ "id": 2234525, "url": "http://patchwork.ozlabs.org/api/1.2/patches/2234525/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/3d1a006b-3e39-4e5d-827c-2ce74ef1e6c2@gmail.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/1.2/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<3d1a006b-3e39-4e5d-827c-2ce74ef1e6c2@gmail.com>", "list_archive_url": null, "date": "2026-05-07T18:38:03", "name": "[v2,2/5] rockchip: Switch rk3229 boards to upstream devicetree", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "5150efad30df3becd1b64bb7001d28d43e2427de", "submitter": { "id": 75645, "url": "http://patchwork.ozlabs.org/api/1.2/people/75645/?format=api", "name": "Johan Jonker", "email": "jbx6244@gmail.com" }, "delegate": { "id": 93623, "url": "http://patchwork.ozlabs.org/api/1.2/users/93623/?format=api", "username": "kevery", "first_name": "Kever", "last_name": "Yang", "email": "ykai007@gmail.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/3d1a006b-3e39-4e5d-827c-2ce74ef1e6c2@gmail.com/mbox/", "series": [ { "id": 503246, "url": "http://patchwork.ozlabs.org/api/1.2/series/503246/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=503246", "date": "2026-05-07T18:34:48", "name": "rockchip: Switch remaining boards to upstream devicetree", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/503246/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2234525/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2234525/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=nw3KeIRB;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de;\n envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org)", "phobos.denx.de;\n dmarc=pass (p=none dis=none) header.from=gmail.com", "phobos.denx.de;\n spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de", "phobos.denx.de;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.b=\"nw3KeIRB\";\n\tdkim-atps=neutral", "phobos.denx.de;\n dmarc=pass (p=none dis=none) header.from=gmail.com", "phobos.denx.de;\n spf=pass smtp.mailfrom=jbx6244@gmail.com" ], "Received": [ "from phobos.denx.de (phobos.denx.de\n [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4gBLbr2CCgz1y04\n\tfor <incoming@patchwork.ozlabs.org>; Fri, 08 May 2026 04:38:16 +1000 (AEST)", "from h2850616.stratoserver.net (localhost [IPv6:::1])\n\tby phobos.denx.de (Postfix) with ESMTP id 399998490D;\n\tThu, 7 May 2026 20:38:14 +0200 (CEST)", "by phobos.denx.de (Postfix, from userid 109)\n id 0A60984A7B; Thu, 7 May 2026 20:38:12 +0200 (CEST)", "from mail-ej1-x632.google.com (mail-ej1-x632.google.com\n [IPv6:2a00:1450:4864:20::632])\n (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits))\n (No client certificate requested)\n by phobos.denx.de (Postfix) with ESMTPS id 37DE384099\n for <u-boot@lists.denx.de>; Thu, 7 May 2026 20:38:06 +0200 (CEST)", "by mail-ej1-x632.google.com with SMTP id\n a640c23a62f3a-bc49d30ceecso16188866b.3\n for <u-boot@lists.denx.de>; Thu, 07 May 2026 11:38:06 -0700 (PDT)", "from ?IPV6:2a02:a449:4071:0:32d0:42ff:fe10:6983?\n ([2a02:a449:4071:0:32d0:42ff:fe10:6983])\n by smtp.gmail.com with ESMTPSA id\n a640c23a62f3a-bca543d2d30sm17039166b.19.2026.05.07.11.38.04\n (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128);\n Thu, 07 May 2026 11:38:04 -0700 (PDT)" ], "X-Spam-Checker-Version": "SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de", "X-Spam-Level": "", "X-Spam-Status": "No, score=-0.8 required=5.0 tests=BAYES_00,DKIM_SIGNED,\n DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FORGED_GMAIL_RCVD,\n FREEMAIL_ENVFROM_END_DIGIT,FREEMAIL_FROM,RCVD_IN_DNSWL_BLOCKED,\n SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.2", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=gmail.com; s=20251104; t=1778179086; x=1778783886; darn=lists.denx.de;\n h=content-transfer-encoding:in-reply-to:content-language:references\n :cc:to:subject:from:user-agent:mime-version:date:message-id:from:to\n :cc:subject:date:message-id:reply-to;\n bh=m4RHtVQsqIJBSl79Nwcv3H+gMCq33EHy9UKGPpKrBwc=;\n b=nw3KeIRBxPkr/lYl35x6wu156VlAGVctty25WZmUeyYct23X21+JVz49jv60Qmckp8\n vRI0To0SOZm0G8Pu+WKp1X91357IktHOM6ZDE4jZiaeWQAsj5zNzjMp1z7wQismuypS6\n kKh9MKcwunvY+ofNm3LpvJ16hwVP0XGkduWnLVrmuLvIrjZXArbdkUBCdMVjm2k+hn1Z\n cdgbEd1be4HtzYUnToiSrjI3Ujw8kQTBG0/ITCg7nRYVLY4zQNiPQkUX1qeaXruy2xE4\n UOEhmx3DovRDzyiGmtY7Jpk5SnECn8gAQ8NZeaJok08SAT5FAYaztCMlrl3WFKhOq3eH\n /qgw==", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=1e100.net; s=20251104; t=1778179086; x=1778783886;\n h=content-transfer-encoding:in-reply-to:content-language:references\n :cc:to:subject:from:user-agent:mime-version:date:message-id:x-gm-gg\n :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to;\n bh=m4RHtVQsqIJBSl79Nwcv3H+gMCq33EHy9UKGPpKrBwc=;\n b=dOsiGV7QCeUjVYbTBo6uOQJAC3KeV9HrCK47q0fu229jnj73q0AVmCiZyOv2Ti+OJh\n 5zXIBLLNgVEA6pGJY32mVjxXazzTe60Cy67Li4VbSkhBvqLJ6J0+IxxkziE1bIA9tsya\n MvUzpOxOUrYkEFw7MAMBVWtQa/hH+K9diLtnQZxJ0FhFdLHCf56dd7P8uACBZzbNXtrX\n Nk6EHq+9MTn9F8KTnFlwje0P5UfFjorGL3d8Blj2nZvmraQVG5idgHYXOgI/5pcEs7rW\n 95GiM14LdxubNncT2GhniZddWCvNfcW4ZedfuZMjYuvUZWzRC92as4r0eMHB+NIAr9UD\n 59EA==", "X-Forwarded-Encrypted": "i=1;\n AFNElJ+6Bj3u9MecQQ18jHYRagGuX7UPeV9quqji4G7juWeEI+xK5JMJVurv+wxtfPx3ZzYuHhpjanw=@lists.denx.de", "X-Gm-Message-State": "AOJu0YwUddLevQsrYc+DcG9q3+wXcolyl/TCo4i4NqQqbzopwYs5cKPa\n 9GW60u2AQbeMYbvWI2SNg7SKpUiO7OIMexXi+/A5ByLjBoMM07CDQFqx", "X-Gm-Gg": "AeBDievScyjnpNfJiJa/K/0x9SCcMuz0zt2xaL39ygU1LiWew843DmWyPaXD7Tv6nSE\n A72CM5bmIqwUtVfxINvdQlI4cMRBfcq50Ey3Gcs3dSWXl6H2nAUeyq/7cQAH1z9w2ogiEx6n+Rt\n RLe5lPowngYtdMEQngZV26kwqPqQbFmFPWYOuQntlAupdjQgoNWNNL0pPdomQ8k1h3bhJdb6I4x\n v+MQjlApKhV9hbkl1GXVjbnkSbOOxZmNInUlrJq1xrC/Ysx36Wa+PHc4AVdJtcu20g6R0e8jND1\n j3Uuv7S5+IhgZIkTj9jHUnvZTUoPeYR1cAfAfnUuFqkChY3Z07pBrrqUv+2BlAexy64XmORiHYV\n 3sA4HKpL/BwrXUNr7z9wctdpxyoVYFkpBU1ZxxxJTKftgrQRaLWisg9qd/OemU3nRs27rc82tQF\n SeDCYjt2a6cd+CRzAxEYqlUWiRFww0Jhphv0wr8mmsmEZwMZe3oxyNUZUcEecOpiZRS0KPb4wb", "X-Received": "by 2002:a17:906:52d2:b0:bc6:3181:a990 with SMTP id\n a640c23a62f3a-bc63181aa04mr135252266b.0.1778179084917;\n Thu, 07 May 2026 11:38:04 -0700 (PDT)", "Message-ID": "<3d1a006b-3e39-4e5d-827c-2ce74ef1e6c2@gmail.com>", "Date": "Thu, 7 May 2026 20:38:03 +0200", "MIME-Version": "1.0", "User-Agent": "Mozilla Thunderbird", "From": "Johan Jonker <jbx6244@gmail.com>", "Subject": "[PATCH v2 2/5] rockchip: Switch rk3229 boards to upstream devicetree", "To": "kever.yang@rock-chips.com", "Cc": "philipp.tomsich@vrull.eu, sjg@chromium.org, trini@konsulko.com,\n afaerber@suse.de, andy.yan@rock-chips.com, u-boot@lists.denx.de,\n quentin.schulz@cherry.de", "References": "<a5bb85ba-c159-4ac0-a1e3-4be1c6db1441@gmail.com>", "Content-Language": "en-US, ar-EG", "In-Reply-To": "<a5bb85ba-c159-4ac0-a1e3-4be1c6db1441@gmail.com>", "Content-Type": "text/plain; charset=UTF-8", "Content-Transfer-Encoding": "7bit", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.39", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<https://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>", "X-Virus-Scanned": "clamav-milter 0.103.8 at phobos.denx.de", "X-Virus-Status": "Clean" }, "content": "Switch rk3229 boards to upstream devicetree.\n\nSigned-off-by: Johan Jonker <jbx6244@gmail.com>\n---\n\nChanged V2:\nremove rk322x.dtsi\n---\n arch/arm/dts/Makefile | 3 -\n arch/arm/dts/rk3229-evb.dts | 256 -----\n arch/arm/dts/rk3229.dtsi | 52 -\n arch/arm/dts/rk322x.dtsi | 1293 ------------------------\n arch/arm/mach-rockchip/Kconfig | 1 +\n board/rockchip/evb_rk3229/MAINTAINERS | 1 -\n configs/evb-rk3229_defconfig | 4 +-\n include/dt-bindings/clock/rk3228-cru.h | 287 ------\n 8 files changed, 3 insertions(+), 1894 deletions(-)\n delete mode 100644 arch/arm/dts/rk3229-evb.dts\n delete mode 100644 arch/arm/dts/rk3229.dtsi\n delete mode 100644 arch/arm/dts/rk322x.dtsi\n delete mode 100644 include/dt-bindings/clock/rk3228-cru.h\n\n--\n2.39.5", "diff": "diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile\nindex fdd057fdfe6c..7b2847804835 100644\n--- a/arch/arm/dts/Makefile\n+++ b/arch/arm/dts/Makefile\n@@ -52,9 +52,6 @@ dtb-$(CONFIG_MACH_S900) += \\\n dtb-$(CONFIG_MACH_S700) += \\\n \ts700-cubieboard7.dtb\n\n-dtb-$(CONFIG_ROCKCHIP_RK322X) += \\\n-\trk3229-evb.dtb\n-\n dtb-$(CONFIG_ROCKCHIP_RK3368) += \\\n \trk3368-sheep.dtb \\\n \trk3368-geekbox.dtb \\\ndiff --git a/arch/arm/dts/rk3229-evb.dts b/arch/arm/dts/rk3229-evb.dts\ndeleted file mode 100644\nindex 797476e8bef1..000000000000\n--- a/arch/arm/dts/rk3229-evb.dts\n+++ /dev/null\n@@ -1,256 +0,0 @@\n-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)\n-\n-/dts-v1/;\n-\n-#include <dt-bindings/input/input.h>\n-#include \"rk3229.dtsi\"\n-\n-/ {\n-\tmodel = \"Rockchip RK3229 Evaluation board\";\n-\tcompatible = \"rockchip,rk3229-evb\", \"rockchip,rk3229\";\n-\n-\taliases {\n-\t\tmmc0 = &emmc;\n-\t};\n-\n-\tmemory@60000000 {\n-\t\tdevice_type = \"memory\";\n-\t\treg = <0x60000000 0x40000000>;\n-\t};\n-\n-\tdc_12v: dc-12v-regulator {\n-\t\tcompatible = \"regulator-fixed\";\n-\t\tregulator-name = \"dc_12v\";\n-\t\tregulator-always-on;\n-\t\tregulator-boot-on;\n-\t\tregulator-min-microvolt = <12000000>;\n-\t\tregulator-max-microvolt = <12000000>;\n-\t};\n-\n-\text_gmac: ext_gmac {\n-\t\tcompatible = \"fixed-clock\";\n-\t\tclock-frequency = <125000000>;\n-\t\tclock-output-names = \"ext_gmac\";\n-\t\t#clock-cells = <0>;\n-\t};\n-\n-\tvcc_host: vcc-host-regulator {\n-\t\tcompatible = \"regulator-fixed\";\n-\t\tenable-active-high;\n-\t\tgpio = <&gpio3 RK_PC4 GPIO_ACTIVE_HIGH>;\n-\t\tpinctrl-names = \"default\";\n-\t\tpinctrl-0 = <&host_vbus_drv>;\n-\t\tregulator-name = \"vcc_host\";\n-\t\tregulator-always-on;\n-\t\tregulator-boot-on;\n-\t\tvin-supply = <&vcc_sys>;\n-\t};\n-\n-\tvcc_phy: vcc-phy-regulator {\n-\t\tcompatible = \"regulator-fixed\";\n-\t\tenable-active-high;\n-\t\tregulator-name = \"vcc_phy\";\n-\t\tregulator-min-microvolt = <1800000>;\n-\t\tregulator-max-microvolt = <1800000>;\n-\t\tregulator-always-on;\n-\t\tregulator-boot-on;\n-\t\tvin-supply = <&vccio_1v8>;\n-\t};\n-\n-\tvcc_sys: vcc-sys-regulator {\n-\t\tcompatible = \"regulator-fixed\";\n-\t\tregulator-name = \"vcc_sys\";\n-\t\tregulator-always-on;\n-\t\tregulator-boot-on;\n-\t\tregulator-min-microvolt = <5000000>;\n-\t\tregulator-max-microvolt = <5000000>;\n-\t\tvin-supply = <&dc_12v>;\n-\t};\n-\n-\tvccio_1v8: vccio-1v8-regulator {\n-\t\tcompatible = \"regulator-fixed\";\n-\t\tregulator-name = \"vccio_1v8\";\n-\t\tregulator-min-microvolt = <1800000>;\n-\t\tregulator-max-microvolt = <1800000>;\n-\t\tregulator-always-on;\n-\t\tvin-supply = <&vcc_sys>;\n-\t};\n-\n-\tvccio_3v3: vccio-3v3-regulator {\n-\t\tcompatible = \"regulator-fixed\";\n-\t\tregulator-name = \"vccio_3v3\";\n-\t\tregulator-min-microvolt = <3300000>;\n-\t\tregulator-max-microvolt = <3300000>;\n-\t\tregulator-always-on;\n-\t\tvin-supply = <&vcc_sys>;\n-\t};\n-\n-\tvdd_arm: vdd-arm-regulator {\n-\t\tcompatible = \"pwm-regulator\";\n-\t\tpwms = <&pwm1 0 25000 1>;\n-\t\tpwm-supply = <&vcc_sys>;\n-\t\tregulator-name = \"vdd_arm\";\n-\t\tregulator-min-microvolt = <950000>;\n-\t\tregulator-max-microvolt = <1400000>;\n-\t\tregulator-always-on;\n-\t\tregulator-boot-on;\n-\t};\n-\n-\tvdd_log: vdd-log-regulator {\n-\t\tcompatible = \"pwm-regulator\";\n-\t\tpwms = <&pwm2 0 25000 1>;\n-\t\tpwm-supply = <&vcc_sys>;\n-\t\tregulator-name = \"vdd_log\";\n-\t\tregulator-min-microvolt = <1000000>;\n-\t\tregulator-max-microvolt = <1300000>;\n-\t\tregulator-always-on;\n-\t\tregulator-boot-on;\n-\t};\n-\n-\tgpio_keys {\n-\t\tcompatible = \"gpio-keys\";\n-\t\tautorepeat;\n-\t\tpinctrl-names = \"default\";\n-\t\tpinctrl-0 = <&pwr_key>;\n-\n-\t\tpower_key: power-key {\n-\t\t\tlabel = \"GPIO Key Power\";\n-\t\t\tgpios = <&gpio3 23 GPIO_ACTIVE_LOW>;\n-\t\t\tlinux,code = <KEY_POWER>;\n-\t\t\tdebounce-interval = <100>;\n-\t\t\twakeup-source;\n-\t\t};\n-\t};\n-};\n-\n-&cpu0 {\n-\tcpu-supply = <&vdd_arm>;\n-};\n-\n-&cpu1 {\n-\tcpu-supply = <&vdd_arm>;\n-};\n-\n-&cpu2 {\n-\tcpu-supply = <&vdd_arm>;\n-};\n-\n-&cpu3 {\n-\tcpu-supply = <&vdd_arm>;\n-};\n-\n-&emmc {\n-\tcap-mmc-highspeed;\n-\tnon-removable;\n-\tstatus = \"okay\";\n-};\n-\n-&gmac {\n-\tassigned-clocks = <&cru SCLK_MAC_EXTCLK>, <&cru SCLK_MAC>;\n-\tassigned-clock-parents = <&ext_gmac>, <&cru SCLK_MAC_EXTCLK>;\n-\tclock_in_out = \"input\";\n-\tphy-supply = <&vcc_phy>;\n-\tphy-mode = \"rgmii\";\n-\tpinctrl-names = \"default\";\n-\tpinctrl-0 = <&rgmii_pins>;\n-\tsnps,reset-gpio = <&gpio2 RK_PD0 GPIO_ACTIVE_LOW>;\n-\tsnps,reset-active-low;\n-\tsnps,reset-delays-us = <0 10000 1000000>;\n-\ttx_delay = <0x30>;\n-\trx_delay = <0x10>;\n-\tstatus = \"okay\";\n-};\n-\n-&io_domains {\n-\tstatus = \"okay\";\n-\n-\tvccio1-supply = <&vccio_3v3>;\n-\tvccio2-supply = <&vccio_1v8>;\n-\tvccio4-supply = <&vccio_3v3>;\n-};\n-\n-&pinctrl {\n-\tkeys {\n-\t\tpwr_key: pwr-key {\n-\t\t\trockchip,pins = <3 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>;\n-\t\t};\n-\t};\n-\n-\tusb {\n-\t\thost_vbus_drv: host-vbus-drv {\n-\t\t\trockchip,pins = <3 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>;\n-\t\t};\n-\t};\n-};\n-\n-&pwm1 {\n-\tstatus = \"okay\";\n-};\n-\n-&pwm2 {\n-\tstatus = \"okay\";\n-};\n-\n-&tsadc {\n-\trockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */\n-\tstatus = \"okay\";\n-};\n-\n-&uart2 {\n-\tstatus = \"okay\";\n-};\n-\n-&u2phy0 {\n-\tstatus = \"okay\";\n-\n-\tu2phy0_otg: otg-port {\n-\t\tstatus = \"okay\";\n-\t};\n-\n-\tu2phy0_host: host-port {\n-\t\tphy-supply = <&vcc_host>;\n-\t\tstatus = \"okay\";\n-\t};\n-};\n-\n-&u2phy1 {\n-\tstatus = \"okay\";\n-\n-\tu2phy1_otg: otg-port {\n-\t\tphy-supply = <&vcc_host>;\n-\t\tstatus = \"okay\";\n-\t};\n-\n-\tu2phy1_host: host-port {\n-\t\tphy-supply = <&vcc_host>;\n-\t\tstatus = \"okay\";\n-\t};\n-};\n-\n-&usb_host0_ehci {\n-\tstatus = \"okay\";\n-};\n-\n-&usb_host0_ohci {\n-\tstatus = \"okay\";\n-};\n-\n-&usb_host1_ehci {\n-\tstatus = \"okay\";\n-};\n-\n-&usb_host1_ohci {\n-\tstatus = \"okay\";\n-};\n-\n-&usb_host2_ehci {\n-\tstatus = \"okay\";\n-};\n-\n-&usb_host2_ohci {\n-\tstatus = \"okay\";\n-};\n-\n-&usb_otg {\n-\tstatus = \"okay\";\n-};\ndiff --git a/arch/arm/dts/rk3229.dtsi b/arch/arm/dts/rk3229.dtsi\ndeleted file mode 100644\nindex c340fb30e775..000000000000\n--- a/arch/arm/dts/rk3229.dtsi\n+++ /dev/null\n@@ -1,52 +0,0 @@\n-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)\n-/*\n- * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd\n- */\n-\n-#include \"rk322x.dtsi\"\n-\n-/ {\n-\tcompatible = \"rockchip,rk3229\";\n-\n-\t/delete-node/ opp-table0;\n-\n-\tcpu0_opp_table: opp-table-0 {\n-\t\tcompatible = \"operating-points-v2\";\n-\t\topp-shared;\n-\n-\t\topp-408000000 {\n-\t\t\topp-hz = /bits/ 64 <408000000>;\n-\t\t\topp-microvolt = <950000>;\n-\t\t\tclock-latency-ns = <40000>;\n-\t\t\topp-suspend;\n-\t\t};\n-\t\topp-600000000 {\n-\t\t\topp-hz = /bits/ 64 <600000000>;\n-\t\t\topp-microvolt = <975000>;\n-\t\t};\n-\t\topp-816000000 {\n-\t\t\topp-hz = /bits/ 64 <816000000>;\n-\t\t\topp-microvolt = <1000000>;\n-\t\t};\n-\t\topp-1008000000 {\n-\t\t\topp-hz = /bits/ 64 <1008000000>;\n-\t\t\topp-microvolt = <1175000>;\n-\t\t};\n-\t\topp-1200000000 {\n-\t\t\topp-hz = /bits/ 64 <1200000000>;\n-\t\t\topp-microvolt = <1275000>;\n-\t\t};\n-\t\topp-1296000000 {\n-\t\t\topp-hz = /bits/ 64 <1296000000>;\n-\t\t\topp-microvolt = <1325000>;\n-\t\t};\n-\t\topp-1392000000 {\n-\t\t\topp-hz = /bits/ 64 <1392000000>;\n-\t\t\topp-microvolt = <1375000>;\n-\t\t};\n-\t\topp-1464000000 {\n-\t\t\topp-hz = /bits/ 64 <1464000000>;\n-\t\t\topp-microvolt = <1400000>;\n-\t\t};\n-\t};\n-};\ndiff --git a/arch/arm/dts/rk322x.dtsi b/arch/arm/dts/rk322x.dtsi\ndeleted file mode 100644\nindex 8eed9e3a92e9..000000000000\n--- a/arch/arm/dts/rk322x.dtsi\n+++ /dev/null\n@@ -1,1293 +0,0 @@\n-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)\n-\n-#include <dt-bindings/gpio/gpio.h>\n-#include <dt-bindings/interrupt-controller/irq.h>\n-#include <dt-bindings/interrupt-controller/arm-gic.h>\n-#include <dt-bindings/pinctrl/rockchip.h>\n-#include <dt-bindings/clock/rk3228-cru.h>\n-#include <dt-bindings/thermal/thermal.h>\n-#include <dt-bindings/power/rk3228-power.h>\n-\n-/ {\n-\t#address-cells = <1>;\n-\t#size-cells = <1>;\n-\n-\tinterrupt-parent = <&gic>;\n-\n-\taliases {\n-\t\tserial0 = &uart0;\n-\t\tserial1 = &uart1;\n-\t\tserial2 = &uart2;\n-\t\tspi0 = &spi0;\n-\t};\n-\n-\tcpus {\n-\t\t#address-cells = <1>;\n-\t\t#size-cells = <0>;\n-\n-\t\tcpu0: cpu@f00 {\n-\t\t\tdevice_type = \"cpu\";\n-\t\t\tcompatible = \"arm,cortex-a7\";\n-\t\t\treg = <0xf00>;\n-\t\t\tresets = <&cru SRST_CORE0>;\n-\t\t\toperating-points-v2 = <&cpu0_opp_table>;\n-\t\t\t#cooling-cells = <2>; /* min followed by max */\n-\t\t\tclock-latency = <40000>;\n-\t\t\tclocks = <&cru ARMCLK>;\n-\t\t\tenable-method = \"psci\";\n-\t\t};\n-\n-\t\tcpu1: cpu@f01 {\n-\t\t\tdevice_type = \"cpu\";\n-\t\t\tcompatible = \"arm,cortex-a7\";\n-\t\t\treg = <0xf01>;\n-\t\t\tresets = <&cru SRST_CORE1>;\n-\t\t\toperating-points-v2 = <&cpu0_opp_table>;\n-\t\t\t#cooling-cells = <2>; /* min followed by max */\n-\t\t\tenable-method = \"psci\";\n-\t\t};\n-\n-\t\tcpu2: cpu@f02 {\n-\t\t\tdevice_type = \"cpu\";\n-\t\t\tcompatible = \"arm,cortex-a7\";\n-\t\t\treg = <0xf02>;\n-\t\t\tresets = <&cru SRST_CORE2>;\n-\t\t\toperating-points-v2 = <&cpu0_opp_table>;\n-\t\t\t#cooling-cells = <2>; /* min followed by max */\n-\t\t\tenable-method = \"psci\";\n-\t\t};\n-\n-\t\tcpu3: cpu@f03 {\n-\t\t\tdevice_type = \"cpu\";\n-\t\t\tcompatible = \"arm,cortex-a7\";\n-\t\t\treg = <0xf03>;\n-\t\t\tresets = <&cru SRST_CORE3>;\n-\t\t\toperating-points-v2 = <&cpu0_opp_table>;\n-\t\t\t#cooling-cells = <2>; /* min followed by max */\n-\t\t\tenable-method = \"psci\";\n-\t\t};\n-\t};\n-\n-\tcpu0_opp_table: opp-table-0 {\n-\t\tcompatible = \"operating-points-v2\";\n-\t\topp-shared;\n-\n-\t\topp-408000000 {\n-\t\t\topp-hz = /bits/ 64 <408000000>;\n-\t\t\topp-microvolt = <950000>;\n-\t\t\tclock-latency-ns = <40000>;\n-\t\t\topp-suspend;\n-\t\t};\n-\t\topp-600000000 {\n-\t\t\topp-hz = /bits/ 64 <600000000>;\n-\t\t\topp-microvolt = <975000>;\n-\t\t};\n-\t\topp-816000000 {\n-\t\t\topp-hz = /bits/ 64 <816000000>;\n-\t\t\topp-microvolt = <1000000>;\n-\t\t};\n-\t\topp-1008000000 {\n-\t\t\topp-hz = /bits/ 64 <1008000000>;\n-\t\t\topp-microvolt = <1175000>;\n-\t\t};\n-\t\topp-1200000000 {\n-\t\t\topp-hz = /bits/ 64 <1200000000>;\n-\t\t\topp-microvolt = <1275000>;\n-\t\t};\n-\t};\n-\n-\tarm-pmu {\n-\t\tcompatible = \"arm,cortex-a7-pmu\";\n-\t\tinterrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,\n-\t\t\t <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,\n-\t\t\t <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,\n-\t\t\t <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;\n-\t\tinterrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;\n-\t};\n-\n-\tpsci {\n-\t\tcompatible = \"arm,psci-1.0\", \"arm,psci-0.2\";\n-\t\tmethod = \"smc\";\n-\t};\n-\n-\ttimer {\n-\t\tcompatible = \"arm,armv7-timer\";\n-\t\tarm,cpu-registers-not-fw-configured;\n-\t\tinterrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,\n-\t\t\t <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,\n-\t\t\t <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,\n-\t\t\t <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;\n-\t\tclock-frequency = <24000000>;\n-\t};\n-\n-\txin24m: oscillator {\n-\t\tcompatible = \"fixed-clock\";\n-\t\tclock-frequency = <24000000>;\n-\t\tclock-output-names = \"xin24m\";\n-\t\t#clock-cells = <0>;\n-\t};\n-\n-\tdisplay_subsystem: display-subsystem {\n-\t\tcompatible = \"rockchip,display-subsystem\";\n-\t\tports = <&vop_out>;\n-\t};\n-\n-\ti2s1: i2s1@100b0000 {\n-\t\tcompatible = \"rockchip,rk3228-i2s\", \"rockchip,rk3066-i2s\";\n-\t\treg = <0x100b0000 0x4000>;\n-\t\tinterrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;\n-\t\tclock-names = \"i2s_clk\", \"i2s_hclk\";\n-\t\tclocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>;\n-\t\tdmas = <&pdma 14>, <&pdma 15>;\n-\t\tdma-names = \"tx\", \"rx\";\n-\t\tpinctrl-names = \"default\";\n-\t\tpinctrl-0 = <&i2s1_bus>;\n-\t\tstatus = \"disabled\";\n-\t};\n-\n-\ti2s0: i2s0@100c0000 {\n-\t\tcompatible = \"rockchip,rk3228-i2s\", \"rockchip,rk3066-i2s\";\n-\t\treg = <0x100c0000 0x4000>;\n-\t\tinterrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;\n-\t\tclock-names = \"i2s_clk\", \"i2s_hclk\";\n-\t\tclocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>;\n-\t\tdmas = <&pdma 11>, <&pdma 12>;\n-\t\tdma-names = \"tx\", \"rx\";\n-\t\tstatus = \"disabled\";\n-\t};\n-\n-\tspdif: spdif@100d0000 {\n-\t\tcompatible = \"rockchip,rk3228-spdif\";\n-\t\treg = <0x100d0000 0x1000>;\n-\t\tinterrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;\n-\t\tclocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>;\n-\t\tclock-names = \"mclk\", \"hclk\";\n-\t\tdmas = <&pdma 10>;\n-\t\tdma-names = \"tx\";\n-\t\tpinctrl-names = \"default\";\n-\t\tpinctrl-0 = <&spdif_tx>;\n-\t\tstatus = \"disabled\";\n-\t};\n-\n-\ti2s2: i2s2@100e0000 {\n-\t\tcompatible = \"rockchip,rk3228-i2s\", \"rockchip,rk3066-i2s\";\n-\t\treg = <0x100e0000 0x4000>;\n-\t\tinterrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;\n-\t\tclock-names = \"i2s_clk\", \"i2s_hclk\";\n-\t\tclocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>;\n-\t\tdmas = <&pdma 0>, <&pdma 1>;\n-\t\tdma-names = \"tx\", \"rx\";\n-\t\tstatus = \"disabled\";\n-\t};\n-\n-\tgrf: syscon@11000000 {\n-\t\tcompatible = \"rockchip,rk3228-grf\", \"syscon\", \"simple-mfd\";\n-\t\treg = <0x11000000 0x1000>;\n-\t\t#address-cells = <1>;\n-\t\t#size-cells = <1>;\n-\n-\t\tio_domains: io-domains {\n-\t\t\tcompatible = \"rockchip,rk3228-io-voltage-domain\";\n-\t\t\tstatus = \"disabled\";\n-\t\t};\n-\n-\t\tpower: power-controller {\n-\t\t\tcompatible = \"rockchip,rk3228-power-controller\";\n-\t\t\t#power-domain-cells = <1>;\n-\t\t\t#address-cells = <1>;\n-\t\t\t#size-cells = <0>;\n-\n-\t\t\tpower-domain@RK3228_PD_VIO {\n-\t\t\t\treg = <RK3228_PD_VIO>;\n-\t\t\t\tclocks = <&cru ACLK_HDCP>,\n-\t\t\t\t\t <&cru SCLK_HDCP>,\n-\t\t\t\t\t <&cru ACLK_IEP>,\n-\t\t\t\t\t <&cru HCLK_IEP>,\n-\t\t\t\t\t <&cru ACLK_RGA>,\n-\t\t\t\t\t <&cru HCLK_RGA>,\n-\t\t\t\t\t <&cru SCLK_RGA>;\n-\t\t\t\tpm_qos = <&qos_hdcp>,\n-\t\t\t\t\t <&qos_iep>,\n-\t\t\t\t\t <&qos_rga_r>,\n-\t\t\t\t\t <&qos_rga_w>;\n-\t\t\t\t#power-domain-cells = <0>;\n-\t\t\t};\n-\n-\t\t\tpower-domain@RK3228_PD_VOP {\n-\t\t\t\treg = <RK3228_PD_VOP>;\n-\t\t\t\tclocks =<&cru ACLK_VOP>,\n-\t\t\t\t\t<&cru DCLK_VOP>,\n-\t\t\t\t\t<&cru HCLK_VOP>;\n-\t\t\t\tpm_qos = <&qos_vop>;\n-\t\t\t\t#power-domain-cells = <0>;\n-\t\t\t};\n-\n-\t\t\tpower-domain@RK3228_PD_VPU {\n-\t\t\t\treg = <RK3228_PD_VPU>;\n-\t\t\t\tclocks = <&cru ACLK_VPU>,\n-\t\t\t\t\t <&cru HCLK_VPU>;\n-\t\t\t\tpm_qos = <&qos_vpu>;\n-\t\t\t\t#power-domain-cells = <0>;\n-\t\t\t};\n-\n-\t\t\tpower-domain@RK3228_PD_RKVDEC {\n-\t\t\t\treg = <RK3228_PD_RKVDEC>;\n-\t\t\t\tclocks = <&cru ACLK_RKVDEC>,\n-\t\t\t\t\t <&cru HCLK_RKVDEC>,\n-\t\t\t\t\t <&cru SCLK_VDEC_CABAC>,\n-\t\t\t\t\t <&cru SCLK_VDEC_CORE>;\n-\t\t\t\tpm_qos = <&qos_rkvdec_r>,\n-\t\t\t\t\t <&qos_rkvdec_w>;\n-\t\t\t\t#power-domain-cells = <0>;\n-\t\t\t};\n-\n-\t\t\tpower-domain@RK3228_PD_GPU {\n-\t\t\t\treg = <RK3228_PD_GPU>;\n-\t\t\t\tclocks = <&cru ACLK_GPU>;\n-\t\t\t\tpm_qos = <&qos_gpu>;\n-\t\t\t\t#power-domain-cells = <0>;\n-\t\t\t};\n-\t\t};\n-\n-\t\tu2phy0: usb2phy@760 {\n-\t\t\tcompatible = \"rockchip,rk3228-usb2phy\";\n-\t\t\treg = <0x0760 0x0c>;\n-\t\t\tclocks = <&cru SCLK_OTGPHY0>;\n-\t\t\tclock-names = \"phyclk\";\n-\t\t\tclock-output-names = \"usb480m_phy0\";\n-\t\t\t#clock-cells = <0>;\n-\t\t\tstatus = \"disabled\";\n-\n-\t\t\tu2phy0_otg: otg-port {\n-\t\t\t\tinterrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,\n-\t\t\t\t\t <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,\n-\t\t\t\t\t <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;\n-\t\t\t\tinterrupt-names = \"otg-bvalid\", \"otg-id\",\n-\t\t\t\t\t\t \"linestate\";\n-\t\t\t\t#phy-cells = <0>;\n-\t\t\t\tstatus = \"disabled\";\n-\t\t\t};\n-\n-\t\t\tu2phy0_host: host-port {\n-\t\t\t\tinterrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;\n-\t\t\t\tinterrupt-names = \"linestate\";\n-\t\t\t\t#phy-cells = <0>;\n-\t\t\t\tstatus = \"disabled\";\n-\t\t\t};\n-\t\t};\n-\n-\t\tu2phy1: usb2phy@800 {\n-\t\t\tcompatible = \"rockchip,rk3228-usb2phy\";\n-\t\t\treg = <0x0800 0x0c>;\n-\t\t\tclocks = <&cru SCLK_OTGPHY1>;\n-\t\t\tclock-names = \"phyclk\";\n-\t\t\tclock-output-names = \"usb480m_phy1\";\n-\t\t\t#clock-cells = <0>;\n-\t\t\tstatus = \"disabled\";\n-\n-\t\t\tu2phy1_otg: otg-port {\n-\t\t\t\tinterrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;\n-\t\t\t\tinterrupt-names = \"linestate\";\n-\t\t\t\t#phy-cells = <0>;\n-\t\t\t\tstatus = \"disabled\";\n-\t\t\t};\n-\n-\t\t\tu2phy1_host: host-port {\n-\t\t\t\tinterrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;\n-\t\t\t\tinterrupt-names = \"linestate\";\n-\t\t\t\t#phy-cells = <0>;\n-\t\t\t\tstatus = \"disabled\";\n-\t\t\t};\n-\t\t};\n-\t};\n-\n-\tuart0: serial@11010000 {\n-\t\tcompatible = \"snps,dw-apb-uart\";\n-\t\treg = <0x11010000 0x100>;\n-\t\tinterrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;\n-\t\tclock-frequency = <24000000>;\n-\t\tclocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;\n-\t\tclock-names = \"baudclk\", \"apb_pclk\";\n-\t\tpinctrl-names = \"default\";\n-\t\tpinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;\n-\t\treg-shift = <2>;\n-\t\treg-io-width = <4>;\n-\t\tstatus = \"disabled\";\n-\t};\n-\n-\tuart1: serial@11020000 {\n-\t\tcompatible = \"snps,dw-apb-uart\";\n-\t\treg = <0x11020000 0x100>;\n-\t\tinterrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;\n-\t\tclock-frequency = <24000000>;\n-\t\tclocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;\n-\t\tclock-names = \"baudclk\", \"apb_pclk\";\n-\t\tpinctrl-names = \"default\";\n-\t\tpinctrl-0 = <&uart1_xfer>;\n-\t\treg-shift = <2>;\n-\t\treg-io-width = <4>;\n-\t\tstatus = \"disabled\";\n-\t};\n-\n-\tuart2: serial@11030000 {\n-\t\tcompatible = \"snps,dw-apb-uart\";\n-\t\treg = <0x11030000 0x100>;\n-\t\tinterrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;\n-\t\tclock-frequency = <24000000>;\n-\t\tclocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;\n-\t\tclock-names = \"baudclk\", \"apb_pclk\";\n-\t\tpinctrl-names = \"default\";\n-\t\tpinctrl-0 = <&uart2_xfer>;\n-\t\treg-shift = <2>;\n-\t\treg-io-width = <4>;\n-\t\tstatus = \"disabled\";\n-\t};\n-\n-\tefuse: efuse@11040000 {\n-\t\tcompatible = \"rockchip,rk3228-efuse\";\n-\t\treg = <0x11040000 0x20>;\n-\t\tclocks = <&cru PCLK_EFUSE_256>;\n-\t\tclock-names = \"pclk_efuse\";\n-\t\t#address-cells = <1>;\n-\t\t#size-cells = <1>;\n-\n-\t\t/* Data cells */\n-\t\tefuse_id: id@7 {\n-\t\t\treg = <0x7 0x10>;\n-\t\t};\n-\t\tcpu_leakage: cpu_leakage@17 {\n-\t\t\treg = <0x17 0x1>;\n-\t\t};\n-\t};\n-\n-\ti2c0: i2c@11050000 {\n-\t\tcompatible = \"rockchip,rk3228-i2c\";\n-\t\treg = <0x11050000 0x1000>;\n-\t\tinterrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;\n-\t\t#address-cells = <1>;\n-\t\t#size-cells = <0>;\n-\t\tclock-names = \"i2c\";\n-\t\tclocks = <&cru PCLK_I2C0>;\n-\t\tpinctrl-names = \"default\";\n-\t\tpinctrl-0 = <&i2c0_xfer>;\n-\t\tstatus = \"disabled\";\n-\t};\n-\n-\ti2c1: i2c@11060000 {\n-\t\tcompatible = \"rockchip,rk3228-i2c\";\n-\t\treg = <0x11060000 0x1000>;\n-\t\tinterrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;\n-\t\t#address-cells = <1>;\n-\t\t#size-cells = <0>;\n-\t\tclock-names = \"i2c\";\n-\t\tclocks = <&cru PCLK_I2C1>;\n-\t\tpinctrl-names = \"default\";\n-\t\tpinctrl-0 = <&i2c1_xfer>;\n-\t\tstatus = \"disabled\";\n-\t};\n-\n-\ti2c2: i2c@11070000 {\n-\t\tcompatible = \"rockchip,rk3228-i2c\";\n-\t\treg = <0x11070000 0x1000>;\n-\t\tinterrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;\n-\t\t#address-cells = <1>;\n-\t\t#size-cells = <0>;\n-\t\tclock-names = \"i2c\";\n-\t\tclocks = <&cru PCLK_I2C2>;\n-\t\tpinctrl-names = \"default\";\n-\t\tpinctrl-0 = <&i2c2_xfer>;\n-\t\tstatus = \"disabled\";\n-\t};\n-\n-\ti2c3: i2c@11080000 {\n-\t\tcompatible = \"rockchip,rk3228-i2c\";\n-\t\treg = <0x11080000 0x1000>;\n-\t\tinterrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;\n-\t\t#address-cells = <1>;\n-\t\t#size-cells = <0>;\n-\t\tclock-names = \"i2c\";\n-\t\tclocks = <&cru PCLK_I2C3>;\n-\t\tpinctrl-names = \"default\";\n-\t\tpinctrl-0 = <&i2c3_xfer>;\n-\t\tstatus = \"disabled\";\n-\t};\n-\n-\tspi0: spi@11090000 {\n-\t\tcompatible = \"rockchip,rk3228-spi\";\n-\t\treg = <0x11090000 0x1000>;\n-\t\tinterrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;\n-\t\t#address-cells = <1>;\n-\t\t#size-cells = <0>;\n-\t\tclocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;\n-\t\tclock-names = \"spiclk\", \"apb_pclk\";\n-\t\tpinctrl-names = \"default\";\n-\t\tpinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0 &spi0_cs1>;\n-\t\tstatus = \"disabled\";\n-\t};\n-\n-\twdt: watchdog@110a0000 {\n-\t\tcompatible = \"rockchip,rk3228-wdt\", \"snps,dw-wdt\";\n-\t\treg = <0x110a0000 0x100>;\n-\t\tinterrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;\n-\t\tclocks = <&cru PCLK_CPU>;\n-\t\tstatus = \"disabled\";\n-\t};\n-\n-\tpwm0: pwm@110b0000 {\n-\t\tcompatible = \"rockchip,rk3288-pwm\";\n-\t\treg = <0x110b0000 0x10>;\n-\t\t#pwm-cells = <3>;\n-\t\tclocks = <&cru PCLK_PWM>;\n-\t\tpinctrl-names = \"default\";\n-\t\tpinctrl-0 = <&pwm0_pin>;\n-\t\tstatus = \"disabled\";\n-\t};\n-\n-\tpwm1: pwm@110b0010 {\n-\t\tcompatible = \"rockchip,rk3288-pwm\";\n-\t\treg = <0x110b0010 0x10>;\n-\t\t#pwm-cells = <3>;\n-\t\tclocks = <&cru PCLK_PWM>;\n-\t\tpinctrl-names = \"default\";\n-\t\tpinctrl-0 = <&pwm1_pin>;\n-\t\tstatus = \"disabled\";\n-\t};\n-\n-\tpwm2: pwm@110b0020 {\n-\t\tcompatible = \"rockchip,rk3288-pwm\";\n-\t\treg = <0x110b0020 0x10>;\n-\t\t#pwm-cells = <3>;\n-\t\tclocks = <&cru PCLK_PWM>;\n-\t\tpinctrl-names = \"default\";\n-\t\tpinctrl-0 = <&pwm2_pin>;\n-\t\tstatus = \"disabled\";\n-\t};\n-\n-\tpwm3: pwm@110b0030 {\n-\t\tcompatible = \"rockchip,rk3288-pwm\";\n-\t\treg = <0x110b0030 0x10>;\n-\t\t#pwm-cells = <2>;\n-\t\tclocks = <&cru PCLK_PWM>;\n-\t\tpinctrl-names = \"default\";\n-\t\tpinctrl-0 = <&pwm3_pin>;\n-\t\tstatus = \"disabled\";\n-\t};\n-\n-\ttimer: timer@110c0000 {\n-\t\tcompatible = \"rockchip,rk3228-timer\", \"rockchip,rk3288-timer\";\n-\t\treg = <0x110c0000 0x20>;\n-\t\tinterrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;\n-\t\tclocks = <&cru PCLK_TIMER>, <&xin24m>;\n-\t\tclock-names = \"pclk\", \"timer\";\n-\t};\n-\n-\tcru: clock-controller@110e0000 {\n-\t\tcompatible = \"rockchip,rk3228-cru\";\n-\t\treg = <0x110e0000 0x1000>;\n-\t\trockchip,grf = <&grf>;\n-\t\t#clock-cells = <1>;\n-\t\t#reset-cells = <1>;\n-\t\tassigned-clocks =\n-\t\t\t<&cru PLL_GPLL>, <&cru ARMCLK>,\n-\t\t\t<&cru PLL_CPLL>, <&cru ACLK_PERI>,\n-\t\t\t<&cru HCLK_PERI>, <&cru PCLK_PERI>,\n-\t\t\t<&cru ACLK_CPU>, <&cru HCLK_CPU>,\n-\t\t\t<&cru PCLK_CPU>;\n-\t\tassigned-clock-rates =\n-\t\t\t<594000000>, <816000000>,\n-\t\t\t<500000000>, <150000000>,\n-\t\t\t<150000000>, <75000000>,\n-\t\t\t<150000000>, <150000000>,\n-\t\t\t<75000000>;\n-\t};\n-\n-\tpdma: pdma@110f0000 {\n-\t\tcompatible = \"arm,pl330\", \"arm,primecell\";\n-\t\treg = <0x110f0000 0x4000>;\n-\t\tinterrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,\n-\t\t\t <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;\n-\t\t#dma-cells = <1>;\n-\t\tarm,pl330-periph-burst;\n-\t\tclocks = <&cru ACLK_DMAC>;\n-\t\tclock-names = \"apb_pclk\";\n-\t};\n-\n-\tthermal-zones {\n-\t\tcpu_thermal: cpu-thermal {\n-\t\t\tpolling-delay-passive = <100>; /* milliseconds */\n-\t\t\tpolling-delay = <5000>; /* milliseconds */\n-\n-\t\t\tthermal-sensors = <&tsadc 0>;\n-\n-\t\t\ttrips {\n-\t\t\t\tcpu_alert0: cpu_alert0 {\n-\t\t\t\t\ttemperature = <70000>; /* millicelsius */\n-\t\t\t\t\thysteresis = <2000>; /* millicelsius */\n-\t\t\t\t\ttype = \"passive\";\n-\t\t\t\t};\n-\t\t\t\tcpu_alert1: cpu_alert1 {\n-\t\t\t\t\ttemperature = <75000>; /* millicelsius */\n-\t\t\t\t\thysteresis = <2000>; /* millicelsius */\n-\t\t\t\t\ttype = \"passive\";\n-\t\t\t\t};\n-\t\t\t\tcpu_crit: cpu_crit {\n-\t\t\t\t\ttemperature = <90000>; /* millicelsius */\n-\t\t\t\t\thysteresis = <2000>; /* millicelsius */\n-\t\t\t\t\ttype = \"critical\";\n-\t\t\t\t};\n-\t\t\t};\n-\n-\t\t\tcooling-maps {\n-\t\t\t\tmap0 {\n-\t\t\t\t\ttrip = <&cpu_alert0>;\n-\t\t\t\t\tcooling-device =\n-\t\t\t\t\t\t<&cpu0 THERMAL_NO_LIMIT 6>,\n-\t\t\t\t\t\t<&cpu1 THERMAL_NO_LIMIT 6>,\n-\t\t\t\t\t\t<&cpu2 THERMAL_NO_LIMIT 6>,\n-\t\t\t\t\t\t<&cpu3 THERMAL_NO_LIMIT 6>;\n-\t\t\t\t};\n-\t\t\t\tmap1 {\n-\t\t\t\t\ttrip = <&cpu_alert1>;\n-\t\t\t\t\tcooling-device =\n-\t\t\t\t\t\t<&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,\n-\t\t\t\t\t\t<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,\n-\t\t\t\t\t\t<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,\n-\t\t\t\t\t\t<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;\n-\t\t\t\t};\n-\t\t\t};\n-\t\t};\n-\t};\n-\n-\ttsadc: tsadc@11150000 {\n-\t\tcompatible = \"rockchip,rk3228-tsadc\";\n-\t\treg = <0x11150000 0x100>;\n-\t\tinterrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;\n-\t\tclocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;\n-\t\tclock-names = \"tsadc\", \"apb_pclk\";\n-\t\tassigned-clocks = <&cru SCLK_TSADC>;\n-\t\tassigned-clock-rates = <32768>;\n-\t\tresets = <&cru SRST_TSADC>;\n-\t\treset-names = \"tsadc-apb\";\n-\t\tpinctrl-names = \"init\", \"default\", \"sleep\";\n-\t\tpinctrl-0 = <&otp_pin>;\n-\t\tpinctrl-1 = <&otp_out>;\n-\t\tpinctrl-2 = <&otp_pin>;\n-\t\t#thermal-sensor-cells = <1>;\n-\t\trockchip,hw-tshut-temp = <95000>;\n-\t\tstatus = \"disabled\";\n-\t};\n-\n-\thdmi_phy: hdmi-phy@12030000 {\n-\t\tcompatible = \"rockchip,rk3228-hdmi-phy\";\n-\t\treg = <0x12030000 0x10000>;\n-\t\tclocks = <&cru PCLK_HDMI_PHY>, <&xin24m>, <&cru DCLK_HDMI_PHY>;\n-\t\tclock-names = \"sysclk\", \"refoclk\", \"refpclk\";\n-\t\t#clock-cells = <0>;\n-\t\tclock-output-names = \"hdmiphy_phy\";\n-\t\t#phy-cells = <0>;\n-\t\tstatus = \"disabled\";\n-\t};\n-\n-\tgpu: gpu@20000000 {\n-\t\tcompatible = \"rockchip,rk3228-mali\", \"arm,mali-400\";\n-\t\treg = <0x20000000 0x10000>;\n-\t\tinterrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,\n-\t\t\t <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,\n-\t\t\t <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,\n-\t\t\t <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,\n-\t\t\t <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,\n-\t\t\t <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;\n-\t\tinterrupt-names = \"gp\",\n-\t\t\t\t \"gpmmu\",\n-\t\t\t\t \"pp0\",\n-\t\t\t\t \"ppmmu0\",\n-\t\t\t\t \"pp1\",\n-\t\t\t\t \"ppmmu1\";\n-\t\tclocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>;\n-\t\tclock-names = \"bus\", \"core\";\n-\t\tpower-domains = <&power RK3228_PD_GPU>;\n-\t\tresets = <&cru SRST_GPU_A>;\n-\t\tstatus = \"disabled\";\n-\t};\n-\n-\tvpu: video-codec@20020000 {\n-\t\tcompatible = \"rockchip,rk3228-vpu\", \"rockchip,rk3399-vpu\";\n-\t\treg = <0x20020000 0x800>;\n-\t\tinterrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,\n-\t\t\t <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;\n-\t\tinterrupt-names = \"vepu\", \"vdpu\";\n-\t\tclocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;\n-\t\tclock-names = \"aclk\", \"hclk\";\n-\t\tiommus = <&vpu_mmu>;\n-\t\tpower-domains = <&power RK3228_PD_VPU>;\n-\t};\n-\n-\tvpu_mmu: iommu@20020800 {\n-\t\tcompatible = \"rockchip,iommu\";\n-\t\treg = <0x20020800 0x100>;\n-\t\tinterrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;\n-\t\tclocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;\n-\t\tclock-names = \"aclk\", \"iface\";\n-\t\tpower-domains = <&power RK3228_PD_VPU>;\n-\t\t#iommu-cells = <0>;\n-\t};\n-\n-\tvdec: video-codec@20030000 {\n-\t\tcompatible = \"rockchip,rk3228-vdec\", \"rockchip,rk3399-vdec\";\n-\t\treg = <0x20030000 0x480>;\n-\t\tinterrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;\n-\t\tclocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>,\n-\t\t\t <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>;\n-\t\tclock-names = \"axi\", \"ahb\", \"cabac\", \"core\";\n-\t\tassigned-clocks = <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>;\n-\t\tassigned-clock-rates = <300000000>, <300000000>;\n-\t\tiommus = <&vdec_mmu>;\n-\t\tpower-domains = <&power RK3228_PD_RKVDEC>;\n-\t};\n-\n-\tvdec_mmu: iommu@20030480 {\n-\t\tcompatible = \"rockchip,iommu\";\n-\t\treg = <0x20030480 0x40>, <0x200304c0 0x40>;\n-\t\tinterrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;\n-\t\tclocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>;\n-\t\tclock-names = \"aclk\", \"iface\";\n-\t\tpower-domains = <&power RK3228_PD_RKVDEC>;\n-\t\t#iommu-cells = <0>;\n-\t};\n-\n-\tvop: vop@20050000 {\n-\t\tcompatible = \"rockchip,rk3228-vop\";\n-\t\treg = <0x20050000 0x1ffc>;\n-\t\tinterrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;\n-\t\tclocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, <&cru HCLK_VOP>;\n-\t\tclock-names = \"aclk_vop\", \"dclk_vop\", \"hclk_vop\";\n-\t\tresets = <&cru SRST_VOP_A>, <&cru SRST_VOP_H>, <&cru SRST_VOP_D>;\n-\t\treset-names = \"axi\", \"ahb\", \"dclk\";\n-\t\tiommus = <&vop_mmu>;\n-\t\tpower-domains = <&power RK3228_PD_VOP>;\n-\t\tstatus = \"disabled\";\n-\n-\t\tvop_out: port {\n-\t\t\t#address-cells = <1>;\n-\t\t\t#size-cells = <0>;\n-\n-\t\t\tvop_out_hdmi: endpoint@0 {\n-\t\t\t\treg = <0>;\n-\t\t\t\tremote-endpoint = <&hdmi_in_vop>;\n-\t\t\t};\n-\t\t};\n-\t};\n-\n-\tvop_mmu: iommu@20053f00 {\n-\t\tcompatible = \"rockchip,iommu\";\n-\t\treg = <0x20053f00 0x100>;\n-\t\tinterrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;\n-\t\tclocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;\n-\t\tclock-names = \"aclk\", \"iface\";\n-\t\tpower-domains = <&power RK3228_PD_VOP>;\n-\t\t#iommu-cells = <0>;\n-\t\tstatus = \"disabled\";\n-\t};\n-\n-\trga: rga@20060000 {\n-\t\tcompatible = \"rockchip,rk3228-rga\", \"rockchip,rk3288-rga\";\n-\t\treg = <0x20060000 0x1000>;\n-\t\tinterrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;\n-\t\tclocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>;\n-\t\tclock-names = \"aclk\", \"hclk\", \"sclk\";\n-\t\tpower-domains = <&power RK3228_PD_VIO>;\n-\t\tresets = <&cru SRST_RGA>, <&cru SRST_RGA_A>, <&cru SRST_RGA_H>;\n-\t\treset-names = \"core\", \"axi\", \"ahb\";\n-\t};\n-\n-\tiep_mmu: iommu@20070800 {\n-\t\tcompatible = \"rockchip,iommu\";\n-\t\treg = <0x20070800 0x100>;\n-\t\tinterrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;\n-\t\tclocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;\n-\t\tclock-names = \"aclk\", \"iface\";\n-\t\tpower-domains = <&power RK3228_PD_VIO>;\n-\t\t#iommu-cells = <0>;\n-\t\tstatus = \"disabled\";\n-\t};\n-\n-\thdmi: hdmi@200a0000 {\n-\t\tcompatible = \"rockchip,rk3228-dw-hdmi\";\n-\t\treg = <0x200a0000 0x20000>;\n-\t\treg-io-width = <4>;\n-\t\tinterrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;\n-\t\tassigned-clocks = <&cru SCLK_HDMI_PHY>;\n-\t\tassigned-clock-parents = <&hdmi_phy>;\n-\t\tclocks = <&cru SCLK_HDMI_HDCP>, <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_CEC>;\n-\t\tclock-names = \"isfr\", \"iahb\", \"cec\";\n-\t\tpinctrl-names = \"default\";\n-\t\tpinctrl-0 = <&hdmii2c_xfer &hdmi_hpd &hdmi_cec>;\n-\t\tresets = <&cru SRST_HDMI_P>;\n-\t\treset-names = \"hdmi\";\n-\t\tphys = <&hdmi_phy>;\n-\t\tphy-names = \"hdmi\";\n-\t\trockchip,grf = <&grf>;\n-\t\tstatus = \"disabled\";\n-\n-\t\tports {\n-\t\t\thdmi_in: port {\n-\t\t\t\t#address-cells = <1>;\n-\t\t\t\t#size-cells = <0>;\n-\t\t\t\thdmi_in_vop: endpoint@0 {\n-\t\t\t\t\treg = <0>;\n-\t\t\t\t\tremote-endpoint = <&vop_out_hdmi>;\n-\t\t\t\t};\n-\t\t\t};\n-\t\t};\n-\t};\n-\n-\tsdmmc: mmc@30000000 {\n-\t\tcompatible = \"rockchip,rk3228-dw-mshc\", \"rockchip,rk3288-dw-mshc\";\n-\t\treg = <0x30000000 0x4000>;\n-\t\tinterrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;\n-\t\tclocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,\n-\t\t\t <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;\n-\t\tclock-names = \"biu\", \"ciu\", \"ciu-drive\", \"ciu-sample\";\n-\t\tfifo-depth = <0x100>;\n-\t\tpinctrl-names = \"default\";\n-\t\tpinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>;\n-\t\tstatus = \"disabled\";\n-\t};\n-\n-\tsdio: mmc@30010000 {\n-\t\tcompatible = \"rockchip,rk3228-dw-mshc\", \"rockchip,rk3288-dw-mshc\";\n-\t\treg = <0x30010000 0x4000>;\n-\t\tinterrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;\n-\t\tclocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,\n-\t\t\t <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;\n-\t\tclock-names = \"biu\", \"ciu\", \"ciu-drive\", \"ciu-sample\";\n-\t\tfifo-depth = <0x100>;\n-\t\tpinctrl-names = \"default\";\n-\t\tpinctrl-0 = <&sdio_clk &sdio_cmd &sdio_bus4>;\n-\t\tstatus = \"disabled\";\n-\t};\n-\n-\temmc: mmc@30020000 {\n-\t\tcompatible = \"rockchip,rk3228-dw-mshc\", \"rockchip,rk3288-dw-mshc\";\n-\t\treg = <0x30020000 0x4000>;\n-\t\tinterrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;\n-\t\tclock-frequency = <37500000>;\n-\t\tmax-frequency = <37500000>;\n-\t\tclocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,\n-\t\t\t <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;\n-\t\tclock-names = \"biu\", \"ciu\", \"ciu-drive\", \"ciu-sample\";\n-\t\tbus-width = <8>;\n-\t\trockchip,default-sample-phase = <158>;\n-\t\tfifo-depth = <0x100>;\n-\t\tpinctrl-names = \"default\";\n-\t\tpinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;\n-\t\tresets = <&cru SRST_EMMC>;\n-\t\treset-names = \"reset\";\n-\t\tstatus = \"disabled\";\n-\t};\n-\n-\tusb_otg: usb@30040000 {\n-\t\tcompatible = \"rockchip,rk3228-usb\", \"rockchip,rk3066-usb\",\n-\t\t\t \"snps,dwc2\";\n-\t\treg = <0x30040000 0x40000>;\n-\t\tinterrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;\n-\t\tclocks = <&cru HCLK_OTG>;\n-\t\tclock-names = \"otg\";\n-\t\tdr_mode = \"otg\";\n-\t\tg-np-tx-fifo-size = <16>;\n-\t\tg-rx-fifo-size = <280>;\n-\t\tg-tx-fifo-size = <256 128 128 64 32 16>;\n-\t\tphys = <&u2phy0_otg>;\n-\t\tphy-names = \"usb2-phy\";\n-\t\tstatus = \"disabled\";\n-\t};\n-\n-\tusb_host0_ehci: usb@30080000 {\n-\t\tcompatible = \"generic-ehci\";\n-\t\treg = <0x30080000 0x20000>;\n-\t\tinterrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;\n-\t\tclocks = <&cru HCLK_HOST0>, <&u2phy0>;\n-\t\tphys = <&u2phy0_host>;\n-\t\tphy-names = \"usb\";\n-\t\tstatus = \"disabled\";\n-\t};\n-\n-\tusb_host0_ohci: usb@300a0000 {\n-\t\tcompatible = \"generic-ohci\";\n-\t\treg = <0x300a0000 0x20000>;\n-\t\tinterrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;\n-\t\tclocks = <&cru HCLK_HOST0>, <&u2phy0>;\n-\t\tphys = <&u2phy0_host>;\n-\t\tphy-names = \"usb\";\n-\t\tstatus = \"disabled\";\n-\t};\n-\n-\tusb_host1_ehci: usb@300c0000 {\n-\t\tcompatible = \"generic-ehci\";\n-\t\treg = <0x300c0000 0x20000>;\n-\t\tinterrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;\n-\t\tclocks = <&cru HCLK_HOST1>, <&u2phy1>;\n-\t\tphys = <&u2phy1_otg>;\n-\t\tphy-names = \"usb\";\n-\t\tstatus = \"disabled\";\n-\t};\n-\n-\tusb_host1_ohci: usb@300e0000 {\n-\t\tcompatible = \"generic-ohci\";\n-\t\treg = <0x300e0000 0x20000>;\n-\t\tinterrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;\n-\t\tclocks = <&cru HCLK_HOST1>, <&u2phy1>;\n-\t\tphys = <&u2phy1_otg>;\n-\t\tphy-names = \"usb\";\n-\t\tstatus = \"disabled\";\n-\t};\n-\n-\tusb_host2_ehci: usb@30100000 {\n-\t\tcompatible = \"generic-ehci\";\n-\t\treg = <0x30100000 0x20000>;\n-\t\tinterrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;\n-\t\tclocks = <&cru HCLK_HOST2>, <&u2phy1>;\n-\t\tphys = <&u2phy1_host>;\n-\t\tphy-names = \"usb\";\n-\t\tstatus = \"disabled\";\n-\t};\n-\n-\tusb_host2_ohci: usb@30120000 {\n-\t\tcompatible = \"generic-ohci\";\n-\t\treg = <0x30120000 0x20000>;\n-\t\tinterrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;\n-\t\tclocks = <&cru HCLK_HOST2>, <&u2phy1>;\n-\t\tphys = <&u2phy1_host>;\n-\t\tphy-names = \"usb\";\n-\t\tstatus = \"disabled\";\n-\t};\n-\n-\tgmac: ethernet@30200000 {\n-\t\tcompatible = \"rockchip,rk3228-gmac\";\n-\t\treg = <0x30200000 0x10000>;\n-\t\tinterrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;\n-\t\tinterrupt-names = \"macirq\";\n-\t\tclocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,\n-\t\t\t<&cru SCLK_MAC_TX>, <&cru SCLK_MAC_REF>,\n-\t\t\t<&cru SCLK_MAC_REFOUT>, <&cru ACLK_GMAC>,\n-\t\t\t<&cru PCLK_GMAC>;\n-\t\tclock-names = \"stmmaceth\", \"mac_clk_rx\",\n-\t\t\t\"mac_clk_tx\", \"clk_mac_ref\",\n-\t\t\t\"clk_mac_refout\", \"aclk_mac\",\n-\t\t\t\"pclk_mac\";\n-\t\tresets = <&cru SRST_GMAC>;\n-\t\treset-names = \"stmmaceth\";\n-\t\trockchip,grf = <&grf>;\n-\t\tstatus = \"disabled\";\n-\t};\n-\n-\tqos_iep: qos@31030080 {\n-\t\tcompatible = \"rockchip,rk3228-qos\", \"syscon\";\n-\t\treg = <0x31030080 0x20>;\n-\t};\n-\n-\tqos_rga_w: qos@31030100 {\n-\t\tcompatible = \"rockchip,rk3228-qos\", \"syscon\";\n-\t\treg = <0x31030100 0x20>;\n-\t};\n-\n-\tqos_hdcp: qos@31030180 {\n-\t\tcompatible = \"rockchip,rk3228-qos\", \"syscon\";\n-\t\treg = <0x31030180 0x20>;\n-\t};\n-\n-\tqos_rga_r: qos@31030200 {\n-\t\tcompatible = \"rockchip,rk3228-qos\", \"syscon\";\n-\t\treg = <0x31030200 0x20>;\n-\t};\n-\n-\tqos_vpu: qos@31040000 {\n-\t\tcompatible = \"rockchip,rk3228-qos\", \"syscon\";\n-\t\treg = <0x31040000 0x20>;\n-\t};\n-\n-\tqos_gpu: qos@31050000 {\n-\t\tcompatible = \"rockchip,rk3228-qos\", \"syscon\";\n-\t\treg = <0x31050000 0x20>;\n-\t};\n-\n-\tqos_vop: qos@31060000 {\n-\t\tcompatible = \"rockchip,rk3228-qos\", \"syscon\";\n-\t\treg = <0x31060000 0x20>;\n-\t};\n-\n-\tqos_rkvdec_r: qos@31070000 {\n-\t\tcompatible = \"rockchip,rk3228-qos\", \"syscon\";\n-\t\treg = <0x31070000 0x20>;\n-\t};\n-\n-\tqos_rkvdec_w: qos@31070080 {\n-\t\tcompatible = \"rockchip,rk3228-qos\", \"syscon\";\n-\t\treg = <0x31070080 0x20>;\n-\t};\n-\n-\tgic: interrupt-controller@32010000 {\n-\t\tcompatible = \"arm,gic-400\";\n-\t\tinterrupt-controller;\n-\t\t#interrupt-cells = <3>;\n-\t\t#address-cells = <0>;\n-\n-\t\treg = <0x32011000 0x1000>,\n-\t\t <0x32012000 0x2000>,\n-\t\t <0x32014000 0x2000>,\n-\t\t <0x32016000 0x2000>;\n-\t\tinterrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;\n-\t};\n-\n-\tpinctrl: pinctrl {\n-\t\tcompatible = \"rockchip,rk3228-pinctrl\";\n-\t\trockchip,grf = <&grf>;\n-\t\t#address-cells = <1>;\n-\t\t#size-cells = <1>;\n-\t\tranges;\n-\n-\t\tgpio0: gpio@11110000 {\n-\t\t\tcompatible = \"rockchip,gpio-bank\";\n-\t\t\treg = <0x11110000 0x100>;\n-\t\t\tinterrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;\n-\t\t\tclocks = <&cru PCLK_GPIO0>;\n-\n-\t\t\tgpio-controller;\n-\t\t\t#gpio-cells = <2>;\n-\n-\t\t\tinterrupt-controller;\n-\t\t\t#interrupt-cells = <2>;\n-\t\t};\n-\n-\t\tgpio1: gpio@11120000 {\n-\t\t\tcompatible = \"rockchip,gpio-bank\";\n-\t\t\treg = <0x11120000 0x100>;\n-\t\t\tinterrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;\n-\t\t\tclocks = <&cru PCLK_GPIO1>;\n-\n-\t\t\tgpio-controller;\n-\t\t\t#gpio-cells = <2>;\n-\n-\t\t\tinterrupt-controller;\n-\t\t\t#interrupt-cells = <2>;\n-\t\t};\n-\n-\t\tgpio2: gpio@11130000 {\n-\t\t\tcompatible = \"rockchip,gpio-bank\";\n-\t\t\treg = <0x11130000 0x100>;\n-\t\t\tinterrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;\n-\t\t\tclocks = <&cru PCLK_GPIO2>;\n-\n-\t\t\tgpio-controller;\n-\t\t\t#gpio-cells = <2>;\n-\n-\t\t\tinterrupt-controller;\n-\t\t\t#interrupt-cells = <2>;\n-\t\t};\n-\n-\t\tgpio3: gpio@11140000 {\n-\t\t\tcompatible = \"rockchip,gpio-bank\";\n-\t\t\treg = <0x11140000 0x100>;\n-\t\t\tinterrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;\n-\t\t\tclocks = <&cru PCLK_GPIO3>;\n-\n-\t\t\tgpio-controller;\n-\t\t\t#gpio-cells = <2>;\n-\n-\t\t\tinterrupt-controller;\n-\t\t\t#interrupt-cells = <2>;\n-\t\t};\n-\n-\t\tpcfg_pull_up: pcfg-pull-up {\n-\t\t\tbias-pull-up;\n-\t\t};\n-\n-\t\tpcfg_pull_down: pcfg-pull-down {\n-\t\t\tbias-pull-down;\n-\t\t};\n-\n-\t\tpcfg_pull_none: pcfg-pull-none {\n-\t\t\tbias-disable;\n-\t\t};\n-\n-\t\tpcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma {\n-\t\t\tdrive-strength = <12>;\n-\t\t};\n-\n-\t\tsdmmc {\n-\t\t\tsdmmc_clk: sdmmc-clk {\n-\t\t\t\trockchip,pins = <1 RK_PC0 1 &pcfg_pull_none_drv_12ma>;\n-\t\t\t};\n-\n-\t\t\tsdmmc_cmd: sdmmc-cmd {\n-\t\t\t\trockchip,pins = <1 RK_PB7 1 &pcfg_pull_none_drv_12ma>;\n-\t\t\t};\n-\n-\t\t\tsdmmc_bus4: sdmmc-bus4 {\n-\t\t\t\trockchip,pins = <1 RK_PC2 1 &pcfg_pull_none_drv_12ma>,\n-\t\t\t\t\t\t<1 RK_PC3 1 &pcfg_pull_none_drv_12ma>,\n-\t\t\t\t\t\t<1 RK_PC4 1 &pcfg_pull_none_drv_12ma>,\n-\t\t\t\t\t\t<1 RK_PC5 1 &pcfg_pull_none_drv_12ma>;\n-\t\t\t};\n-\t\t};\n-\n-\t\tsdio {\n-\t\t\tsdio_clk: sdio-clk {\n-\t\t\t\trockchip,pins = <3 RK_PA0 1 &pcfg_pull_none_drv_12ma>;\n-\t\t\t};\n-\n-\t\t\tsdio_cmd: sdio-cmd {\n-\t\t\t\trockchip,pins = <3 RK_PA1 1 &pcfg_pull_none_drv_12ma>;\n-\t\t\t};\n-\n-\t\t\tsdio_bus4: sdio-bus4 {\n-\t\t\t\trockchip,pins = <3 RK_PA2 1 &pcfg_pull_none_drv_12ma>,\n-\t\t\t\t\t\t<3 RK_PA3 1 &pcfg_pull_none_drv_12ma>,\n-\t\t\t\t\t\t<3 RK_PA4 1 &pcfg_pull_none_drv_12ma>,\n-\t\t\t\t\t\t<3 RK_PA5 1 &pcfg_pull_none_drv_12ma>;\n-\t\t\t};\n-\t\t};\n-\n-\t\temmc {\n-\t\t\temmc_clk: emmc-clk {\n-\t\t\t\trockchip,pins = <2 RK_PA7 2 &pcfg_pull_none>;\n-\t\t\t};\n-\n-\t\t\temmc_cmd: emmc-cmd {\n-\t\t\t\trockchip,pins = <1 RK_PC6 2 &pcfg_pull_none>;\n-\t\t\t};\n-\n-\t\t\temmc_bus8: emmc-bus8 {\n-\t\t\t\trockchip,pins = <1 RK_PD0 2 &pcfg_pull_none>,\n-\t\t\t\t\t\t<1 RK_PD1 2 &pcfg_pull_none>,\n-\t\t\t\t\t\t<1 RK_PD2 2 &pcfg_pull_none>,\n-\t\t\t\t\t\t<1 RK_PD3 2 &pcfg_pull_none>,\n-\t\t\t\t\t\t<1 RK_PD4 2 &pcfg_pull_none>,\n-\t\t\t\t\t\t<1 RK_PD5 2 &pcfg_pull_none>,\n-\t\t\t\t\t\t<1 RK_PD6 2 &pcfg_pull_none>,\n-\t\t\t\t\t\t<1 RK_PD7 2 &pcfg_pull_none>;\n-\t\t\t};\n-\t\t};\n-\n-\t\tgmac {\n-\t\t\trgmii_pins: rgmii-pins {\n-\t\t\t\trockchip,pins = <2 RK_PB6 1 &pcfg_pull_none>,\n-\t\t\t\t\t\t<2 RK_PB4 1 &pcfg_pull_none>,\n-\t\t\t\t\t\t<2 RK_PD1 1 &pcfg_pull_none>,\n-\t\t\t\t\t\t<2 RK_PC3 1 &pcfg_pull_none_drv_12ma>,\n-\t\t\t\t\t\t<2 RK_PC2 1 &pcfg_pull_none_drv_12ma>,\n-\t\t\t\t\t\t<2 RK_PC6 1 &pcfg_pull_none_drv_12ma>,\n-\t\t\t\t\t\t<2 RK_PC7 1 &pcfg_pull_none_drv_12ma>,\n-\t\t\t\t\t\t<2 RK_PB1 1 &pcfg_pull_none_drv_12ma>,\n-\t\t\t\t\t\t<2 RK_PB5 1 &pcfg_pull_none_drv_12ma>,\n-\t\t\t\t\t\t<2 RK_PC1 1 &pcfg_pull_none>,\n-\t\t\t\t\t\t<2 RK_PC0 1 &pcfg_pull_none>,\n-\t\t\t\t\t\t<2 RK_PC5 2 &pcfg_pull_none>,\n-\t\t\t\t\t\t<2 RK_PC4 2 &pcfg_pull_none>,\n-\t\t\t\t\t\t<2 RK_PB3 1 &pcfg_pull_none>,\n-\t\t\t\t\t\t<2 RK_PB0 1 &pcfg_pull_none>;\n-\t\t\t};\n-\n-\t\t\trmii_pins: rmii-pins {\n-\t\t\t\trockchip,pins = <2 RK_PB6 1 &pcfg_pull_none>,\n-\t\t\t\t\t\t<2 RK_PB4 1 &pcfg_pull_none>,\n-\t\t\t\t\t\t<2 RK_PD1 1 &pcfg_pull_none>,\n-\t\t\t\t\t\t<2 RK_PC3 1 &pcfg_pull_none_drv_12ma>,\n-\t\t\t\t\t\t<2 RK_PC2 1 &pcfg_pull_none_drv_12ma>,\n-\t\t\t\t\t\t<2 RK_PB5 1 &pcfg_pull_none_drv_12ma>,\n-\t\t\t\t\t\t<2 RK_PC1 1 &pcfg_pull_none>,\n-\t\t\t\t\t\t<2 RK_PC0 1 &pcfg_pull_none>,\n-\t\t\t\t\t\t<2 RK_PB0 1 &pcfg_pull_none>,\n-\t\t\t\t\t\t<2 RK_PB7 1 &pcfg_pull_none>;\n-\t\t\t};\n-\n-\t\t\tphy_pins: phy-pins {\n-\t\t\t\trockchip,pins = <2 RK_PB6 2 &pcfg_pull_none>,\n-\t\t\t\t\t\t<2 RK_PB0 2 &pcfg_pull_none>;\n-\t\t\t};\n-\t\t};\n-\n-\t\thdmi {\n-\t\t\thdmi_hpd: hdmi-hpd {\n-\t\t\t\trockchip,pins = <0 RK_PB7 1 &pcfg_pull_down>;\n-\t\t\t};\n-\n-\t\t\thdmii2c_xfer: hdmii2c-xfer {\n-\t\t\t\trockchip,pins = <0 RK_PA6 2 &pcfg_pull_none>,\n-\t\t\t\t\t\t<0 RK_PA7 2 &pcfg_pull_none>;\n-\t\t\t};\n-\n-\t\t\thdmi_cec: hdmi-cec {\n-\t\t\t\trockchip,pins = <0 RK_PC4 1 &pcfg_pull_none>;\n-\t\t\t};\n-\t\t};\n-\n-\t\ti2c0 {\n-\t\t\ti2c0_xfer: i2c0-xfer {\n-\t\t\t\trockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>,\n-\t\t\t\t\t\t<0 RK_PA1 1 &pcfg_pull_none>;\n-\t\t\t};\n-\t\t};\n-\n-\t\ti2c1 {\n-\t\t\ti2c1_xfer: i2c1-xfer {\n-\t\t\t\trockchip,pins = <0 RK_PA2 1 &pcfg_pull_none>,\n-\t\t\t\t\t\t<0 RK_PA3 1 &pcfg_pull_none>;\n-\t\t\t};\n-\t\t};\n-\n-\t\ti2c2 {\n-\t\t\ti2c2_xfer: i2c2-xfer {\n-\t\t\t\trockchip,pins = <2 RK_PC4 1 &pcfg_pull_none>,\n-\t\t\t\t\t\t<2 RK_PC5 1 &pcfg_pull_none>;\n-\t\t\t};\n-\t\t};\n-\n-\t\ti2c3 {\n-\t\t\ti2c3_xfer: i2c3-xfer {\n-\t\t\t\trockchip,pins = <0 RK_PA6 1 &pcfg_pull_none>,\n-\t\t\t\t\t\t<0 RK_PA7 1 &pcfg_pull_none>;\n-\t\t\t};\n-\t\t};\n-\n-\t\tspi0 {\n-\t\t\tspi0_clk: spi0-clk {\n-\t\t\t\trockchip,pins = <0 RK_PB1 2 &pcfg_pull_up>;\n-\t\t\t};\n-\t\t\tspi0_cs0: spi0-cs0 {\n-\t\t\t\trockchip,pins = <0 RK_PB6 2 &pcfg_pull_up>;\n-\t\t\t};\n-\t\t\tspi0_tx: spi0-tx {\n-\t\t\t\trockchip,pins = <0 RK_PB3 2 &pcfg_pull_up>;\n-\t\t\t};\n-\t\t\tspi0_rx: spi0-rx {\n-\t\t\t\trockchip,pins = <0 RK_PB5 2 &pcfg_pull_up>;\n-\t\t\t};\n-\t\t\tspi0_cs1: spi0-cs1 {\n-\t\t\t\trockchip,pins = <1 RK_PB4 1 &pcfg_pull_up>;\n-\t\t\t};\n-\t\t};\n-\n-\t\tspi1 {\n-\t\t\tspi1_clk: spi1-clk {\n-\t\t\t\trockchip,pins = <0 RK_PC7 2 &pcfg_pull_up>;\n-\t\t\t};\n-\t\t\tspi1_cs0: spi1-cs0 {\n-\t\t\t\trockchip,pins = <2 RK_PA2 2 &pcfg_pull_up>;\n-\t\t\t};\n-\t\t\tspi1_rx: spi1-rx {\n-\t\t\t\trockchip,pins = <2 RK_PA0 2 &pcfg_pull_up>;\n-\t\t\t};\n-\t\t\tspi1_tx: spi1-tx {\n-\t\t\t\trockchip,pins = <2 RK_PA1 2 &pcfg_pull_up>;\n-\t\t\t};\n-\t\t\tspi1_cs1: spi1-cs1 {\n-\t\t\t\trockchip,pins = <2 RK_PA3 2 &pcfg_pull_up>;\n-\t\t\t};\n-\t\t};\n-\n-\t\ti2s1 {\n-\t\t\ti2s1_bus: i2s1-bus {\n-\t\t\t\trockchip,pins = <0 RK_PB0 1 &pcfg_pull_none>,\n-\t\t\t\t\t\t<0 RK_PB1 1 &pcfg_pull_none>,\n-\t\t\t\t\t\t<0 RK_PB3 1 &pcfg_pull_none>,\n-\t\t\t\t\t\t<0 RK_PB4 1 &pcfg_pull_none>,\n-\t\t\t\t\t\t<0 RK_PB5 1 &pcfg_pull_none>,\n-\t\t\t\t\t\t<0 RK_PB6 1 &pcfg_pull_none>,\n-\t\t\t\t\t\t<1 RK_PA2 2 &pcfg_pull_none>,\n-\t\t\t\t\t\t<1 RK_PA4 2 &pcfg_pull_none>,\n-\t\t\t\t\t\t<1 RK_PA5 2 &pcfg_pull_none>;\n-\t\t\t};\n-\t\t};\n-\n-\t\tpwm0 {\n-\t\t\tpwm0_pin: pwm0-pin {\n-\t\t\t\trockchip,pins = <3 RK_PC5 1 &pcfg_pull_none>;\n-\t\t\t};\n-\t\t};\n-\n-\t\tpwm1 {\n-\t\t\tpwm1_pin: pwm1-pin {\n-\t\t\t\trockchip,pins = <0 RK_PD6 2 &pcfg_pull_none>;\n-\t\t\t};\n-\t\t};\n-\n-\t\tpwm2 {\n-\t\t\tpwm2_pin: pwm2-pin {\n-\t\t\t\trockchip,pins = <1 RK_PB4 2 &pcfg_pull_none>;\n-\t\t\t};\n-\t\t};\n-\n-\t\tpwm3 {\n-\t\t\tpwm3_pin: pwm3-pin {\n-\t\t\t\trockchip,pins = <1 RK_PB3 2 &pcfg_pull_none>;\n-\t\t\t};\n-\t\t};\n-\n-\t\tspdif {\n-\t\t\tspdif_tx: spdif-tx {\n-\t\t\t\trockchip,pins = <3 RK_PD7 2 &pcfg_pull_none>;\n-\t\t\t};\n-\t\t};\n-\n-\t\ttsadc {\n-\t\t\totp_pin: otp-pin {\n-\t\t\t\trockchip,pins = <0 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;\n-\t\t\t};\n-\n-\t\t\totp_out: otp-out {\n-\t\t\t\trockchip,pins = <0 RK_PD0 2 &pcfg_pull_none>;\n-\t\t\t};\n-\t\t};\n-\n-\t\tuart0 {\n-\t\t\tuart0_xfer: uart0-xfer {\n-\t\t\t\trockchip,pins = <2 RK_PD2 1 &pcfg_pull_none>,\n-\t\t\t\t\t\t<2 RK_PD3 1 &pcfg_pull_none>;\n-\t\t\t};\n-\n-\t\t\tuart0_cts: uart0-cts {\n-\t\t\t\trockchip,pins = <2 RK_PD5 1 &pcfg_pull_none>;\n-\t\t\t};\n-\n-\t\t\tuart0_rts: uart0-rts {\n-\t\t\t\trockchip,pins = <0 RK_PC1 1 &pcfg_pull_none>;\n-\t\t\t};\n-\t\t};\n-\n-\t\tuart1 {\n-\t\t\tuart1_xfer: uart1-xfer {\n-\t\t\t\trockchip,pins = <1 RK_PB1 1 &pcfg_pull_none>,\n-\t\t\t\t\t\t<1 RK_PB2 1 &pcfg_pull_none>;\n-\t\t\t};\n-\n-\t\t\tuart1_cts: uart1-cts {\n-\t\t\t\trockchip,pins = <1 RK_PB0 1 &pcfg_pull_none>;\n-\t\t\t};\n-\n-\t\t\tuart1_rts: uart1-rts {\n-\t\t\t\trockchip,pins = <1 RK_PB3 1 &pcfg_pull_none>;\n-\t\t\t};\n-\t\t};\n-\n-\t\tuart2 {\n-\t\t\tuart2_xfer: uart2-xfer {\n-\t\t\t\trockchip,pins = <1 RK_PC2 2 &pcfg_pull_up>,\n-\t\t\t\t\t\t<1 RK_PC3 2 &pcfg_pull_none>;\n-\t\t\t};\n-\n-\t\t\tuart21_xfer: uart21-xfer {\n-\t\t\t\trockchip,pins = <1 RK_PB2 2 &pcfg_pull_up>,\n-\t\t\t\t\t\t<1 RK_PB1 2 &pcfg_pull_none>;\n-\t\t\t};\n-\n-\t\t\tuart2_cts: uart2-cts {\n-\t\t\t\trockchip,pins = <0 RK_PD1 1 &pcfg_pull_none>;\n-\t\t\t};\n-\n-\t\t\tuart2_rts: uart2-rts {\n-\t\t\t\trockchip,pins = <0 RK_PD0 1 &pcfg_pull_none>;\n-\t\t\t};\n-\t\t};\n-\t};\n-};\ndiff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig\nindex 02737c62df03..d92fcae2bb56 100644\n--- a/arch/arm/mach-rockchip/Kconfig\n+++ b/arch/arm/mach-rockchip/Kconfig\n@@ -109,6 +109,7 @@ config ROCKCHIP_RK322X\n \tselect TPL_OF_LIBFDT\n \tselect TPL_HAVE_INIT_STACK if TPL\n \tselect SPL_DRIVERS_MISC\n+\timply OF_UPSTREAM\n \timply ROCKCHIP_COMMON_BOARD\n \timply SPL_SERIAL\n \timply SPL_ROCKCHIP_COMMON_BOARD\ndiff --git a/board/rockchip/evb_rk3229/MAINTAINERS b/board/rockchip/evb_rk3229/MAINTAINERS\nindex 4de97dbb0a49..7758ee9b9306 100644\n--- a/board/rockchip/evb_rk3229/MAINTAINERS\n+++ b/board/rockchip/evb_rk3229/MAINTAINERS\n@@ -1,7 +1,6 @@\n EVB-RK3229\n M: Kever Yang <kever.yang@rock-chips.com>\n S: Maintained\n-F:\tarch/arm/dts/rk3229-evb.dts\n F:\tarch/arm/dts/rk3229-evb-u-boot.dtsi\n F: board/rockchip/evb_rk3229\n F: include/configs/evb_rk3229.h\ndiff --git a/configs/evb-rk3229_defconfig b/configs/evb-rk3229_defconfig\nindex 116c04c914d7..46a682faecb0 100644\n--- a/configs/evb-rk3229_defconfig\n+++ b/configs/evb-rk3229_defconfig\n@@ -9,7 +9,7 @@ CONFIG_NR_DRAM_BANKS=2\n CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y\n CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x61100000\n CONFIG_ENV_OFFSET=0x3F8000\n-CONFIG_DEFAULT_DEVICE_TREE=\"rk3229-evb\"\n+CONFIG_DEFAULT_DEVICE_TREE=\"rockchip/rk3229-evb\"\n CONFIG_ROCKCHIP_RK322X=y\n CONFIG_TARGET_EVB_RK3229=y\n CONFIG_SPL_STACK_R_ADDR=0x60600000\n@@ -24,7 +24,7 @@ CONFIG_FIT=y\n CONFIG_FIT_VERBOSE=y\n CONFIG_SPL_LOAD_FIT=y\n CONFIG_USE_PREBOOT=y\n-CONFIG_DEFAULT_FDT_FILE=\"rk3229-evb.dtb\"\n+CONFIG_DEFAULT_FDT_FILE=\"rockchip/rk3229-evb.dtb\"\n # CONFIG_DISPLAY_CPUINFO is not set\n CONFIG_DISPLAY_BOARDINFO_LATE=y\n CONFIG_SPL_MAX_SIZE=0x100000\ndiff --git a/include/dt-bindings/clock/rk3228-cru.h b/include/dt-bindings/clock/rk3228-cru.h\ndeleted file mode 100644\nindex de550ea56eeb..000000000000\n--- a/include/dt-bindings/clock/rk3228-cru.h\n+++ /dev/null\n@@ -1,287 +0,0 @@\n-/* SPDX-License-Identifier: GPL-2.0-or-later */\n-/*\n- * Copyright (c) 2015 Rockchip Electronics Co. Ltd.\n- * Author: Jeffy Chen <jeffy.chen@rock-chips.com>\n- */\n-\n-#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3228_H\n-#define _DT_BINDINGS_CLK_ROCKCHIP_RK3228_H\n-\n-/* core clocks */\n-#define PLL_APLL\t\t1\n-#define PLL_DPLL\t\t2\n-#define PLL_CPLL\t\t3\n-#define PLL_GPLL\t\t4\n-#define ARMCLK\t\t\t5\n-\n-/* sclk gates (special clocks) */\n-#define SCLK_SPI0\t\t65\n-#define SCLK_NANDC\t\t67\n-#define SCLK_SDMMC\t\t68\n-#define SCLK_SDIO\t\t69\n-#define SCLK_EMMC\t\t71\n-#define SCLK_TSADC\t\t72\n-#define SCLK_UART0\t\t77\n-#define SCLK_UART1\t\t78\n-#define SCLK_UART2\t\t79\n-#define SCLK_I2S0\t\t80\n-#define SCLK_I2S1\t\t81\n-#define SCLK_I2S2\t\t82\n-#define SCLK_SPDIF\t\t83\n-#define SCLK_TIMER0\t\t85\n-#define SCLK_TIMER1\t\t86\n-#define SCLK_TIMER2\t\t87\n-#define SCLK_TIMER3\t\t88\n-#define SCLK_TIMER4\t\t89\n-#define SCLK_TIMER5\t\t90\n-#define SCLK_I2S_OUT\t\t113\n-#define SCLK_SDMMC_DRV\t\t114\n-#define SCLK_SDIO_DRV\t\t115\n-#define SCLK_EMMC_DRV\t\t117\n-#define SCLK_SDMMC_SAMPLE\t118\n-#define SCLK_SDIO_SAMPLE\t119\n-#define SCLK_SDIO_SRC\t\t120\n-#define SCLK_EMMC_SAMPLE\t121\n-#define SCLK_VOP\t\t122\n-#define SCLK_HDMI_HDCP\t\t123\n-#define SCLK_MAC_SRC\t\t124\n-#define SCLK_MAC_EXTCLK\t\t125\n-#define SCLK_MAC\t\t126\n-#define SCLK_MAC_REFOUT\t\t127\n-#define SCLK_MAC_REF\t\t128\n-#define SCLK_MAC_RX\t\t129\n-#define SCLK_MAC_TX\t\t130\n-#define SCLK_MAC_PHY\t\t131\n-#define SCLK_MAC_OUT\t\t132\n-#define SCLK_VDEC_CABAC\t\t133\n-#define SCLK_VDEC_CORE\t\t134\n-#define SCLK_RGA\t\t135\n-#define SCLK_HDCP\t\t136\n-#define SCLK_HDMI_CEC\t\t137\n-#define SCLK_CRYPTO\t\t138\n-#define SCLK_TSP\t\t139\n-#define SCLK_HSADC\t\t140\n-#define SCLK_WIFI\t\t141\n-#define SCLK_OTGPHY0\t\t142\n-#define SCLK_OTGPHY1\t\t143\n-#define SCLK_HDMI_PHY\t\t144\n-\n-/* dclk gates */\n-#define DCLK_VOP\t\t190\n-#define DCLK_HDMI_PHY\t\t191\n-\n-/* aclk gates */\n-#define ACLK_DMAC\t\t194\n-#define ACLK_CPU\t\t195\n-#define ACLK_VPU_PRE\t\t196\n-#define ACLK_RKVDEC_PRE\t\t197\n-#define ACLK_RGA_PRE\t\t198\n-#define ACLK_IEP_PRE\t\t199\n-#define ACLK_HDCP_PRE\t\t200\n-#define ACLK_VOP_PRE\t\t201\n-#define ACLK_VPU\t\t202\n-#define ACLK_RKVDEC\t\t203\n-#define ACLK_IEP\t\t204\n-#define ACLK_RGA\t\t205\n-#define ACLK_HDCP\t\t206\n-#define ACLK_PERI\t\t210\n-#define ACLK_VOP\t\t211\n-#define ACLK_GMAC\t\t212\n-#define ACLK_GPU\t\t213\n-\n-/* pclk gates */\n-#define PCLK_GPIO0\t\t320\n-#define PCLK_GPIO1\t\t321\n-#define PCLK_GPIO2\t\t322\n-#define PCLK_GPIO3\t\t323\n-#define PCLK_VIO_H2P\t\t324\n-#define PCLK_HDCP\t\t325\n-#define PCLK_EFUSE_1024\t\t326\n-#define PCLK_EFUSE_256\t\t327\n-#define PCLK_GRF\t\t329\n-#define PCLK_I2C0\t\t332\n-#define PCLK_I2C1\t\t333\n-#define PCLK_I2C2\t\t334\n-#define PCLK_I2C3\t\t335\n-#define PCLK_SPI0\t\t338\n-#define PCLK_UART0\t\t341\n-#define PCLK_UART1\t\t342\n-#define PCLK_UART2\t\t343\n-#define PCLK_TSADC\t\t344\n-#define PCLK_PWM\t\t350\n-#define PCLK_TIMER\t\t353\n-#define PCLK_CPU\t\t354\n-#define PCLK_PERI\t\t363\n-#define PCLK_HDMI_CTRL\t\t364\n-#define PCLK_HDMI_PHY\t\t365\n-#define PCLK_GMAC\t\t367\n-\n-/* hclk gates */\n-#define HCLK_I2S0_8CH\t\t442\n-#define HCLK_I2S1_8CH\t\t443\n-#define HCLK_I2S2_2CH\t\t444\n-#define HCLK_SPDIF_8CH\t\t445\n-#define HCLK_VOP\t\t452\n-#define HCLK_NANDC\t\t453\n-#define HCLK_SDMMC\t\t456\n-#define HCLK_SDIO\t\t457\n-#define HCLK_EMMC\t\t459\n-#define HCLK_CPU\t\t460\n-#define HCLK_VPU_PRE\t\t461\n-#define HCLK_RKVDEC_PRE\t\t462\n-#define HCLK_VIO_PRE\t\t463\n-#define HCLK_VPU\t\t464\n-#define HCLK_RKVDEC\t\t465\n-#define HCLK_VIO\t\t466\n-#define HCLK_RGA\t\t467\n-#define HCLK_IEP\t\t468\n-#define HCLK_VIO_H2P\t\t469\n-#define HCLK_HDCP_MMU\t\t470\n-#define HCLK_HOST0\t\t471\n-#define HCLK_HOST1\t\t472\n-#define HCLK_HOST2\t\t473\n-#define HCLK_OTG\t\t474\n-#define HCLK_TSP\t\t475\n-#define HCLK_M_CRYPTO\t\t476\n-#define HCLK_S_CRYPTO\t\t477\n-#define HCLK_PERI\t\t478\n-\n-#define CLK_NR_CLKS\t\t(HCLK_PERI + 1)\n-\n-/* soft-reset indices */\n-#define SRST_CORE0_PO\t\t0\n-#define SRST_CORE1_PO\t\t1\n-#define SRST_CORE2_PO\t\t2\n-#define SRST_CORE3_PO\t\t3\n-#define SRST_CORE0\t\t4\n-#define SRST_CORE1\t\t5\n-#define SRST_CORE2\t\t6\n-#define SRST_CORE3\t\t7\n-#define SRST_CORE0_DBG\t\t8\n-#define SRST_CORE1_DBG\t\t9\n-#define SRST_CORE2_DBG\t\t10\n-#define SRST_CORE3_DBG\t\t11\n-#define SRST_TOPDBG\t\t12\n-#define SRST_ACLK_CORE\t\t13\n-#define SRST_NOC\t\t14\n-#define SRST_L2C\t\t15\n-\n-#define SRST_CPUSYS_H\t\t18\n-#define SRST_BUSSYS_H\t\t19\n-#define SRST_SPDIF\t\t20\n-#define SRST_INTMEM\t\t21\n-#define SRST_ROM\t\t22\n-#define SRST_OTG_ADP\t\t23\n-#define SRST_I2S0\t\t24\n-#define SRST_I2S1\t\t25\n-#define SRST_I2S2\t\t26\n-#define SRST_ACODEC_P\t\t27\n-#define SRST_DFIMON\t\t28\n-#define SRST_MSCH\t\t29\n-#define SRST_EFUSE1024\t\t30\n-#define SRST_EFUSE256\t\t31\n-\n-#define SRST_GPIO0\t\t32\n-#define SRST_GPIO1\t\t33\n-#define SRST_GPIO2\t\t34\n-#define SRST_GPIO3\t\t35\n-#define SRST_PERIPH_NOC_A\t36\n-#define SRST_PERIPH_NOC_BUS_H\t37\n-#define SRST_PERIPH_NOC_P\t38\n-#define SRST_UART0\t\t39\n-#define SRST_UART1\t\t40\n-#define SRST_UART2\t\t41\n-#define SRST_PHYNOC\t\t42\n-#define SRST_I2C0\t\t43\n-#define SRST_I2C1\t\t44\n-#define SRST_I2C2\t\t45\n-#define SRST_I2C3\t\t46\n-\n-#define SRST_PWM\t\t48\n-#define SRST_A53_GIC\t\t49\n-#define SRST_DAP\t\t51\n-#define SRST_DAP_NOC\t\t52\n-#define SRST_CRYPTO\t\t53\n-#define SRST_SGRF\t\t54\n-#define SRST_GRF\t\t55\n-#define SRST_GMAC\t\t56\n-#define SRST_PERIPH_NOC_H\t58\n-#define SRST_MACPHY\t\t63\n-\n-#define SRST_DMA\t\t64\n-#define SRST_NANDC\t\t68\n-#define SRST_USBOTG\t\t69\n-#define SRST_OTGC\t\t70\n-#define SRST_USBHOST0\t\t71\n-#define SRST_HOST_CTRL0\t\t72\n-#define SRST_USBHOST1\t\t73\n-#define SRST_HOST_CTRL1\t\t74\n-#define SRST_USBHOST2\t\t75\n-#define SRST_HOST_CTRL2\t\t76\n-#define SRST_USBPOR0\t\t77\n-#define SRST_USBPOR1\t\t78\n-#define SRST_DDRMSCH\t\t79\n-\n-#define SRST_SMART_CARD\t\t80\n-#define SRST_SDMMC\t\t81\n-#define SRST_SDIO\t\t82\n-#define SRST_EMMC\t\t83\n-#define SRST_SPI\t\t84\n-#define SRST_TSP_H\t\t85\n-#define SRST_TSP\t\t86\n-#define SRST_TSADC\t\t87\n-#define SRST_DDRPHY\t\t88\n-#define SRST_DDRPHY_P\t\t89\n-#define SRST_DDRCTRL\t\t90\n-#define SRST_DDRCTRL_P\t\t91\n-#define SRST_HOST0_ECHI\t\t92\n-#define SRST_HOST1_ECHI\t\t93\n-#define SRST_HOST2_ECHI\t\t94\n-#define SRST_VOP_NOC_A\t\t95\n-\n-#define SRST_HDMI_P\t\t96\n-#define SRST_VIO_ARBI_H\t\t97\n-#define SRST_IEP_NOC_A\t\t98\n-#define SRST_VIO_NOC_H\t\t99\n-#define SRST_VOP_A\t\t100\n-#define SRST_VOP_H\t\t101\n-#define SRST_VOP_D\t\t102\n-#define SRST_UTMI0\t\t103\n-#define SRST_UTMI1\t\t104\n-#define SRST_UTMI2\t\t105\n-#define SRST_UTMI3\t\t106\n-#define SRST_RGA\t\t107\n-#define SRST_RGA_NOC_A\t\t108\n-#define SRST_RGA_A\t\t109\n-#define SRST_RGA_H\t\t110\n-#define SRST_HDCP_A\t\t111\n-\n-#define SRST_VPU_A\t\t112\n-#define SRST_VPU_H\t\t113\n-#define SRST_VPU_NOC_A\t\t116\n-#define SRST_VPU_NOC_H\t\t117\n-#define SRST_RKVDEC_A\t\t118\n-#define SRST_RKVDEC_NOC_A\t119\n-#define SRST_RKVDEC_H\t\t120\n-#define SRST_RKVDEC_NOC_H\t121\n-#define SRST_RKVDEC_CORE\t122\n-#define SRST_RKVDEC_CABAC\t123\n-#define SRST_IEP_A\t\t124\n-#define SRST_IEP_H\t\t125\n-#define SRST_GPU_A\t\t126\n-#define SRST_GPU_NOC_A\t\t127\n-\n-#define SRST_CORE_DBG\t\t128\n-#define SRST_DBG_P\t\t129\n-#define SRST_TIMER0\t\t130\n-#define SRST_TIMER1\t\t131\n-#define SRST_TIMER2\t\t132\n-#define SRST_TIMER3\t\t133\n-#define SRST_TIMER4\t\t134\n-#define SRST_TIMER5\t\t135\n-#define SRST_VIO_H2P\t\t136\n-#define SRST_HDMIPHY\t\t139\n-#define SRST_VDAC\t\t140\n-#define SRST_TIMER_6CH_P\t141\n-\n-#endif\n", "prefixes": [ "v2", "2/5" ] }