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GET /api/1.2/patches/2234524/?format=api
{ "id": 2234524, "url": "http://patchwork.ozlabs.org/api/1.2/patches/2234524/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/0dd99123-acbe-48cb-b90f-ee2679d7465e@gmail.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/1.2/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<0dd99123-acbe-48cb-b90f-ee2679d7465e@gmail.com>", "list_archive_url": null, "date": "2026-05-07T18:37:50", "name": "[v2,1/5] rockchip: Switch rk3128 boards to upstream devicetree", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "a507600f5364f4b13990e3cf9d769049e998412e", "submitter": { "id": 75645, "url": "http://patchwork.ozlabs.org/api/1.2/people/75645/?format=api", "name": "Johan Jonker", "email": "jbx6244@gmail.com" }, "delegate": { "id": 93623, "url": "http://patchwork.ozlabs.org/api/1.2/users/93623/?format=api", "username": "kevery", "first_name": "Kever", "last_name": "Yang", "email": "ykai007@gmail.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/0dd99123-acbe-48cb-b90f-ee2679d7465e@gmail.com/mbox/", "series": [ { "id": 503246, "url": "http://patchwork.ozlabs.org/api/1.2/series/503246/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=503246", "date": "2026-05-07T18:34:48", "name": "rockchip: Switch remaining boards to upstream devicetree", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/503246/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2234524/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2234524/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": 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"text/plain; charset=UTF-8", "Content-Transfer-Encoding": "7bit", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.39", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<https://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>", "X-Virus-Scanned": "clamav-milter 0.103.8 at phobos.denx.de", "X-Virus-Status": "Clean" }, "content": "Switch rk3128 boards to upstream devicetree.\n\nSigned-off-by: Johan Jonker <jbx6244@gmail.com>\n---\n arch/arm/dts/Makefile | 3 -\n arch/arm/dts/rk3128-evb.dts | 99 ----\n arch/arm/dts/rk3128.dtsi | 780 -------------------------\n arch/arm/mach-rockchip/Kconfig | 1 +\n configs/evb-rk3128_defconfig | 4 +-\n include/dt-bindings/clock/rk3128-cru.h | 273 ---------\n 6 files changed, 3 insertions(+), 1157 deletions(-)\n delete mode 100644 arch/arm/dts/rk3128-evb.dts\n delete mode 100644 arch/arm/dts/rk3128.dtsi\n delete mode 100644 include/dt-bindings/clock/rk3128-cru.h\n\n--\n2.39.5", "diff": "diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile\nindex e79cfb4b6337..fdd057fdfe6c 100644\n--- a/arch/arm/dts/Makefile\n+++ b/arch/arm/dts/Makefile\n@@ -52,9 +52,6 @@ dtb-$(CONFIG_MACH_S900) += \\\n dtb-$(CONFIG_MACH_S700) += \\\n \ts700-cubieboard7.dtb\n\n-dtb-$(CONFIG_ROCKCHIP_RK3128) += \\\n-\trk3128-evb.dtb\n-\n dtb-$(CONFIG_ROCKCHIP_RK322X) += \\\n \trk3229-evb.dtb\n\ndiff --git a/arch/arm/dts/rk3128-evb.dts b/arch/arm/dts/rk3128-evb.dts\ndeleted file mode 100644\nindex 93291d787341..000000000000\n--- a/arch/arm/dts/rk3128-evb.dts\n+++ /dev/null\n@@ -1,99 +0,0 @@\n-// SPDX-License-Identifier: GPL-2.0+\n-/*\n- * (C) Copyright 2017 Rockchip Electronics Co., Ltd\n- */\n-\n-/dts-v1/;\n-\n-#include \"rk3128.dtsi\"\n-\n-/ {\n-\tmodel = \"Rockchip RK3128 Evaluation board\";\n-\tcompatible = \"rockchip,rk3128-evb\", \"rockchip,rk3128\";\n-\n-\tchosen {\n-\t\tstdout-path = &uart2;\n-\t};\n-\n-\tmemory@60000000 {\n-\t\tdevice_type = \"memory\";\n-\t\treg = <0x60000000 0x40000000>;\n-\t};\n-\n-\tvcc5v0_otg: vcc5v0-otg-drv {\n-\t\tcompatible = \"regulator-fixed\";\n-\t\tregulator-name = \"vcc5v0_otg\";\n-\t\tgpio = <&gpio0 26 GPIO_ACTIVE_HIGH>;\n-\t\tpinctrl-names = \"default\";\n-\t\tpinctrl-0 = <&otg_vbus_drv>;\n-\t\tregulator-min-microvolt = <5000000>;\n-\t\tregulator-max-microvolt = <5000000>;\n-\t};\n-\n-\tvcc5v0_host: vcc5v0-host-drv {\n-\t\tcompatible = \"regulator-fixed\";\n-\t\tregulator-name = \"vcc5v0_host\";\n-\t\tgpio = <&gpio2 23 GPIO_ACTIVE_HIGH>;\n-\t\tpinctrl-names = \"default\";\n-\t\tpinctrl-0 = <&host_vbus_drv>;\n-\t\tregulator-min-microvolt = <5000000>;\n-\t\tregulator-max-microvolt = <5000000>;\n-\t\tregulator-always-on;\n-\t};\n-};\n-\n-&emmc {\n-\tfifo-mode;\n-\tstatus = \"okay\";\n-};\n-\n-&i2c1 {\n-\tstatus = \"okay\";\n-\n-\thym8563: hym8563@51 {\n-\t\tcompatible = \"haoyu,hym8563\";\n-\t\treg = <0x51>;\n-\t\t#clock-cells = <0>;\n-\t\tclock-frequency = <32768>;\n-\t\tclock-output-names = \"xin32k\";\n-\t};\n-};\n-\n-&u2phy {\n-\tstatus = \"okay\";\n-};\n-\n-&u2phy_otg {\n-\tstatus = \"okay\";\n-};\n-\n-&u2phy_host {\n-\tstatus = \"okay\";\n-};\n-\n-&usb_host_ehci {\n-\tstatus = \"okay\";\n-};\n-\n-&usb_host_ohci {\n-\tstatus = \"okay\";\n-};\n-\n-&usb_otg {\n-\tvbus-supply = <&vcc5v0_otg>;\n-\tstatus = \"okay\";\n-};\n-\n-&pinctrl {\n-\tusb_otg {\n-\t\totg_vbus_drv: host-vbus-drv {\n-\t\t\trockchip,pins = <0 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;\n-\t\t};\n-\t};\n-\n-\tusb_host {\n-\t\thost_vbus_drv: host-vbus-drv {\n-\t\t\trockchip,pins = <2 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>;\n-\t\t};\n-\t};\n-};\ndiff --git a/arch/arm/dts/rk3128.dtsi b/arch/arm/dts/rk3128.dtsi\ndeleted file mode 100644\nindex 3253c6403413..000000000000\n--- a/arch/arm/dts/rk3128.dtsi\n+++ /dev/null\n@@ -1,780 +0,0 @@\n-// SPDX-License-Identifier: GPL-2.0+\n-/*\n- * (C) Copyright 2017 Rockchip Electronics Co., Ltd\n- */\n-\n-#include <dt-bindings/gpio/gpio.h>\n-#include <dt-bindings/interrupt-controller/irq.h>\n-#include <dt-bindings/interrupt-controller/arm-gic.h>\n-#include <dt-bindings/pinctrl/rockchip.h>\n-#include <dt-bindings/clock/rk3128-cru.h>\n-\n-/ {\n-\tcompatible = \"rockchip,rk3128\";\n-\trockchip,sram = <&sram>;\n-\tinterrupt-parent = <&gic>;\n-\t#address-cells = <1>;\n-\t#size-cells = <1>;\n-\n-\taliases {\n-\t\tgpio0 = &gpio0;\n-\t\tgpio1 = &gpio1;\n-\t\tgpio2 = &gpio2;\n-\t\tgpio3 = &gpio3;\n-\t\ti2c0 = &i2c0;\n-\t\ti2c1 = &i2c1;\n-\t\ti2c2 = &i2c2;\n-\t\ti2c3 = &i2c3;\n-\t\tspi0 = &spi0;\n-\t\tserial0 = &uart0;\n-\t\tserial1 = &uart1;\n-\t\tserial2 = &uart2;\n-\t\tmmc0 = &emmc;\n-\t\tmmc1 = &sdmmc;\n-\t};\n-\n-\tarm-pmu {\n-\t\tcompatible = \"arm,cortex-a7-pmu\";\n-\t\tinterrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,\n-\t\t\t <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,\n-\t\t\t <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,\n-\t\t\t <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;\n-\t};\n-\n-\tcpus {\n-\t\t#address-cells = <1>;\n-\t\t#size-cells = <0>;\n-\t\tenable-method = \"rockchip,rk3128-smp\";\n-\n-\t\tcpu0: cpu@0 {\n-\t\t\tdevice_type = \"cpu\";\n-\t\t\tcompatible = \"arm,cortex-a7\";\n-\t\t\treg = <0x0>;\n-\t\t\toperating-points = <\n-\t\t\t\t/* KHz uV */\n-\t\t\t\t 816000 1000000\n-\t\t\t>;\n-\t\t\t#cooling-cells = <2>; /* min followed by max */\n-\t\t\tclock-latency = <40000>;\n-\t\t\tclocks = <&cru ARMCLK>;\n-\t\t};\n-\n-\t\tcpu1: cpu@1 {\n-\t\t\tdevice_type = \"cpu\";\n-\t\t\tcompatible = \"arm,cortex-a7\";\n-\t\t\treg = <0x1>;\n-\t\t};\n-\n-\t\tcpu2: cpu@2 {\n-\t\t\tdevice_type = \"cpu\";\n-\t\t\tcompatible = \"arm,cortex-a7\";\n-\t\t\treg = <0x2>;\n-\t\t};\n-\n-\t\tcpu3: cpu@3 {\n-\t\t\tdevice_type = \"cpu\";\n-\t\t\tcompatible = \"arm,cortex-a7\";\n-\t\t\treg = <0x3>;\n-\t\t};\n-\t};\n-\n-\tcpu_axi_bus: cpu_axi_bus {\n-\t\tcompatible = \"rockchip,cpu_axi_bus\";\n-\t\t#address-cells = <1>;\n-\t\t#size-cells = <1>;\n-\t\tranges;\n-\n-\t\tqos {\n-\t\t\t#address-cells = <1>;\n-\t\t\t#size-cells = <1>;\n-\t\t\tranges;\n-\n-\t\t\tcrypto {\n-\t\t\t\treg = <0x10128080 0x20>;\n-\t\t\t};\n-\n-\t\t\tcore {\n-\t\t\t\treg = <0x1012a000 0x20>;\n-\t\t\t};\n-\n-\t\t\tperi {\n-\t\t\t\treg = <0x1012c000 0x20>;\n-\t\t\t};\n-\n-\t\t\tgpu {\n-\t\t\t\treg = <0x1012d000 0x20>;\n-\t\t\t};\n-\n-\t\t\tvpu {\n-\t\t\t\treg = <0x1012e000 0x20>;\n-\t\t\t};\n-\n-\t\t\trga {\n-\t\t\t\treg = <0x1012f000 0x20>;\n-\t\t\t};\n-\t\t\tebc {\n-\t\t\t\treg = <0x1012f080 0x20>;\n-\t\t\t};\n-\n-\t\t\tiep {\n-\t\t\t\treg = <0x1012f100 0x20>;\n-\t\t\t};\n-\n-\t\t\tlcdc {\n-\t\t\t\treg = <0x1012f180 0x20>;\n-\t\t\t\trockchip,priority = <3 3>;\n-\t\t\t};\n-\n-\t\t\tvip {\n-\t\t\t\treg = <0x1012f200 0x20>;\n-\t\t\t\trockchip,priority = <3 3>;\n-\t\t\t};\n-\t\t};\n-\n-\t\tmsch {\n-\t\t\t#address-cells = <1>;\n-\t\t\t#size-cells = <1>;\n-\t\t\tranges;\n-\n-\t\t\tmsch@10128000 {\n-\t\t\t\treg = <0x10128000 0x20>;\n-\t\t\t\trockchip,read-latency = <0x3f>;\n-\t\t\t};\n-\t\t};\n-\t};\n-\n-\tpsci {\n-\t\tcompatible = \"arm,psci\";\n-\t\tmethod = \"smc\";\n-\t\tcpu_suspend = <0x84000001>;\n-\t\tcpu_off = <0x84000002>;\n-\t\tcpu_on = <0x84000003>;\n-\t\tmigrate = <0x84000005>;\n-\t};\n-\n-\tamba {\n-\t\tcompatible = \"arm,amba-bus\";\n-\t\t#address-cells = <1>;\n-\t\t#size-cells = <1>;\n-\t\tinterrupt-parent = <&gic>;\n-\t\tranges;\n-\n-\t\tpdma: dma-controller@20078000 {\n-\t\t\tcompatible = \"arm,pl330\", \"arm,primecell\";\n-\t\t\treg = <0x20078000 0x4000>;\n-\t\t\tarm,pl330-broken-no-flushp;//2\n-\t\t\tinterrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,\n-\t\t\t\t <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;\n-\t\t\t#dma-cells = <1>;\n-\t\t\tclocks = <&cru ACLK_DMAC>;\n-\t\t\tclock-names = \"apb_pclk\";\n-\t\t};\n-\t};\n-\n-\txin24m: xin24m {\n-\t\tcompatible = \"fixed-clock\";\n-\t\tclock-frequency = <24000000>;\n-\t\tclock-output-names = \"xin24m\";\n-\t\t#clock-cells = <0>;\n-\t};\n-\n-\txin12m: xin12m {\n-\t\tcompatible = \"fixed-clock\";\n-\t\tclock-frequency = <12000000>;\n-\t\tclock-output-names = \"xin12m\";\n-\t\t#clock-cells = <0>;\n-\t};\n-\n-\ttimer {\n-\t\tcompatible = \"arm,armv7-timer\";\n-\t\tarm,cpu-registers-not-fw-configured;\n-\t\tinterrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,\n-\t\t\t <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;\n-\t\tclock-frequency = <24000000>;\n-\t};\n-\n-\ttimer@20044000 {\n-\t\tcompatible = \"arm,armv7-timer\";\n-\t\treg = <0x20044000 0xb8>;\n-\t\tinterrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;\n-\t\trockchip,broadcast = <1>;\n-\t};\n-\n-\twatchdog: watchdog@2004c000 {\n-\t\tcompatible = \"rockchip,rk3128-wdt\", \"snps,dw-wdt\";\n-\t\treg = <0x2004c000 0x100>;\n-\t\tclocks = <&cru PCLK_WDT>;\n-\t\tinterrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;\n-\t\trockchip,irq = <1>;\n-\t\trockchip,timeout = <60>;\n-\t\trockchip,atboot = <1>;\n-\t\trockchip,debug = <0>;\n-\t};\n-\n-\treset: reset@20000110 {\n-\t\tcompatible = \"rockchip,reset\";\n-\t\treg = <0x20000110 0x24>;\n-\t\t#reset-cells = <1>;\n-\t};\n-\n-\tnandc: nand-controller@10500000 {\n-\t\tcompatible = \"rockchip,rk3128-nfc\", \"rockchip,rk2928-nfc\";\n-\t\treg = <0x10500000 0x4000>;\n-\t\tinterrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;\n-\t\tpinctrl-names = \"default\";\n-\t\tpinctrl-0 = <&nandc_ale &nandc_cle &nandc_wrn &nandc_rdn &nandc_rdy &nandc_cs0 &nandc_data>;\n-\t\tclocks = <&cru HCLK_NANDC>, <&cru SCLK_NANDC>;\n-\t\tclock-names = \"ahb\", \"nfc\";\n-\t};\n-\n-\tcru: clock-controller@20000000 {\n-\t\tcompatible = \"rockchip,rk3128-cru\";\n-\t\treg = <0x20000000 0x1000>;\n-\t\tclocks = <&xin24m>;\n-\t\tclock-names = \"xin24m\";\n-\t\trockchip,grf = <&grf>;\n-\t\t#clock-cells = <1>;\n-\t\t#reset-cells = <1>;\n-\t\tassigned-clocks = <&cru PLL_GPLL>;\n-\t\tassigned-clock-rates = <594000000>;\n-\t};\n-\n-\tuart0: serial@20060000 {\n-\t\tcompatible = \"rockchip,rk3128-uart\", \"snps,dw-apb-uart\";\n-\t\treg = <0x20060000 0x100>;\n-\t\tinterrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;\n-\t\treg-shift = <2>;\n-\t\treg-io-width = <4>;\n-\t\tclock-frequency = <24000000>;\n-\t\tclocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;\n-\t\tclock-names = \"baudclk\", \"apb_pclk\";\n-\t\tpinctrl-names = \"default\";\n-\t\tpinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;\n-\t\tdmas = <&pdma 2>, <&pdma 3>;\n-\t\t#dma-cells = <2>;\n-\t};\n-\n-\tuart1: serial@20064000 {\n-\t\tcompatible = \"rockchip,rk3128-uart\", \"snps,dw-apb-uart\";\n-\t\treg = <0x20064000 0x100>;\n-\t\tinterrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;\n-\t\treg-shift = <2>;\n-\t\treg-io-width = <4>;\n-\t\tclock-frequency = <24000000>;\n-\t\tclocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;\n-\t\tclock-names = \"baudclk\", \"apb_pclk\";\n-\t\tpinctrl-names = \"default\";\n-\t\tpinctrl-0 = <&uart1_xfer>;\n-\t\tdmas = <&pdma 4>, <&pdma 5>;\n-\t\t#dma-cells = <2>;\n-\t};\n-\n-\tuart2: serial@20068000 {\n-\t\tcompatible = \"rockchip,rk3128-uart\", \"snps,dw-apb-uart\";\n-\t\treg = <0x20068000 0x100>;\n-\t\tinterrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;\n-\t\treg-shift = <2>;\n-\t\treg-io-width = <4>;\n-\t\tclock-frequency = <24000000>;\n-\t\tclocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;\n-\t\tclock-names = \"baudclk\", \"apb_pclk\";\n-\t\tpinctrl-names = \"default\";\n-\t\tpinctrl-0 = <&uart2_xfer>;\n-\t\tdmas = <&pdma 6>, <&pdma 7>;\n-\t\t#dma-cells = <2>;\n-\t};\n-\n-\tsaradc: saradc@2006c000 {\n-\t\tcompatible = \"rockchip,saradc\";\n-\t\treg = <0x2006c000 0x100>;\n-\t\tinterrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;\n-\t\t#io-channel-cells = <1>;\n-\t\tclocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;\n-\t\tclock-names = \"saradc\", \"apb_pclk\";\n-\t\tresets = <&cru SRST_SARADC>;\n-\t\treset-names = \"saradc-apb\";\n-\t\tstatus = \"disabled\";\n-\t};\n-\n-\tpwm0: pwm@20050000 {\n-\t\tcompatible = \"rockchip,rk3128-pwm\", \"rockchip,rk3288-pwm\";\n-\t\treg = <0x20050000 0x10>;\n-\t\t#pwm-cells = <3>;\n-\t\tpinctrl-names = \"default\";\n-\t\tpinctrl-0 = <&pwm0_pin>;\n-\t\tclocks = <&cru PCLK_PWM>;\n-\t};\n-\n-\tpwm1: pwm@20050010 {\n-\t\tcompatible = \"rockchip,rk3128-pwm\", \"rockchip,rk3288-pwm\";\n-\t\treg = <0x20050010 0x10>;\n-\t\t#pwm-cells = <3>;\n-\t\tpinctrl-names = \"default\";\n-\t\tpinctrl-0 = <&pwm1_pin>;\n-\t\tclocks = <&cru PCLK_PWM>;\n-\t};\n-\n-\tpwm2: pwm@20050020 {\n-\t\tcompatible = \"rockchip,rk3128-pwm\", \"rockchip,rk3288-pwm\";\n-\t\treg = <0x20050020 0x10>;\n-\t\t#pwm-cells = <3>;\n-\t\tpinctrl-names = \"default\";\n-\t\tpinctrl-0 = <&pwm2_pin>;\n-\t\tclocks = <&cru PCLK_PWM>;\n-\t};\n-\n-\tpwm3: pwm@20050030 {\n-\t\tcompatible = \"rockchip,rk3128-pwm\", \"rockchip,rk3288-pwm\";\n-\t\treg = <0x20050030 0x10>;\n-\t\t#pwm-cells = <3>;\n-\t\tpinctrl-names = \"default\";\n-\t\tpinctrl-0 = <&pwm3_pin>;\n-\t\tclocks = <&cru PCLK_PWM>;\n-\t};\n-\n-\tsram: sram@10080400 {\n-\t\tcompatible = \"rockchip,rk3128-smp-sram\", \"mmio-sram\";\n-\t\treg = <0x10080400 0x1C00>;\n-\t\tmap-exec;\n-\t\tmap-cacheable;\n-\t};\n-\n-\tpmu: syscon@100a0000 {\n-\t\tcompatible = \"rockchip,rk3128-pmu\", \"syscon\", \"simple-mfd\";\n-\t\treg = <0x100a0000 0x1000>;\n-\t\t#address-cells = <1>;\n-\t\t#size-cells = <1>;\n-\t};\n-\n-\tgic: interrupt-controller@10139000 {\n-\t\tcompatible = \"arm,gic-400\";\n-\t\tinterrupt-controller;\n-\t\t#interrupt-cells = <3>;\n-\t\t#address-cells = <0>;\n-\t\treg = <0x10139000 0x1000>,\n-\t\t <0x1013a000 0x1000>,\n-\t\t <0x1013c000 0x2000>,\n-\t\t <0x1013e000 0x2000>;\n-\t\tinterrupts = <GIC_PPI 9 0xf04>;\n-\t};\n-\n-\tu2phy: usb2phy {\n-\t\tcompatible = \"rockchip,rk3128-usb2phy\";\n-\t\treg = <0x017c 0x0c>;\n-\t\trockchip,grf = <&grf>;\n-\t\tclocks = <&cru SCLK_OTGPHY0>;\n-\t\tclock-names = \"phyclk\";\n-\t\t#clock-cells = <0>;\n-\t\tclock-output-names = \"usb480m_phy\";\n-\t\tstatus = \"disabled\";\n-\n-\t\tu2phy_otg: otg-port {\n-\t\t\t#phy-cells = <0>;\n-\t\t\tinterrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,\n-\t\t\t\t <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,\n-\t\t\t\t <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;\n-\t\t\tinterrupt-names = \"otg-bvalid\", \"otg-id\",\n-\t\t\t\t\t \"linestate\";\n-\t\t\tstatus = \"disabled\";\n-\t\t};\n-\n-\t\tu2phy_host: host-port {\n-\t\t\t#phy-cells = <0>;\n-\t\t\tinterrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;\n-\t\t\tinterrupt-names = \"linestate\";\n-\t\t\tstatus = \"disabled\";\n-\t\t};\n-\t};\n-\n-\tusb_otg: usb@10180000 {\n-\t\tcompatible = \"rockchip,rk3128-usb\", \"rockchip,rk3066-usb\", \"snps,dwc2\";\n-\t\treg = <0x10180000 0x40000>;\n-\t\tinterrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;\n-\t\tclocks = <&cru HCLK_OTG>;\n-\t\tclock-names = \"otg\";\n-\t\tdr_mode = \"otg\";\n-\t\tphys = <&u2phy_otg>;\n-\t\tphy-names = \"usb2-phy\";\n-\t\tstatus = \"disabled\";\n-\t};\n-\n-\tusb_host_ehci: usb@101c0000 {\n-\t\tcompatible = \"generic-ehci\";\n-\t\treg = <0x101c0000 0x20000>;\n-\t\tinterrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;\n-\t\tphys = <&u2phy_host>;\n-\t\tphy-names = \"usb\";\n-\t\tstatus = \"disabled\";\n-\t};\n-\n-\tusb_host_ohci: usb@101e0000 {\n-\t\tcompatible = \"generic-ohci\";\n-\t\treg = <0x101e0000 0x20000>;\n-\t\tinterrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;\n-\t\tphys = <&u2phy_host>;\n-\t\tphy-names = \"usb\";\n-\t\tstatus = \"disabled\";\n-\t};\n-\n-\tsdmmc: mmc@10214000 {\n-\t\tcompatible = \"rockchip,rk3128-dw-mshc\", \"rockchip,rk3288-dw-mshc\";\n-\t\treg = <0x10214000 0x4000>;\n-\t\tmax-frequency = <150000000>;\n-\t\tinterrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;\n-\t\tclocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,\n-\t\t\t <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;\n-\t\tclock-names = \"biu\", \"ciu\", \"ciu-drive\", \"ciu-sample\";\n-\t\tfifo-depth = <0x100>;\n-\t\tpinctrl-names = \"default\";\n-\t\tpinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>;\n-\t\tbus-width = <4>;\n-\t\tstatus = \"disabled\";\n-\t};\n-\n-\temmc: mmc@1021c000 {\n-\t\tcompatible = \"rockchip,rk3128-dw-mshc\", \"rockchip,rk3288-dw-mshc\";\n-\t\treg = <0x1021c000 0x4000>;\n-\t\tmax-frequency = <150000000>;\n-\t\tinterrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;\n-\t\tclocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,\n-\t\t\t <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;\n-\t\tclock-names = \"biu\", \"ciu\", \"ciu-drive\", \"ciu-sample\";\n-\t\tbus-width = <8>;\n-\t\tdefault-sample-phase = <158>;\n-\t\tnum-slots = <1>;\n-\t\tfifo-depth = <0x100>;\n-\t\tpinctrl-names = \"default\";\n-\t\tpinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;\n-\t\tresets = <&cru SRST_EMMC>;\n-\t\treset-names = \"reset\";\n-\t\tstatus = \"disabled\";\n-\t};\n-\n-\ti2c0: i2c@20072000 {\n-\t\tcompatible = \"rockchip,rk3128-i2c\", \"rockchip,rk3288-i2c\";\n-\t\treg = <20072000 0x1000>;\n-\t\tinterrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;\n-\t\t#address-cells = <1>;\n-\t\t#size-cells = <0>;\n-\t\tclock-names = \"i2c\";\n-\t\tclocks = <&cru PCLK_I2C0>;\n-\t\tpinctrl-names = \"default\";\n-\t\tpinctrl-0 = <&i2c0_xfer>;\n-\t};\n-\n-\ti2c1: i2c@20056000 {\n-\t\tcompatible = \"rockchip,rk3128-i2c\", \"rockchip,rk3288-i2c\";\n-\t\treg = <0x20056000 0x1000>;\n-\t\tinterrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;\n-\t\t#address-cells = <1>;\n-\t\t#size-cells = <0>;\n-\t\tclock-names = \"i2c\";\n-\t\tclocks = <&cru PCLK_I2C1>;\n-\t\tpinctrl-names = \"default\";\n-\t\tpinctrl-0 = <&i2c1_xfer>;\n-\t};\n-\n-\ti2c2: i2c@2005a000 {\n-\t\tcompatible = \"rockchip,rk3128-i2c\", \"rockchip,rk3288-i2c\";\n-\t\treg = <0x2005a000 0x1000>;\n-\t\tinterrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;\n-\t\t#address-cells = <1>;\n-\t\t#size-cells = <0>;\n-\t\tclock-names = \"i2c\";\n-\t\tclocks = <&cru PCLK_I2C2>;\n-\t\tpinctrl-names = \"default\";\n-\t\tpinctrl-0 = <&i2c2_xfer>;\n-\t};\n-\n-\ti2c3: i2c@2005e000 {\n-\t\tcompatible = \"rockchip,rk3128-i2c\", \"rockchip,rk3288-i2c\";\n-\t\treg = <0x2005e000 0x1000>;\n-\t\tinterrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;\n-\t\t#address-cells = <1>;\n-\t\t#size-cells = <0>;\n-\t\tclock-names = \"i2c\";\n-\t\tclocks = <&cru PCLK_I2C3>;\n-\t\tpinctrl-names = \"default\";\n-\t\tpinctrl-0 = <&i2c3_xfer>;\n-\t};\n-\n-\tspi0: spi@20074000 {\n-\t\tcompatible = \"rockchip,rk3128-spi\", \"rockchip,rk3066-spi\";\n-\t\treg = <0x20074000 0x1000>;\n-\t\tinterrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;\n-\t\t#address-cells = <1>;\n-\t\t#size-cells = <0>;\n-\t\tpinctrl-names = \"default\";\n-\t\tpinctrl-0 = <&spi0_txd_mux0 &spi0_rxd_mux0 &spi0_clk_mux0 &spi0_cs0_mux0 &spi0_cs1_mux0>;\n-\t\trockchip,spi-src-clk = <0>;\n-\t\tnum-cs = <2>;\n-\t\tclocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;\n-\t\tclock-names = \"spiclk\", \"apb_pclk\";\n-\t\tdmas = <&pdma 8>, <&pdma 9>;\n-\t\t#dma-cells = <2>;\n-\t\tdma-names = \"tx\", \"rx\";\n-\t};\n-\n-\tgrf: syscon@20008000 {\n-\t\tcompatible = \"rockchip,rk3128-grf\", \"syscon\";\n-\t\treg = <0x20008000 0x1000>;\n-\t};\n-\n-\tpinctrl: pinctrl@20008000 {\n-\t\tcompatible = \"rockchip,rk3128-pinctrl\";\n-\t\treg = <0x20008000 0xA8>,\n-\t\t <0x200080A8 0x4C>,\n-\t\t <0x20008118 0x20>,\n-\t\t <0x20008100 0x04>;\n-\t\treg-names = \"base\", \"mux\", \"pull\", \"drv\";\n-\t\trockchip,grf = <&grf>;\n-\t\t#address-cells = <1>;\n-\t\t#size-cells = <1>;\n-\t\tranges;\n-\n-\t\tgpio0: gpio@2007c000 {\n-\t\t\tcompatible = \"rockchip,gpio-bank\";\n-\t\t\treg = <0x2007c000 0x100>;\n-\t\t\tinterrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;\n-\t\t\tclocks = <&cru PCLK_GPIO0>;\n-\t\t\tgpio-controller;\n-\t\t\t#gpio-cells = <2>;\n-\t\t\tinterrupt-controller;\n-\t\t\t#interrupt-cells = <2>;\n-\t\t};\n-\n-\t\tgpio1: gpio@20080000 {\n-\t\t\tcompatible = \"rockchip,gpio-bank\";\n-\t\t\treg = <0x20080000 0x100>;\n-\t\t\tinterrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;\n-\t\t\tclocks = <&cru PCLK_GPIO1>;\n-\t\t\tgpio-controller;\n-\t\t\t#gpio-cells = <2>;\n-\t\t\tinterrupt-controller;\n-\t\t\t#interrupt-cells = <2>;\n-\t\t};\n-\n-\t\tgpio2: gpio@20084000 {\n-\t\t\tcompatible = \"rockchip,gpio-bank\";\n-\t\t\treg = <0x20084000 0x100>;\n-\t\t\tinterrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;\n-\t\t\tclocks = <&cru PCLK_GPIO2>;\n-\t\t\tgpio-controller;\n-\t\t\t#gpio-cells = <2>;\n-\t\t\tinterrupt-controller;\n-\t\t\t#interrupt-cells = <2>;\n-\t\t};\n-\n-\t\tgpio3: gpio@20088000 {\n-\t\t\tcompatible = \"rockchip,gpio-bank\";\n-\t\t\treg = <0x20088000 0x100>;\n-\t\t\tinterrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;\n-\t\t\tclocks = <&cru PCLK_GPIO3>;\n-\t\t\tgpio-controller;\n-\t\t\t#gpio-cells = <2>;\n-\t\t\tinterrupt-controller;\n-\t\t\t#interrupt-cells = <2>;\n-\t\t};\n-\n-\t\tpcfg_pull_up: pcfg-pull-up {\n-\t\t\tbias-pull-up;\n-\t\t};\n-\n-\t\tpcfg_pull_down: pcfg-pull-down {\n-\t\t\tbias-pull-down;\n-\t\t};\n-\n-\t\tpcfg_pull_none: pcfg-pull-none {\n-\t\t\tbias-disable;\n-\t\t};\n-\n-\t\temmc {\n-\t\t\t/*\n-\t\t\t * We run eMMC at max speed; bump up drive strength.\n-\t\t\t * We also have external pulls, so disable the internal ones.\n-\t\t\t */\n-\n-\t\t\temmc_clk: emmc-clk {\n-\t\t\t\trockchip,pins = <2 RK_PA7 2 &pcfg_pull_none>;\n-\t\t\t};\n-\n-\t\t\temmc_cmd: emmc-cmd {\n-\t\t\t\trockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>;\n-\t\t\t};\n-\n-\t\t\temmc_pwren: emmc-pwren {\n-\t\t\t\trockchip,pins = <2 RK_PA5 2 &pcfg_pull_none>;\n-\t\t\t};\n-\n-\t\t\temmc_bus8: emmc-bus8 {\n-\t\t\t\trockchip,pins = <1 RK_PD0 2 &pcfg_pull_none>,\n-\t\t\t\t\t\t<1 RK_PD1 2 &pcfg_pull_none>,\n-\t\t\t\t\t\t<1 RK_PD2 2 &pcfg_pull_none>,\n-\t\t\t\t\t\t<1 RK_PD3 2 &pcfg_pull_none>,\n-\t\t\t\t\t\t<1 RK_PD4 2 &pcfg_pull_none>,\n-\t\t\t\t\t\t<1 RK_PD5 2 &pcfg_pull_none>,\n-\t\t\t\t\t\t<1 RK_PD6 2 &pcfg_pull_none>,\n-\t\t\t\t\t\t<1 RK_PD7 2 &pcfg_pull_none>;\n-\t\t\t};\n-\t\t};\n-\n-\t\tnandc{\n-\t\t\tnandc_ale:nandc-ale {\n-\t\t\t\trockchip,pins = <0 RK_PC2 1 &pcfg_pull_none>;\n-\t\t\t};\n-\n-\t\t\tnandc_cle:nandc-cle {\n-\t\t\t\trockchip,pins = <0 RK_PC2 1 &pcfg_pull_none>;\n-\t\t\t};\n-\n-\t\t\tnandc_wrn:nandc-wrn {\n-\t\t\t\trockchip,pins = <0 RK_PC2 1 &pcfg_pull_none>;\n-\t\t\t};\n-\n-\t\t\tnandc_rdn:nandc-rdn {\n-\t\t\t\trockchip,pins = <0 RK_PC2 1 &pcfg_pull_none>;\n-\t\t\t};\n-\n-\t\t\tnandc_rdy:nandc-rdy {\n-\t\t\t\trockchip,pins = <0 RK_PC2 1 &pcfg_pull_none>;\n-\t\t\t};\n-\n-\t\t\tnandc_cs0:nandc-cs0 {\n-\t\t\t\trockchip,pins = <0 RK_PC2 1 &pcfg_pull_none>;\n-\t\t\t};\n-\n-\t\t\tnandc_data: nandc-data {\n-\t\t\t\trockchip,pins = <0 RK_PC2 1 &pcfg_pull_none>;\n-\t\t\t};\n-\t\t};\n-\n-\t\tuart0 {\n-\t\t\tuart0_xfer: uart0-xfer {\n-\t\t\t\trockchip,pins = <0 RK_PC0 1 &pcfg_pull_none>,\n-\t\t\t\t\t\t<0 RK_PC1 1 &pcfg_pull_none>;\n-\t\t\t};\n-\n-\t\t\tuart0_cts: uart0-cts {\n-\t\t\t\trockchip,pins = <0 RK_PC2 1 &pcfg_pull_none>;\n-\t\t\t};\n-\n-\t\t\tuart0_rts: uart0-rts {\n-\t\t\t\trockchip,pins = <0 RK_PC3 1 &pcfg_pull_none>;\n-\t\t\t};\n-\t\t};\n-\n-\t\tuart1 {\n-\t\t\tuart1_xfer: uart1-xfer {\n-\t\t\t\trockchip,pins = <2 RK_PC6 1 &pcfg_pull_none>,\n-\t\t\t\t\t\t<2 RK_PC7 1 &pcfg_pull_none>;\n-\t\t\t};\n-\t\t};\n-\n-\t\tuart2 {\n-\t\t\tuart2_xfer: uart2-xfer {\n-\t\t\t\trockchip,pins = <1 RK_PC2 2 &pcfg_pull_none>,\n-\t\t\t\t\t\t<1 RK_PC3 2 &pcfg_pull_none>;\n-\t\t\t};\n-\t\t};\n-\n-\t\tsdmmc {\n-\t\t\tsdmmc_clk: sdmmc-clk {\n-\t\t\t\trockchip,pins = <1 RK_PC0 1 &pcfg_pull_none>;\n-\t\t\t};\n-\n-\t\t\tsdmmc_cmd: sdmmc-cmd {\n-\t\t\t\trockchip,pins = <1 RK_PC1 1 &pcfg_pull_up>;\n-\t\t\t};\n-\n-\t\t\tsdmmc_wp: sdmmc-wp {\n-\t\t\t\trockchip,pins = <1 RK_PA7 1 &pcfg_pull_up>;\n-\t\t\t};\n-\n-\t\t\tsdmmc_pwren: sdmmc-pwren {\n-\t\t\t\trockchip,pins = <1 RK_PB6 1 &pcfg_pull_up>;\n-\t\t\t};\n-\n-\t\t\tsdmmc_bus4: sdmmc-bus4 {\n-\t\t\t\trockchip,pins = <1 RK_PC2 1 &pcfg_pull_up>,\n-\t\t\t\t\t\t<1 RK_PC3 1 &pcfg_pull_up>,\n-\t\t\t\t\t\t<1 RK_PC4 1 &pcfg_pull_up>,\n-\t\t\t\t\t\t<1 RK_PC5 1 &pcfg_pull_up>;\n-\t\t\t};\n-\t\t};\n-\n-\t\tpwm0 {\n-\t\t\tpwm0_pin: pwm0-pin {\n-\t\t\t\trockchip,pins = <0 RK_PA0 2 &pcfg_pull_none>;\n-\t\t\t};\n-\t\t};\n-\n-\t\tpwm1 {\n-\t\t\tpwm1_pin: pwm1-pin {\n-\t\t\t\trockchip,pins = <0 RK_PA1 2 &pcfg_pull_none>;\n-\t\t\t};\n-\t\t};\n-\n-\t\tpwm2 {\n-\t\t\tpwm2_pin: pwm2-pin {\n-\t\t\t\trockchip,pins = <0 RK_PA1 2 &pcfg_pull_none>;\n-\t\t\t};\n-\t\t};\n-\n-\t\tpwm3 {\n-\t\t\tpwm3_pin: pwm3-pin {\n-\t\t\t\trockchip,pins = <0 RK_PD3 1 &pcfg_pull_none>;\n-\t\t\t};\n-\t\t};\n-\n-\t\ti2c0 {\n-\t\t\ti2c0_xfer: i2c0-xfer {\n-\t\t\t\trockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>,\n-\t\t\t\t\t\t<0 RK_PA1 1 &pcfg_pull_none>;\n-\t\t\t};\n-\t\t};\n-\n-\t\ti2c1 {\n-\t\t\ti2c1_xfer: i2c1-xfer {\n-\t\t\t\trockchip,pins = <0 RK_PA2 1 &pcfg_pull_none>,\n-\t\t\t\t\t\t<0 RK_PA3 1 &pcfg_pull_none>;\n-\t\t\t};\n-\t\t};\n-\n-\t\ti2c2 {\n-\t\t\ti2c2_xfer: i2c2-xfer {\n-\t\t\t\trockchip,pins = <2 RK_PC4 3 &pcfg_pull_none>,\n-\t\t\t\t\t\t<2 RK_PC5 3 &pcfg_pull_none>;\n-\t\t\t};\n-\t\t};\n-\n-\t\ti2c3 {\n-\t\t\ti2c3_xfer: i2c3-xfer {\n-\t\t\t\trockchip,pins = <0 RK_PA6 1 &pcfg_pull_none>,\n-\t\t\t\t\t\t<0 RK_PA7 1 &pcfg_pull_none>;\n-\t\t\t};\n-\t\t};\n-\n-\t\tspi0 {\n-\t\t\tspi0_txd_mux0:spi0-txd-mux0 {\n-\t\t\t\trockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>;\n-\t\t\t};\n-\n-\t\t\tspi0_rxd_mux0:spi0-rxd-mux0 {\n-\t\t\t\trockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>;\n-\t\t\t};\n-\n-\t\t\tspi0_clk_mux0:spi0-clk-mux0 {\n-\t\t\t\trockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>;\n-\t\t\t};\n-\n-\t\t\tspi0_cs0_mux0:spi0-cs0-mux0 {\n-\t\t\t\trockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>;\n-\t\t\t};\n-\n-\t\t\tspi0_cs1_mux0:spi0-cs1-mux0 {\n-\t\t\t\trockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>;\n-\t\t\t};\n-\t\t};\n-\n-\t};\n-};\ndiff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig\nindex 108713488af1..02737c62df03 100644\n--- a/arch/arm/mach-rockchip/Kconfig\n+++ b/arch/arm/mach-rockchip/Kconfig\n@@ -65,6 +65,7 @@ config ROCKCHIP_RK3066\n config ROCKCHIP_RK3128\n \tbool \"Support Rockchip RK3128\"\n \tselect CPU_V7A\n+\timply OF_UPSTREAM\n \timply ROCKCHIP_COMMON_BOARD\n \thelp\n \t The Rockchip RK3128 is a ARM-based SoC with a quad-core Cortex-A7\ndiff --git a/configs/evb-rk3128_defconfig b/configs/evb-rk3128_defconfig\nindex 90cbf55806af..eb009c7c36ae 100644\n--- a/configs/evb-rk3128_defconfig\n+++ b/configs/evb-rk3128_defconfig\n@@ -8,7 +8,7 @@ CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y\n CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x60100000\n CONFIG_SF_DEFAULT_SPEED=20000000\n CONFIG_ENV_OFFSET=0x0\n-CONFIG_DEFAULT_DEVICE_TREE=\"rk3128-evb\"\n+CONFIG_DEFAULT_DEVICE_TREE=\"rockchip/rk3128-evb\"\n CONFIG_DM_RESET=y\n CONFIG_ROCKCHIP_RK3128=y\n CONFIG_SYS_BOOTM_LEN=0x4000000\n@@ -18,7 +18,7 @@ CONFIG_DEBUG_UART_CLOCK=24000000\n # CONFIG_DEBUG_UART_BOARD_INIT is not set\n CONFIG_DEBUG_UART=y\n CONFIG_FIT=y\n-CONFIG_DEFAULT_FDT_FILE=\"rk3128-evb.dtb\"\n+CONFIG_DEFAULT_FDT_FILE=\"rockchip/rk3128-evb.dtb\"\n # CONFIG_DISPLAY_CPUINFO is not set\n CONFIG_DISPLAY_BOARDINFO_LATE=y\n CONFIG_CMD_GPT=y\ndiff --git a/include/dt-bindings/clock/rk3128-cru.h b/include/dt-bindings/clock/rk3128-cru.h\ndeleted file mode 100644\nindex 6a47825dac5d..000000000000\n--- a/include/dt-bindings/clock/rk3128-cru.h\n+++ /dev/null\n@@ -1,273 +0,0 @@\n-/* SPDX-License-Identifier: GPL-2.0-or-later */\n-/*\n- * Copyright (c) 2017 Rockchip Electronics Co. Ltd.\n- * Author: Elaine <zhangqing@rock-chips.com>\n- */\n-\n-#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3128_H\n-#define _DT_BINDINGS_CLK_ROCKCHIP_RK3128_H\n-\n-/* core clocks */\n-#define PLL_APLL\t\t1\n-#define PLL_DPLL\t\t2\n-#define PLL_CPLL\t\t3\n-#define PLL_GPLL\t\t4\n-#define ARMCLK\t\t\t5\n-#define PLL_GPLL_DIV2\t\t6\n-#define PLL_GPLL_DIV3\t\t7\n-\n-/* sclk gates (special clocks) */\n-#define SCLK_SPI0\t\t65\n-#define SCLK_NANDC\t\t67\n-#define SCLK_SDMMC\t\t68\n-#define SCLK_SDIO\t\t69\n-#define SCLK_EMMC\t\t71\n-#define SCLK_UART0\t\t77\n-#define SCLK_UART1\t\t78\n-#define SCLK_UART2\t\t79\n-#define SCLK_I2S0\t\t80\n-#define SCLK_I2S1\t\t81\n-#define SCLK_SPDIF\t\t83\n-#define SCLK_TIMER0\t\t85\n-#define SCLK_TIMER1\t\t86\n-#define SCLK_TIMER2\t\t87\n-#define SCLK_TIMER3\t\t88\n-#define SCLK_TIMER4\t\t89\n-#define SCLK_TIMER5\t\t90\n-#define SCLK_SARADC\t\t91\n-#define SCLK_I2S_OUT\t\t113\n-#define SCLK_SDMMC_DRV\t\t114\n-#define SCLK_SDIO_DRV\t\t115\n-#define SCLK_EMMC_DRV\t\t117\n-#define SCLK_SDMMC_SAMPLE\t118\n-#define SCLK_SDIO_SAMPLE\t119\n-#define SCLK_EMMC_SAMPLE\t121\n-#define SCLK_VOP\t\t122\n-#define SCLK_MAC_SRC\t\t124\n-#define SCLK_MAC\t\t126\n-#define SCLK_MAC_REFOUT\t\t127\n-#define SCLK_MAC_REF\t\t128\n-#define SCLK_MAC_RX\t\t129\n-#define SCLK_MAC_TX\t\t130\n-#define SCLK_HEVC_CORE\t\t134\n-#define SCLK_RGA\t\t135\n-#define SCLK_CRYPTO\t\t138\n-#define SCLK_TSP\t\t139\n-#define SCLK_OTGPHY0\t\t142\n-#define SCLK_OTGPHY1\t\t143\n-#define SCLK_DDRC\t\t144\n-#define SCLK_PVTM_FUNC\t\t145\n-#define SCLK_PVTM_CORE\t\t146\n-#define SCLK_PVTM_GPU\t\t147\n-#define SCLK_MIPI_24M\t\t148\n-#define SCLK_PVTM\t\t149\n-#define SCLK_CIF_SRC\t\t150\n-#define SCLK_CIF_OUT_SRC\t151\n-#define SCLK_CIF_OUT\t\t152\n-#define SCLK_SFC\t\t153\n-#define SCLK_USB480M\t\t154\n-\n-/* dclk gates */\n-#define DCLK_VOP\t\t190\n-#define DCLK_EBC\t\t191\n-\n-/* aclk gates */\n-#define ACLK_VIO0\t\t192\n-#define ACLK_VIO1\t\t193\n-#define ACLK_DMAC\t\t194\n-#define ACLK_CPU\t\t195\n-#define ACLK_VEPU\t\t196\n-#define ACLK_VDPU\t\t197\n-#define ACLK_CIF\t\t198\n-#define ACLK_IEP\t\t199\n-#define ACLK_LCDC0\t\t204\n-#define ACLK_RGA\t\t205\n-#define ACLK_PERI\t\t210\n-#define ACLK_VOP\t\t211\n-#define ACLK_GMAC\t\t212\n-#define ACLK_GPU\t\t213\n-\n-/* pclk gates */\n-#define PCLK_SARADC\t\t318\n-#define PCLK_WDT\t\t319\n-#define PCLK_GPIO0\t\t320\n-#define PCLK_GPIO1\t\t321\n-#define PCLK_GPIO2\t\t322\n-#define PCLK_GPIO3\t\t323\n-#define PCLK_VIO_H2P\t\t324\n-#define PCLK_MIPI\t\t325\n-#define PCLK_EFUSE\t\t326\n-#define PCLK_HDMI\t\t327\n-#define PCLK_ACODEC\t\t328\n-#define PCLK_GRF\t\t329\n-#define PCLK_I2C0\t\t332\n-#define PCLK_I2C1\t\t333\n-#define PCLK_I2C2\t\t334\n-#define PCLK_I2C3\t\t335\n-#define PCLK_SPI0\t\t338\n-#define PCLK_UART0\t\t341\n-#define PCLK_UART1\t\t342\n-#define PCLK_UART2\t\t343\n-#define PCLK_TSADC\t\t344\n-#define PCLK_PWM\t\t350\n-#define PCLK_TIMER\t\t353\n-#define PCLK_CPU\t\t354\n-#define PCLK_PERI\t\t363\n-#define PCLK_GMAC\t\t367\n-#define PCLK_PMU_PRE\t\t368\n-#define PCLK_SIM_CARD\t\t369\n-\n-/* hclk gates */\n-#define HCLK_SPDIF\t\t440\n-#define HCLK_GPS\t\t441\n-#define HCLK_USBHOST\t\t442\n-#define HCLK_I2S_8CH\t\t443\n-#define HCLK_I2S_2CH\t\t444\n-#define HCLK_VOP\t\t452\n-#define HCLK_NANDC\t\t453\n-#define HCLK_SDMMC\t\t456\n-#define HCLK_SDIO\t\t457\n-#define HCLK_EMMC\t\t459\n-#define HCLK_CPU\t\t460\n-#define HCLK_VEPU\t\t461\n-#define HCLK_VDPU\t\t462\n-#define HCLK_LCDC0\t\t463\n-#define HCLK_EBC\t\t465\n-#define HCLK_VIO\t\t466\n-#define HCLK_RGA\t\t467\n-#define HCLK_IEP\t\t468\n-#define HCLK_VIO_H2P\t\t469\n-#define HCLK_CIF\t\t470\n-#define HCLK_HOST2\t\t473\n-#define HCLK_OTG\t\t474\n-#define HCLK_TSP\t\t475\n-#define HCLK_CRYPTO\t\t476\n-#define HCLK_PERI\t\t478\n-\n-#define CLK_NR_CLKS\t\t(HCLK_PERI + 1)\n-\n-/* soft-reset indices */\n-#define SRST_CORE0_PO\t\t0\n-#define SRST_CORE1_PO\t\t1\n-#define SRST_CORE2_PO\t\t2\n-#define SRST_CORE3_PO\t\t3\n-#define SRST_CORE0\t\t4\n-#define SRST_CORE1\t\t5\n-#define SRST_CORE2\t\t6\n-#define SRST_CORE3\t\t7\n-#define SRST_CORE0_DBG\t\t8\n-#define SRST_CORE1_DBG\t\t9\n-#define SRST_CORE2_DBG\t\t10\n-#define SRST_CORE3_DBG\t\t11\n-#define SRST_TOPDBG\t\t12\n-#define SRST_ACLK_CORE\t\t13\n-#define SRST_STRC_SYS_A\t\t14\n-#define SRST_L2C\t\t15\n-\n-#define SRST_CPUSYS_H\t\t18\n-#define SRST_AHB2APBSYS_H\t19\n-#define SRST_SPDIF\t\t20\n-#define SRST_INTMEM\t\t21\n-#define SRST_ROM\t\t22\n-#define SRST_PERI_NIU\t\t23\n-#define SRST_I2S_2CH\t\t24\n-#define SRST_I2S_8CH\t\t25\n-#define SRST_GPU_PVTM\t\t26\n-#define SRST_FUNC_PVTM\t\t27\n-#define SRST_CORE_PVTM\t\t29\n-#define SRST_EFUSE_P\t\t30\n-#define SRST_ACODEC_P\t\t31\n-\n-#define SRST_GPIO0\t\t32\n-#define SRST_GPIO1\t\t33\n-#define SRST_GPIO2\t\t34\n-#define SRST_GPIO3\t\t35\n-#define SRST_MIPIPHY_P\t\t36\n-#define SRST_UART0\t\t39\n-#define SRST_UART1\t\t40\n-#define SRST_UART2\t\t41\n-#define SRST_I2C0\t\t43\n-#define SRST_I2C1\t\t44\n-#define SRST_I2C2\t\t45\n-#define SRST_I2C3\t\t46\n-#define SRST_SFC\t\t47\n-\n-#define SRST_PWM\t\t48\n-#define SRST_DAP_PO\t\t50\n-#define SRST_DAP\t\t51\n-#define SRST_DAP_SYS\t\t52\n-#define SRST_CRYPTO\t\t53\n-#define SRST_GRF\t\t55\n-#define SRST_GMAC\t\t56\n-#define SRST_PERIPH_SYS_A\t57\n-#define SRST_PERIPH_SYS_H\t58\n-#define SRST_PERIPH_SYS_P 59\n-#define SRST_SMART_CARD\t\t60\n-#define SRST_CPU_PERI\t\t61\n-#define SRST_EMEM_PERI\t\t62\n-#define SRST_USB_PERI\t\t63\n-\n-#define SRST_DMA\t\t64\n-#define SRST_GPS\t\t67\n-#define SRST_NANDC\t\t68\n-#define SRST_USBOTG0\t\t69\n-#define SRST_OTGC0\t\t71\n-#define SRST_USBOTG1\t\t72\n-#define SRST_OTGC1\t\t74\n-#define SRST_DDRMSCH\t\t79\n-\n-#define SRST_SDMMC\t\t81\n-#define SRST_SDIO\t\t82\n-#define SRST_EMMC\t\t83\n-#define SRST_SPI\t\t84\n-#define SRST_WDT\t\t86\n-#define SRST_SARADC\t\t87\n-#define SRST_DDRPHY\t\t88\n-#define SRST_DDRPHY_P\t\t89\n-#define SRST_DDRCTRL\t\t90\n-#define SRST_DDRCTRL_P\t\t91\n-#define SRST_TSP\t\t92\n-#define SRST_TSP_CLKIN\t\t93\n-#define SRST_HOST0_ECHI\t\t94\n-\n-#define SRST_HDMI_P\t\t96\n-#define SRST_VIO_ARBI_H\t\t97\n-#define SRST_VIO0_A\t\t98\n-#define SRST_VIO_BUS_H\t\t99\n-#define SRST_VOP_A\t\t100\n-#define SRST_VOP_H\t\t101\n-#define SRST_VOP_D\t\t102\n-#define SRST_UTMI0\t\t103\n-#define SRST_UTMI1\t\t104\n-#define SRST_USBPOR\t\t105\n-#define SRST_IEP_A\t\t106\n-#define SRST_IEP_H\t\t107\n-#define SRST_RGA_A\t\t108\n-#define SRST_RGA_H\t\t109\n-#define SRST_CIF0\t\t110\n-#define SRST_PMU\t\t111\n-\n-#define SRST_VCODEC_A\t\t112\n-#define SRST_VCODEC_H\t\t113\n-#define SRST_VIO1_A\t\t114\n-#define SRST_HEVC_CORE\t\t115\n-#define SRST_VCODEC_NIU_A\t116\n-#define SRST_PMU_NIU_P\t\t117\n-#define SRST_LCDC0_S\t\t119\n-#define SRST_GPU\t\t120\n-#define SRST_GPU_NIU_A\t\t122\n-#define SRST_EBC_A\t\t123\n-#define SRST_EBC_H\t\t124\n-\n-#define SRST_CORE_DBG\t\t128\n-#define SRST_DBG_P\t\t129\n-#define SRST_TIMER0\t\t130\n-#define SRST_TIMER1\t\t131\n-#define SRST_TIMER2\t\t132\n-#define SRST_TIMER3\t\t133\n-#define SRST_TIMER4\t\t134\n-#define SRST_TIMER5\t\t135\n-#define SRST_VIO_H2P\t\t136\n-#define SRST_VIO_MIPI_DSI\t137\n-\n-#endif\n", "prefixes": [ "v2", "1/5" ] }