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GET /api/1.2/patches/2234476/?format=api
HTTP 200 OK
Allow: GET, PUT, PATCH, HEAD, OPTIONS
Content-Type: application/json
Vary: Accept

{
    "id": 2234476,
    "url": "http://patchwork.ozlabs.org/api/1.2/patches/2234476/?format=api",
    "web_url": "http://patchwork.ozlabs.org/project/linux-mtd/patch/20260507-winbond-v6-18-rc1-spi-nor-swp-v5-25-93453e1a9597@bootlin.com/",
    "project": {
        "id": 3,
        "url": "http://patchwork.ozlabs.org/api/1.2/projects/3/?format=api",
        "name": "Linux MTD development",
        "link_name": "linux-mtd",
        "list_id": "linux-mtd.lists.infradead.org",
        "list_email": "linux-mtd@lists.infradead.org",
        "web_url": null,
        "scm_url": null,
        "webscm_url": null,
        "list_archive_url": "",
        "list_archive_url_format": "",
        "commit_url_format": ""
    },
    "msgid": "<20260507-winbond-v6-18-rc1-spi-nor-swp-v5-25-93453e1a9597@bootlin.com>",
    "list_archive_url": null,
    "date": "2026-05-07T16:47:06",
    "name": "[v5,25/28] mtd: spi-nor: winbond: Add W25H02NWxxAM CMP locking support",
    "commit_ref": null,
    "pull_url": null,
    "state": "new",
    "archived": false,
    "hash": "8594bb6b2c7cf7e6d95c32fd30004e7748108c22",
    "submitter": {
        "id": 73368,
        "url": "http://patchwork.ozlabs.org/api/1.2/people/73368/?format=api",
        "name": "Miquel Raynal",
        "email": "miquel.raynal@bootlin.com"
    },
    "delegate": null,
    "mbox": "http://patchwork.ozlabs.org/project/linux-mtd/patch/20260507-winbond-v6-18-rc1-spi-nor-swp-v5-25-93453e1a9597@bootlin.com/mbox/",
    "series": [
        {
            "id": 503226,
            "url": "http://patchwork.ozlabs.org/api/1.2/series/503226/?format=api",
            "web_url": "http://patchwork.ozlabs.org/project/linux-mtd/list/?series=503226",
            "date": "2026-05-07T16:46:51",
            "name": "mtd: spi-nor: Enhance software protection",
            "version": 5,
            "mbox": "http://patchwork.ozlabs.org/series/503226/mbox/"
        }
    ],
    "comments": "http://patchwork.ozlabs.org/api/patches/2234476/comments/",
    "check": "pending",
    "checks": "http://patchwork.ozlabs.org/api/patches/2234476/checks/",
    "tags": {},
    "related": [],
    "headers": {
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        ],
        "From": "Miquel Raynal <miquel.raynal@bootlin.com>",
        "Date": "Thu, 07 May 2026 18:47:06 +0200",
        "Subject": "[PATCH v5 25/28] mtd: spi-nor: winbond: Add W25H02NWxxAM CMP\n locking support",
        "MIME-Version": "1.0",
        "Message-Id": "\n <20260507-winbond-v6-18-rc1-spi-nor-swp-v5-25-93453e1a9597@bootlin.com>",
        "References": "\n <20260507-winbond-v6-18-rc1-spi-nor-swp-v5-0-93453e1a9597@bootlin.com>",
        "In-Reply-To": "\n <20260507-winbond-v6-18-rc1-spi-nor-swp-v5-0-93453e1a9597@bootlin.com>",
        "To": "Pratyush Yadav <pratyush@kernel.org>, Michael Walle <mwalle@kernel.org>,\n Takahiro Kuwano <takahiro.kuwano@infineon.com>,\n Richard Weinberger <richard@nod.at>, Vignesh Raghavendra <vigneshr@ti.com>,\n Jonathan Corbet <corbet@lwn.net>, Tudor Ambarus <tudor.ambarus@linaro.org>,\n Shuah Khan <skhan@linuxfoundation.org>",
        "Cc": "Sean Anderson <sean.anderson@linux.dev>,\n Thomas Petazzoni <thomas.petazzoni@bootlin.com>,\n Steam Lin <STLin2@winbond.com>, linux-mtd@lists.infradead.org,\n linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org,\n Miquel Raynal <miquel.raynal@bootlin.com>",
        "X-Mailer": "b4 0.14.3",
        "X-Last-TLS-Session-Version": "TLSv1.3",
        "X-CRM114-Version": "20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 ",
        "X-CRM114-CacheID": "sfid-20260507_174742_002919_D9BC6F4F ",
        "X-CRM114-Status": "GOOD (  14.80  )",
        "X-Spam-Score": "-0.2 (/)",
        "X-Spam-Report": "Spam detection software,\n running on the system \"desiato.infradead.org\",\n has NOT identified this incoming email as spam.  The original\n message has been attached to this so you can view it or label\n similar future email.  If you have any questions, see\n the administrator of that system for details.\n Content preview:  This chip has support for the locking complement (CMP)\n feature.\n    Add the relevant bit to enable it. Unfortunately,\n this chip also comes with\n    an incorrect BFPT table,\n indicating the Control Register cannot be read back.\n    This is wrong, reading back the register works and has no (observed) side\n    effect. [...]\n Content analysis details:   (-0.2 points, 5.0 required)\n  pts rule name              description\n ---- ----------------------\n --------------------------------------------------\n -0.0 SPF_PASS               SPF: sender matches SPF record\n -0.0 SPF_HELO_PASS          SPF: HELO matches SPF record\n -0.1 DKIM_VALID             Message has at least one valid DKIM or DK\n signature\n -0.1 DKIM_VALID_AU          Message has a valid DKIM or DK signature from\n author's\n                             domain\n  0.1 DKIM_SIGNED            Message has a DKIM or DK signature,\n not necessarily valid\n -0.1 DKIM_VALID_EF          Message has a valid DKIM or DK signature from\n                             envelope-from domain\n -0.0 DMARC_PASS             DMARC pass policy",
        "X-BeenThere": "linux-mtd@lists.infradead.org",
        "X-Mailman-Version": "2.1.34",
        "Precedence": "list",
        "List-Id": "Linux MTD discussion mailing list <linux-mtd.lists.infradead.org>",
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        "Sender": "\"linux-mtd\" <linux-mtd-bounces@lists.infradead.org>",
        "Errors-To": "linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org"
    },
    "content": "This chip has support for the locking complement (CMP) feature. Add\nthe relevant bit to enable it.\n\nUnfortunately, this chip also comes with an incorrect BFPT table,\nindicating the Control Register cannot be read back. This is wrong,\nreading back the register works and has no (observed) side effect. The\ndatasheet clearly indicates supporting the 35h command and all bits from\nthe CR are marked readable. QE and CMP bits are inside, and can be\nproperly read back.\n\nAdd a fixup for this, otherwise it would defeat the use of the CMP\nfeature.\n\nSigned-off-by: Miquel Raynal <miquel.raynal@bootlin.com>\n---\nTest run with W25H02NWxxAM:\n$ flash_lock -u /dev/mtd0\n$ flash_lock -l /dev/mtd0 $bs $all_but_one # all but the first\n$ show_sectors\nlocked sectors\n region (in hex)   | status   | #blocks\n ------------------+----------+--------\n 00000000-0000ffff | unlocked | 1\n 00010000-0fffffff |   locked | 4095\n$ flash_lock -u /dev/mtd0 $bs 1 # all but the two first\n$ show_sectors\nlocked sectors\n region (in hex)   | status   | #blocks\n ------------------+----------+--------\n 00000000-0001ffff | unlocked | 2\n 00020000-0fffffff |   locked | 4094\n$ flash_lock -u /dev/mtd0\n$ flash_lock -l /dev/mtd0 0 $all_but_one # same from the other side\n$ show_sectors\nlocked sectors\n region (in hex)   | status   | #blocks\n ------------------+----------+--------\n 00000000-0ffeffff |   locked | 4095\n 0fff0000-0fffffff | unlocked | 1\n$ flash_lock -u /dev/mtd0 $(($size - (2 * $bs))) 1 # all but two\n$ show_sectors\nlocked sectors\n region (in hex)   | status   | #blocks\n ------------------+----------+--------\n 00000000-0ffdffff |   locked | 4094\n 0ffe0000-0fffffff | unlocked | 2\n---\n drivers/mtd/spi-nor/winbond.c | 24 +++++++++++++++++++++++-\n 1 file changed, 23 insertions(+), 1 deletion(-)",
    "diff": "diff --git a/drivers/mtd/spi-nor/winbond.c b/drivers/mtd/spi-nor/winbond.c\nindex 7628fa7fb64f..2c48d6c4a0aa 100644\n--- a/drivers/mtd/spi-nor/winbond.c\n+++ b/drivers/mtd/spi-nor/winbond.c\n@@ -73,6 +73,26 @@ static const struct spi_nor_fixups w25q256_fixups = {\n \t.post_bfpt = w25q256_post_bfpt_fixups,\n };\n \n+static int\n+winbond_rdcr_post_bfpt_fixup(struct spi_nor *nor,\n+\t\t\t     const struct sfdp_parameter_header *bfpt_header,\n+\t\t\t     const struct sfdp_bfpt *bfpt)\n+{\n+\t/*\n+\t * W25H02NW, unlike its W25H512NW nor W25H01NW cousins, improperly sets\n+\t * the QE BFPT configuration bits, indicating a non readable CR. This is\n+\t * both incorrect and impractical, as the chip features a CMP bit for its\n+\t * locking scheme that lays in the Control Register, and needs to be read.\n+\t */\n+\tnor->flags &= ~SNOR_F_NO_READ_CR;\n+\n+\treturn 0;\n+}\n+\n+static const struct spi_nor_fixups winbond_rdcr_fixup = {\n+\t.post_bfpt = winbond_rdcr_post_bfpt_fixup,\n+};\n+\n /**\n  * winbond_nor_select_die() - Set active die.\n  * @nor:\tpointer to 'struct spi_nor'.\n@@ -370,7 +390,9 @@ static const struct flash_info winbond_nor_parts[] = {\n \t}, {\n \t\t/* W25H02NWxxAM */\n \t\t.id = SNOR_ID(0xef, 0xa0, 0x22),\n-\t\t.flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_TB_SR_BIT6 | SPI_NOR_4BIT_BP,\n+\t\t.flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_TB_SR_BIT6 |\n+\t\t\t SPI_NOR_4BIT_BP | SPI_NOR_HAS_CMP,\n+\t\t.fixups = &winbond_rdcr_fixup,\n \t},\n };\n \n",
    "prefixes": [
        "v5",
        "25/28"
    ]
}