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GET /api/1.2/patches/2234467/?format=api
{ "id": 2234467, "url": "http://patchwork.ozlabs.org/api/1.2/patches/2234467/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-mtd/patch/20260507-winbond-v6-18-rc1-spi-nor-swp-v5-14-93453e1a9597@bootlin.com/", "project": { "id": 3, "url": "http://patchwork.ozlabs.org/api/1.2/projects/3/?format=api", "name": "Linux MTD development", "link_name": "linux-mtd", "list_id": "linux-mtd.lists.infradead.org", "list_email": "linux-mtd@lists.infradead.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260507-winbond-v6-18-rc1-spi-nor-swp-v5-14-93453e1a9597@bootlin.com>", "list_archive_url": null, "date": "2026-05-07T16:46:55", "name": "[v5,14/28] mtd: spi-nor: swp: Create helpers for building the SR register", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "2f0919d680a669814d7470faab147f7ef82a331a", "submitter": { "id": 73368, "url": "http://patchwork.ozlabs.org/api/1.2/people/73368/?format=api", "name": "Miquel Raynal", "email": "miquel.raynal@bootlin.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-mtd/patch/20260507-winbond-v6-18-rc1-spi-nor-swp-v5-14-93453e1a9597@bootlin.com/mbox/", "series": [ { "id": 503226, "url": "http://patchwork.ozlabs.org/api/1.2/series/503226/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-mtd/list/?series=503226", "date": "2026-05-07T16:46:51", "name": "mtd: spi-nor: Enhance software protection", "version": 5, "mbox": "http://patchwork.ozlabs.org/series/503226/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2234467/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2234467/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n secure) header.d=lists.infradead.org header.i=@lists.infradead.org\n header.a=rsa-sha256 header.s=bombadil.20210309 header.b=aQZAypqO;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n unprotected) header.d=bootlin.com header.i=@bootlin.com header.a=rsa-sha256\n header.s=dkim header.b=j1mzdCVI;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=none (no SPF record) smtp.mailfrom=lists.infradead.org\n (client-ip=2607:7c80:54:3::133; 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a=rsa-sha256; q=dns/txt; c=relaxed/relaxed;\n\td=lists.infradead.org; s=bombadil.20210309; h=Sender:\n\tContent-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post:\n\tList-Archive:List-Unsubscribe:List-Id:Cc:To:In-Reply-To:References:Message-Id\n\t:MIME-Version:Subject:Date:From:Reply-To:Content-ID:Content-Description:\n\tResent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:\n\tList-Owner; bh=px0K3MKifz9qyPOfH4OeaCYx/e6u3QshWUuliCQxcFs=; b=aQZAypqOjuWDjF\n\tNbW8ECvHEp4zu2WQRICzG3u8NlI6lDTMpjAc6C4arOcVRQw4TjHqMTlT4LdN6n3XlWIjmOdPWxn8z\n\teforj0iu+d3BQ7SbsZm7HmSxXnVMR1rjiq/PEBRy8k2V+i4WVMI9z/C2Z1YgJK1YSbUDUqIMpm9Zy\n\ty8SFbpu79sLl13+PykVN7bqmLuUv4pdORIA0m9iFR8YvUjLbbo0wvPiufeiDHHjzIi60HgfMxa6uD\n\tkXMQcwWmI0tmikDG0hKm8PuPQXP112irwkjLjv95tDb5qtApMWQBlPd2tSHCGjZJFGkiTDcs9c1pc\n\tjyT1nO8meVMRPBJT3rOw==;", "v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim;\n\tt=1778172438; h=from:subject:date:message-id:to:cc:mime-version:content-type:\n\t content-transfer-encoding:in-reply-to:references;\n\tbh=e6BDzr2gXG0gqoEqMqjyiWr31fY70QwF9TnwzmX2hIs=;\n\tb=j1mzdCVI4s5RarreRyOOUty0J8r8yU/f4AbT84lL2BAVrf0iazgNyB7GecQ2mQHRI5++0k\n\tjTT5rmcO0tRXCv4xULxaDW+J1Cv5yKbLjNWJ4ggyMEiDR5DcvjjoXs6bXvbgvB83sjdQbc\n\tz3FyBYTZ6fXy+k/nUcOA9wNjYq1YTf0K+Z8tyWsEFfi6vqkpXGFZebC8cyYXFi37S8l+6T\n\t+IL6eSad8p6KXDS4zaeHl92Buthfp+s5cSIIucbrTUgZ4mjeycFBt5qAVa/DnyyafrA5fQ\n\tMsmFIKZNk5sR9JP5aYhv+a1ACBc1Pt0P9iTnRVx4cSEkKRpPQaeSeMfaNjL22A==" ], "From": "Miquel Raynal <miquel.raynal@bootlin.com>", "Date": "Thu, 07 May 2026 18:46:55 +0200", "Subject": "[PATCH v5 14/28] mtd: spi-nor: swp: Create helpers for building\n the SR register", "MIME-Version": "1.0", "Message-Id": "\n <20260507-winbond-v6-18-rc1-spi-nor-swp-v5-14-93453e1a9597@bootlin.com>", "References": "\n <20260507-winbond-v6-18-rc1-spi-nor-swp-v5-0-93453e1a9597@bootlin.com>", "In-Reply-To": "\n <20260507-winbond-v6-18-rc1-spi-nor-swp-v5-0-93453e1a9597@bootlin.com>", "To": "Pratyush Yadav <pratyush@kernel.org>, Michael Walle <mwalle@kernel.org>,\n Takahiro Kuwano <takahiro.kuwano@infineon.com>,\n Richard Weinberger <richard@nod.at>, Vignesh Raghavendra <vigneshr@ti.com>,\n Jonathan Corbet <corbet@lwn.net>, Tudor Ambarus <tudor.ambarus@linaro.org>,\n Shuah Khan <skhan@linuxfoundation.org>", "Cc": "Sean Anderson <sean.anderson@linux.dev>,\n Thomas Petazzoni <thomas.petazzoni@bootlin.com>,\n Steam Lin <STLin2@winbond.com>, linux-mtd@lists.infradead.org,\n linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org,\n Miquel Raynal <miquel.raynal@bootlin.com>", "X-Mailer": "b4 0.14.3", "X-Last-TLS-Session-Version": "TLSv1.3", "X-CRM114-Version": "20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 ", "X-CRM114-CacheID": "sfid-20260507_094721_620322_E39FCB6D ", "X-CRM114-Status": "GOOD ( 14.20 )", "X-Spam-Score": "-2.1 (--)", "X-Spam-Report": "Spam detection software,\n running on the system \"bombadil.infradead.org\",\n has NOT identified this incoming email as spam. The original\n message has been attached to this so you can view it or label\n similar future email. If you have any questions, see\n the administrator of that system for details.\n Content preview: The status register contains 3 or 4 BP (Block Protect)\n bits,\n 0 or 1 TB (Top/Bottom) bit, soon 0 or 1 CMP (Complement) bit. The last BP\n bit and the TB bit locations change between vendors. The whole lo [...]\n Content analysis details: (-2.1 points, 5.0 required)\n pts rule name description\n ---- ----------------------\n --------------------------------------------------\n -0.0 SPF_HELO_PASS SPF: HELO matches SPF record\n -0.0 SPF_PASS SPF: sender matches SPF record\n -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from\n envelope-from domain\n -0.1 DKIM_VALID Message has at least one valid DKIM or DK\n signature\n -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from\n author's\n domain\n 0.1 DKIM_SIGNED Message has a DKIM or DK signature,\n not necessarily valid\n -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n [score: 0.0000]\n -0.0 DMARC_PASS DMARC pass policy", "X-BeenThere": "linux-mtd@lists.infradead.org", "X-Mailman-Version": "2.1.34", "Precedence": "list", "List-Id": "Linux MTD discussion mailing list <linux-mtd.lists.infradead.org>", "List-Unsubscribe": "<http://lists.infradead.org/mailman/options/linux-mtd>,\n <mailto:linux-mtd-request@lists.infradead.org?subject=unsubscribe>", "List-Archive": "<http://lists.infradead.org/pipermail/linux-mtd/>", "List-Post": "<mailto:linux-mtd@lists.infradead.org>", "List-Help": "<mailto:linux-mtd-request@lists.infradead.org?subject=help>", "List-Subscribe": "<http://lists.infradead.org/mailman/listinfo/linux-mtd>,\n <mailto:linux-mtd-request@lists.infradead.org?subject=subscribe>", "Content-Type": "text/plain; charset=\"us-ascii\"", "Content-Transfer-Encoding": "7bit", "Sender": "\"linux-mtd\" <linux-mtd-bounces@lists.infradead.org>", "Errors-To": "linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org" }, "content": "The status register contains 3 or 4 BP (Block Protect) bits, 0 or 1\nTB (Top/Bottom) bit, soon 0 or 1 CMP (Complement) bit. The last BP bit\nand the TB bit locations change between vendors. The whole logic of\nbuildling the content of the status register based on some input\nconditions is used two times and soon will be used 4 times.\n\nCreate dedicated helpers for these steps.\n\nSigned-off-by: Miquel Raynal <miquel.raynal@bootlin.com>\n---\n drivers/mtd/spi-nor/swp.c | 83 +++++++++++++++++++++++++++++------------------\n 1 file changed, 51 insertions(+), 32 deletions(-)", "diff": "diff --git a/drivers/mtd/spi-nor/swp.c b/drivers/mtd/spi-nor/swp.c\nindex 540cd221c455..8aa0fe297188 100644\n--- a/drivers/mtd/spi-nor/swp.c\n+++ b/drivers/mtd/spi-nor/swp.c\n@@ -125,6 +125,43 @@ static bool spi_nor_is_unlocked_sr(struct spi_nor *nor, loff_t ofs, u64 len,\n \treturn spi_nor_check_lock_status_sr(nor, ofs, len, sr, false);\n }\n \n+static int spi_nor_sr_set_bp_mask(struct spi_nor *nor, u8 *sr, u8 pow)\n+{\n+\tu8 mask = spi_nor_get_sr_bp_mask(nor);\n+\tu8 val = pow << SR_BP_SHIFT;\n+\n+\tif (nor->flags & SNOR_F_HAS_SR_BP3_BIT6 && val & SR_BP3)\n+\t\tval = (val & ~SR_BP3) | SR_BP3_BIT6;\n+\n+\tif (val & ~mask)\n+\t\treturn -EINVAL;\n+\n+\tsr[0] = val;\n+\n+\treturn 0;\n+}\n+\n+static int spi_nor_build_sr(struct spi_nor *nor, const u8 *old_sr, u8 *new_sr,\n+\t\t\t u8 pow, bool use_top)\n+{\n+\tu8 bp_mask = spi_nor_get_sr_bp_mask(nor);\n+\tu8 tb_mask = spi_nor_get_sr_tb_mask(nor);\n+\tint ret;\n+\n+\tnew_sr[0] = old_sr[0] & ~bp_mask & ~tb_mask;\n+\n+\t/* Build BP field */\n+\tret = spi_nor_sr_set_bp_mask(nor, &new_sr[0], pow);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\t/* Build TB field */\n+\tif (!use_top)\n+\t\tnew_sr[0] |= tb_mask;\n+\n+\treturn 0;\n+}\n+\n /*\n * Lock a region of the flash. Compatible with ST Micro and similar flash.\n * Supports the block protection bits BP{0,1,2}/BP{0,1,2,3} in the status\n@@ -164,11 +201,10 @@ static int spi_nor_sr_lock(struct spi_nor *nor, loff_t ofs, u64 len)\n \tint ret;\n \tu8 status_old[1] = {}, status_new[1] = {};\n \tu8 bp_mask = spi_nor_get_sr_bp_mask(nor);\n-\tu8 tb_mask = spi_nor_get_sr_tb_mask(nor);\n-\tu8 pow, val;\n \tloff_t lock_len;\n \tbool can_be_top = true, can_be_bottom = nor->flags & SNOR_F_HAS_SR_TB;\n \tbool use_top;\n+\tu8 pow;\n \n \tret = spi_nor_read_sr(nor, nor->bouncebuf);\n \tif (ret)\n@@ -202,24 +238,19 @@ static int spi_nor_sr_lock(struct spi_nor *nor, loff_t ofs, u64 len)\n \t\tlock_len = ofs + len;\n \n \tif (lock_len == nor->params->size) {\n-\t\tval = bp_mask;\n+\t\tpow = (nor->flags & SNOR_F_HAS_4BIT_BP) ? GENMASK(3, 0) : GENMASK(2, 0);\n \t} else {\n \t\tmin_prot_len = spi_nor_get_min_prot_length_sr(nor);\n \t\tpow = ilog2(lock_len) - ilog2(min_prot_len) + 1;\n-\t\tval = pow << SR_BP_SHIFT;\n-\n-\t\tif (nor->flags & SNOR_F_HAS_SR_BP3_BIT6 && val & SR_BP3)\n-\t\t\tval = (val & ~SR_BP3) | SR_BP3_BIT6;\n-\n-\t\tif (val & ~bp_mask)\n-\t\t\treturn -EINVAL;\n-\n-\t\t/* Don't \"lock\" with no region! */\n-\t\tif (!(val & bp_mask))\n-\t\t\treturn -EINVAL;\n \t}\n \n-\tstatus_new[0] = (status_old[0] & ~bp_mask & ~tb_mask) | val;\n+\tret = spi_nor_build_sr(nor, status_old, status_new, pow, use_top);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\t/* Don't \"lock\" with no region! */\n+\tif (!(status_new[0] & bp_mask))\n+\t\treturn -EINVAL;\n \n \t/*\n \t * Disallow further writes if WP# pin is neither left floating nor\n@@ -229,9 +260,6 @@ static int spi_nor_sr_lock(struct spi_nor *nor, loff_t ofs, u64 len)\n \tif (!(nor->flags & SNOR_F_NO_WP))\n \t\tstatus_new[0] |= SR_SRWD;\n \n-\tif (!use_top)\n-\t\tstatus_new[0] |= tb_mask;\n-\n \t/* Don't bother if they're the same */\n \tif (status_new[0] == status_old[0])\n \t\treturn 0;\n@@ -254,11 +282,10 @@ static int spi_nor_sr_unlock(struct spi_nor *nor, loff_t ofs, u64 len)\n \tint ret;\n \tu8 status_old[1], status_new[1];\n \tu8 bp_mask = spi_nor_get_sr_bp_mask(nor);\n-\tu8 tb_mask = spi_nor_get_sr_tb_mask(nor);\n-\tu8 pow, val;\n \tloff_t lock_len;\n \tbool can_be_top = true, can_be_bottom = nor->flags & SNOR_F_HAS_SR_TB;\n \tbool use_top;\n+\tu8 pow;\n \n \tret = spi_nor_read_sr(nor, nor->bouncebuf);\n \tif (ret)\n@@ -299,29 +326,21 @@ static int spi_nor_sr_unlock(struct spi_nor *nor, loff_t ofs, u64 len)\n \t\tlock_len = ofs;\n \n \tif (lock_len == 0) {\n-\t\tval = 0; /* fully unlocked */\n+\t\tpow = 0; /* fully unlocked */\n \t} else {\n \t\tmin_prot_len = spi_nor_get_min_prot_length_sr(nor);\n \t\tpow = ilog2(lock_len) - ilog2(min_prot_len) + 1;\n-\t\tval = pow << SR_BP_SHIFT;\n \n-\t\tif (nor->flags & SNOR_F_HAS_SR_BP3_BIT6 && val & SR_BP3)\n-\t\t\tval = (val & ~SR_BP3) | SR_BP3_BIT6;\n-\n-\t\t/* Some power-of-two sizes may not be supported */\n-\t\tif (val & ~bp_mask)\n-\t\t\treturn -EINVAL;\n \t}\n \n-\tstatus_new[0] = (status_old[0] & ~bp_mask & ~tb_mask) | val;\n+\tret = spi_nor_build_sr(nor, status_old, status_new, pow, use_top);\n+\tif (ret)\n+\t\treturn ret;\n \n \t/* Don't protect status register if we're fully unlocked */\n \tif (lock_len == 0)\n \t\tstatus_new[0] &= ~SR_SRWD;\n \n-\tif (!use_top)\n-\t\tstatus_new[0] |= tb_mask;\n-\n \t/* Don't bother if they're the same */\n \tif (status_new[0] == status_old[0])\n \t\treturn 0;\n", "prefixes": [ "v5", "14/28" ] }