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GET /api/1.2/patches/2234403/?format=api
{ "id": 2234403, "url": "http://patchwork.ozlabs.org/api/1.2/patches/2234403/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260507160959.449170-7-richard.henderson@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.2/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260507160959.449170-7-richard.henderson@linaro.org>", "list_archive_url": null, "date": "2026-05-07T16:09:54", "name": "[v3,06/11] target/s390x: Move float{32, 64}_s390_divide_to_integer", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "503908d7432abdc722e19f344aaceec5e7e98998", "submitter": { "id": 72104, "url": "http://patchwork.ozlabs.org/api/1.2/people/72104/?format=api", "name": "Richard Henderson", "email": "richard.henderson@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260507160959.449170-7-richard.henderson@linaro.org/mbox/", "series": [ { "id": 503213, "url": "http://patchwork.ozlabs.org/api/1.2/series/503213/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=503213", "date": "2026-05-07T16:09:49", "name": "fpu: Export some internals for targets", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/503213/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2234403/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2234403/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=LwJijNhF;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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a=rsa-sha256; c=relaxed/relaxed;\n d=1e100.net; s=20251104; t=1778170208; x=1778775008;\n h=content-transfer-encoding:mime-version:references:in-reply-to\n :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from\n :to:cc:subject:date:message-id:reply-to;\n bh=IjstTKJT90sH1HrKciEy2EXgN+I4s6KJIu6v2tPYbj4=;\n b=WtXK7ybRbQyw1MH5CumQHDLCXIj7YgIpaWisq4fsJM8TKQ1FBmOiAl72mbp6c1LMOk\n O7N1wRgprNhzKtl6JjXPBoiLVuVkqV0PM0Oa9iHGvUqjbAopmclTfoa556waLVlHoAVH\n g4taHUEMNGw6eowK6dTKs5hB7/qlT6SXuxZ3jQdrLXjnAwJ7bQytvy/R77/52RzMTHZh\n Zq4EYLCDVuZ1gnB6xYVhhnp/4NZPcP89cwvsulSfqE/CbZGh7zTdBXPqUzSroOKWQ3BY\n opbipQ/J2n9wSNEfPHN2JimDaV9IdW13kZubBu0ZmQYlOveifcNqjFOPAx0p2FIAII7Q\n yJ5g==", "X-Gm-Message-State": "AOJu0YzqTAvAgDVuhUyL+GZPUbczTNpNleyGUWlMLtQNzbwAVpzwn45o\n z45OgGdT+uwQ5Hri5m09RsgLSRYlY/lSSICc4dEqvllQy+ABicFxYsL1SMJoB8AS0drZBtKe23M\n nZgq8", "X-Gm-Gg": "AeBDiesH2FctrBrpZ1iCRst8nNa5OKpHKMTORIGZikoDyqMY//KelphMZzi9EZgSZdK\n UcOuu5Jg043hJbRMpiNsKy1egCz0orXUZD4KSeDDTwUQOtV8a3JUhWbLBtqHYjOJ9qdmbdAGc+V\n +8OGEFiUapkYFYdpUgF1GS/+DD6fBCdSvmLyRwokKoz10NtGgM5VYv4ZHEhyXT+cPrNoi0H1aCM\n O7UwBPPebi++1ihUKZGv30NqQM9umqC8R04apvBUKBwjSfUiqwzkOdNL/6BcwWQBNdIFq/1+JpW\n lO6i4noRqCylReNRGWiWt4AAMJqcOY8LroDUOmVIP1OgJeJd3u8hicgbtWYkfWXUunWv+8Exka+\n r4ZJbxN7a4BRnTQYbLY0RmcHIo1w2wze7Jb+0t/texM9CXgF849QgaoU2W9uZYkjbILCzDUw8jj\n rVcYmKvbVNUDp6weZtWJnAdykhWR3aIcja31eLyV0u+fsoaA==", "X-Received": "by 2002:a05:6830:6d15:b0:7d9:71e7:abe5 with SMTP id\n 46e09a7af769-7e1dee9096amr5434678a34.10.1778170207609;\n Thu, 07 May 2026 09:10:07 -0700 (PDT)", "From": "Richard Henderson <richard.henderson@linaro.org>", "To": "qemu-devel@nongnu.org", "Cc": "=?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= <philmd@linaro.org>,\n Ilya Leoshkevich <iii@linux.ibm.com>", "Subject": "[PATCH v3 06/11] target/s390x: Move float{32,\n 64}_s390_divide_to_integer", "Date": "Thu, 7 May 2026 11:09:54 -0500", "Message-ID": "<20260507160959.449170-7-richard.henderson@linaro.org>", "X-Mailer": "git-send-email 2.43.0", "In-Reply-To": "<20260507160959.449170-1-richard.henderson@linaro.org>", "References": "<20260507160959.449170-1-richard.henderson@linaro.org>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=UTF-8", "Content-Transfer-Encoding": "8bit", "Received-SPF": "pass client-ip=2607:f8b0:4864:20::32d;\n envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x32d.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "Now that we've exposed enough infrastructure, this can be\nimplemented in the backend that needs it.\n\nReviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>\nReviewed-by: Ilya Leoshkevich <iii@linux.ibm.com>\nSigned-off-by: Richard Henderson <richard.henderson@linaro.org>\n---\n include/fpu/softfloat.h | 11 ---\n fpu/softfloat.c | 137 ----------------------------------\n target/s390x/tcg/fpu_helper.c | 135 +++++++++++++++++++++++++++++++++\n 3 files changed, 135 insertions(+), 148 deletions(-)", "diff": "diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h\nindex 8389a07b04..1580d956d5 100644\n--- a/include/fpu/softfloat.h\n+++ b/include/fpu/softfloat.h\n@@ -1386,15 +1386,4 @@ static inline bool float128_unordered_quiet(float128 a, float128 b,\n *----------------------------------------------------------------------------*/\n float128 float128_default_nan(float_status *status);\n \n-#define DECLARE_S390_DIVIDE_TO_INTEGER(floatN) \\\n-void floatN ## _s390_divide_to_integer(floatN a, floatN b, \\\n- int final_quotient_rounding_mode, \\\n- bool mask_underflow, bool mask_inexact, \\\n- floatN *r, floatN *n, \\\n- uint32_t *cc, int *dxc, \\\n- float_status *status)\n-DECLARE_S390_DIVIDE_TO_INTEGER(float32);\n-DECLARE_S390_DIVIDE_TO_INTEGER(float64);\n-\n-\n #endif /* SOFTFLOAT_H */\ndiff --git a/fpu/softfloat.c b/fpu/softfloat.c\nindex cd03ace323..6a14c5d639 100644\n--- a/fpu/softfloat.c\n+++ b/fpu/softfloat.c\n@@ -5151,143 +5151,6 @@ floatx80 floatx80_round(floatx80 a, float_status *status)\n return floatx80_round_pack_canonical(&p, status);\n }\n \n-static void parts_s390_divide_to_integer(FloatParts64 *a, FloatParts64 *b,\n- int final_quotient_rounding_mode,\n- bool mask_underflow, bool mask_inexact,\n- const FloatFmt *fmt,\n- FloatParts64 *r, FloatParts64 *n,\n- uint32_t *cc, int *dxc,\n- float_status *status)\n-{\n- /* POp table \"Results: DIVIDE TO INTEGER (Part 1 of 2)\" */\n- if ((float_cmask(a->cls) | float_cmask(b->cls)) & float_cmask_anynan) {\n- *r = parts64_pick_nan(a, b, status);\n- *n = *r;\n- *cc = 1;\n- } else if (a->cls == float_class_inf || b->cls == float_class_zero) {\n- *r = parts64_default_nan(status);\n- *n = *r;\n- *cc = 1;\n- status->float_exception_flags |= float_flag_invalid;\n- } else if (b->cls == float_class_inf) {\n- *r = *a;\n- n->cls = float_class_zero;\n- n->sign = a->sign ^ b->sign;\n- *cc = 0;\n- } else {\n- FloatParts64 *q, q_buf, r_precise;\n- int float_exception_flags = 0;\n- bool is_q_smallish;\n- uint32_t r_flags;\n-\n- /* Compute precise quotient */\n- q_buf = parts64_div(a, b, status);\n- q = &q_buf;\n-\n- /*\n- * Check whether two closest integers can be precisely represented,\n- * i.e., all their bits fit into the fractional part.\n- */\n- is_q_smallish = q->exp < (fmt->frac_size + 1);\n-\n- /*\n- * Final quotient is rounded using final-quotient-rounding method, and\n- * partial quotient is rounded toward zero.\n- *\n- * Rounding of partial quotient may be inexact. This is the whole point\n- * of distinguishing partial quotients, so ignore the exception.\n- */\n- *n = parts64_round_to_int(q,\n- is_q_smallish\n- ? final_quotient_rounding_mode\n- : float_round_to_zero,\n- 0, status, fmt);\n-\n- /* Compute precise remainder */\n- r_precise = parts64_muladd(b, n, a,\n- float_muladd_negate_product, status);\n-\n- /* Round remainder to the target format */\n- *r = r_precise;\n- status->float_exception_flags = 0;\n- *r = parts64_round_to_fmt(r, status, fmt);\n- r_flags = status->float_exception_flags;\n-\n- /* POp table \"Results: DIVIDE TO INTEGER (Part 2 of 2)\" */\n- if (is_q_smallish) {\n- if (r->cls != float_class_zero) {\n- if (r->exp < 2 - (1 << (fmt->exp_size - 1))) {\n- if (mask_underflow) {\n- float_exception_flags |= float_flag_underflow;\n- *dxc = 0x10;\n- r->exp += fmt->exp_re_bias;\n- }\n- } else if (r_flags & float_flag_inexact) {\n- float_exception_flags |= float_flag_inexact;\n- if (mask_inexact) {\n- bool saved_r_sign, saved_r_precise_sign;\n-\n- /*\n- * Check whether remainder was truncated (rounded\n- * toward zero) or incremented.\n- */\n- saved_r_sign = r->sign;\n- saved_r_precise_sign = r_precise.sign;\n- r->sign = false;\n- r_precise.sign = false;\n- if (parts64_compare(r, &r_precise, status, true) <\n- float_relation_equal) {\n- *dxc = 0x8;\n- } else {\n- *dxc = 0xc;\n- }\n- r->sign = saved_r_sign;\n- r_precise.sign = saved_r_precise_sign;\n- }\n- }\n- }\n- *cc = 0;\n- } else if (n->exp > (1 << (fmt->exp_size - 1)) - 1) {\n- n->exp -= fmt->exp_re_bias;\n- *cc = r->cls == float_class_zero ? 1 : 3;\n- } else {\n- *cc = r->cls == float_class_zero ? 0 : 2;\n- }\n-\n- /* Adjust signs of zero results */\n- if (r->cls == float_class_zero) {\n- r->sign = a->sign;\n- }\n- if (n->cls == float_class_zero) {\n- n->sign = a->sign ^ b->sign;\n- }\n-\n- status->float_exception_flags = float_exception_flags;\n- }\n-}\n-\n-#define DEFINE_S390_DIVIDE_TO_INTEGER(floatN) \\\n-void floatN ## _s390_divide_to_integer(floatN a, floatN b, \\\n- int final_quotient_rounding_mode, \\\n- bool mask_underflow, bool mask_inexact, \\\n- floatN *r, floatN *n, \\\n- uint32_t *cc, int *dxc, \\\n- float_status *status) \\\n-{ \\\n- FloatParts64 pa = floatN ## _unpack_canonical(a, status); \\\n- FloatParts64 pb = floatN ## _unpack_canonical(b, status); \\\n- FloatParts64 pr, pn; \\\n- parts_s390_divide_to_integer(&pa, &pb, final_quotient_rounding_mode, \\\n- mask_underflow, mask_inexact, \\\n- &floatN ## _params, \\\n- &pr, &pn, cc, dxc, status); \\\n- *r = floatN ## _round_pack_canonical(&pr, status); \\\n- *n = floatN ## _round_pack_canonical(&pn, status); \\\n-}\n-\n-DEFINE_S390_DIVIDE_TO_INTEGER(float32)\n-DEFINE_S390_DIVIDE_TO_INTEGER(float64)\n-\n static void __attribute__((constructor)) softfloat_init(void)\n {\n union_float64 ua, ub, uc, ur;\ndiff --git a/target/s390x/tcg/fpu_helper.c b/target/s390x/tcg/fpu_helper.c\nindex 122994960a..33e0f6100d 100644\n--- a/target/s390x/tcg/fpu_helper.c\n+++ b/target/s390x/tcg/fpu_helper.c\n@@ -24,6 +24,7 @@\n #include \"tcg_s390x.h\"\n #include \"exec/helper-proto.h\"\n #include \"fpu/softfloat.h\"\n+#include \"fpu/softfloat-parts.h\"\n \n /* #define DEBUG_HELPER */\n #ifdef DEBUG_HELPER\n@@ -315,6 +316,140 @@ Int128 HELPER(dxb)(CPUS390XState *env, Int128 a, Int128 b)\n return RET128(ret);\n }\n \n+static void parts_s390_divide_to_integer(FloatParts64 *a, FloatParts64 *b,\n+ int final_quotient_rounding_mode,\n+ bool mask_underflow, bool mask_inexact,\n+ const FloatFmt *fmt,\n+ FloatParts64 *r, FloatParts64 *n,\n+ uint32_t *cc, int *dxc,\n+ float_status *status)\n+{\n+ /* POp table \"Results: DIVIDE TO INTEGER (Part 1 of 2)\" */\n+ if ((float_cmask(a->cls) | float_cmask(b->cls)) & float_cmask_anynan) {\n+ *r = parts64_pick_nan(a, b, status);\n+ *n = *r;\n+ *cc = 1;\n+ } else if (a->cls == float_class_inf || b->cls == float_class_zero) {\n+ *r = parts64_default_nan(status);\n+ *n = *r;\n+ *cc = 1;\n+ status->float_exception_flags |= float_flag_invalid;\n+ } else if (b->cls == float_class_inf) {\n+ *r = *a;\n+ n->cls = float_class_zero;\n+ n->sign = a->sign ^ b->sign;\n+ *cc = 0;\n+ } else {\n+ FloatParts64 *q, q_buf, r_precise;\n+ int float_exception_flags = 0;\n+ bool is_q_smallish;\n+ uint32_t r_flags;\n+\n+ /* Compute precise quotient */\n+ q_buf = parts64_div(a, b, status);\n+ q = &q_buf;\n+\n+ /*\n+ * Check whether two closest integers can be precisely represented,\n+ * i.e., all their bits fit into the fractional part.\n+ */\n+ is_q_smallish = q->exp < (fmt->frac_size + 1);\n+\n+ /*\n+ * Final quotient is rounded using final-quotient-rounding method, and\n+ * partial quotient is rounded toward zero.\n+ *\n+ * Rounding of partial quotient may be inexact. This is the whole point\n+ * of distinguishing partial quotients, so ignore the exception.\n+ */\n+ *n = parts64_round_to_int(q,\n+ is_q_smallish\n+ ? final_quotient_rounding_mode\n+ : float_round_to_zero,\n+ 0, status, fmt);\n+\n+ /* Compute precise remainder */\n+ r_precise = parts64_muladd(b, n, a,\n+ float_muladd_negate_product, status);\n+\n+ /* Round remainder to the target format */\n+ *r = r_precise;\n+ status->float_exception_flags = 0;\n+ *r = parts64_round_to_fmt(r, status, fmt);\n+ r_flags = status->float_exception_flags;\n+\n+ /* POp table \"Results: DIVIDE TO INTEGER (Part 2 of 2)\" */\n+ if (is_q_smallish) {\n+ if (r->cls != float_class_zero) {\n+ if (r->exp < 2 - (1 << (fmt->exp_size - 1))) {\n+ if (mask_underflow) {\n+ float_exception_flags |= float_flag_underflow;\n+ *dxc = 0x10;\n+ r->exp += fmt->exp_re_bias;\n+ }\n+ } else if (r_flags & float_flag_inexact) {\n+ float_exception_flags |= float_flag_inexact;\n+ if (mask_inexact) {\n+ bool saved_r_sign, saved_r_precise_sign;\n+\n+ /*\n+ * Check whether remainder was truncated (rounded\n+ * toward zero) or incremented.\n+ */\n+ saved_r_sign = r->sign;\n+ saved_r_precise_sign = r_precise.sign;\n+ r->sign = false;\n+ r_precise.sign = false;\n+ if (parts64_compare(r, &r_precise, status, true) <\n+ float_relation_equal) {\n+ *dxc = 0x8;\n+ } else {\n+ *dxc = 0xc;\n+ }\n+ r->sign = saved_r_sign;\n+ r_precise.sign = saved_r_precise_sign;\n+ }\n+ }\n+ }\n+ *cc = 0;\n+ } else if (n->exp > (1 << (fmt->exp_size - 1)) - 1) {\n+ n->exp -= fmt->exp_re_bias;\n+ *cc = r->cls == float_class_zero ? 1 : 3;\n+ } else {\n+ *cc = r->cls == float_class_zero ? 0 : 2;\n+ }\n+\n+ /* Adjust signs of zero results */\n+ if (r->cls == float_class_zero) {\n+ r->sign = a->sign;\n+ }\n+ if (n->cls == float_class_zero) {\n+ n->sign = a->sign ^ b->sign;\n+ }\n+\n+ status->float_exception_flags = float_exception_flags;\n+ }\n+}\n+\n+#define DEFINE_S390_DIVIDE_TO_INTEGER(floatN) \\\n+static void floatN ## _s390_divide_to_integer(floatN a, floatN b, \\\n+ int final_quotient_rounding_mode, bool mask_underflow, bool mask_inexact, \\\n+ floatN *r, floatN *n, uint32_t *cc, int *dxc, float_status *status) \\\n+{ \\\n+ FloatParts64 pa = floatN ## _unpack_canonical(a, status); \\\n+ FloatParts64 pb = floatN ## _unpack_canonical(b, status); \\\n+ FloatParts64 pr, pn; \\\n+ parts_s390_divide_to_integer(&pa, &pb, final_quotient_rounding_mode, \\\n+ mask_underflow, mask_inexact, \\\n+ &floatN ## _params, \\\n+ &pr, &pn, cc, dxc, status); \\\n+ *r = floatN ## _round_pack_canonical(&pr, status); \\\n+ *n = floatN ## _round_pack_canonical(&pn, status); \\\n+}\n+\n+DEFINE_S390_DIVIDE_TO_INTEGER(float32)\n+DEFINE_S390_DIVIDE_TO_INTEGER(float64)\n+\n void HELPER(dib)(CPUS390XState *env, uint32_t r1, uint32_t r2, uint32_t r3,\n uint32_t m4, uint32_t bits)\n {\n", "prefixes": [ "v3", "06/11" ] }