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GET /api/1.2/patches/2234314/?format=api
{ "id": 2234314, "url": "http://patchwork.ozlabs.org/api/1.2/patches/2234314/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/patch/20260507155010.23784-3-richard.ball@arm.com/", "project": { "id": 17, "url": "http://patchwork.ozlabs.org/api/1.2/projects/17/?format=api", "name": "GNU Compiler Collection", "link_name": "gcc", "list_id": "gcc-patches.gcc.gnu.org", "list_email": "gcc-patches@gcc.gnu.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260507155010.23784-3-richard.ball@arm.com>", "list_archive_url": null, "date": "2026-05-07T15:50:10", "name": "[2/2] aarch64: Add support for FEAT_CMH atomic_fetch intrinsics", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "3a7a7c13c06d92ed33052e9c3955cd978e24835f", "submitter": { "id": 84470, "url": "http://patchwork.ozlabs.org/api/1.2/people/84470/?format=api", "name": "Richard Ball", "email": "richard.ball@arm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/gcc/patch/20260507155010.23784-3-richard.ball@arm.com/mbox/", "series": [ { "id": 503209, "url": "http://patchwork.ozlabs.org/api/1.2/series/503209/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/list/?series=503209", "date": "2026-05-07T15:50:08", "name": "aarch64: Add support for FEAT_CMH", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/503209/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2234314/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2234314/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "gcc-patches@gcc.gnu.org" ], "Delivered-To": [ "patchwork-incoming@legolas.ozlabs.org", "gcc-patches@gcc.gnu.org" ], "Authentication-Results": [ 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receiver=protection.outlook.com;\n client-ip=172.205.89.229; helo=nebula.arm.com; pr=C" ], "From": "<richard.ball@arm.com>", "To": "<gcc-patches@gcc.gnu.org>", "CC": "<richard.earnshaw@arm.com>, <tamar.christina@arm.com>,\n <ktkachov@nvidia.com>, <Wilco.Dijkstra@arm.com>, <Alex.Coplan@arm.com>,\n <Alice.Carlotti@arm.com>, Richard Ball <Richard.Ball@arm.com>", "Subject": "[PATCH 2/2] aarch64: Add support for FEAT_CMH atomic_fetch intrinsics", "Date": "Thu, 7 May 2026 16:50:10 +0100", "Message-ID": "<20260507155010.23784-3-richard.ball@arm.com>", "X-Mailer": "git-send-email 2.34.1", "In-Reply-To": "<20260507155010.23784-1-richard.ball@arm.com>", "References": "<20260507155010.23784-1-richard.ball@arm.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-EOPAttributedMessage": "1", "X-MS-TrafficTypeDiagnostic": "\n DB1PEPF000509FF:EE_|PAVPR08MB9380:EE_|AMS1EPF00000042:EE_|AS8PR08MB6168:EE_", "X-MS-Office365-Filtering-Correlation-Id": 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293238d1-6513-437e-c217-08deac508d98", "X-MS-Exchange-CrossTenant-Id": "f34e5979-57d9-4aaa-ad4d-b122a662184d", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d; Ip=[4.158.2.129];\n Helo=[outbound-uk1.az.dlp.m.darktrace.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n AMS1EPF00000042.eurprd04.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-BeenThere": "gcc-patches@gcc.gnu.org", "X-Mailman-Version": "2.1.30", "Precedence": "list", "List-Id": "Gcc-patches mailing list <gcc-patches.gcc.gnu.org>", "List-Unsubscribe": "<https://gcc.gnu.org/mailman/options/gcc-patches>,\n <mailto:gcc-patches-request@gcc.gnu.org?subject=unsubscribe>", "List-Archive": "<https://gcc.gnu.org/pipermail/gcc-patches/>", "List-Post": "<mailto:gcc-patches@gcc.gnu.org>", "List-Help": "<mailto:gcc-patches-request@gcc.gnu.org?subject=help>", "List-Subscribe": "<https://gcc.gnu.org/mailman/listinfo/gcc-patches>,\n <mailto:gcc-patches-request@gcc.gnu.org?subject=subscribe>", "Errors-To": "gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org" }, "content": "From: Richard Ball <Richard.Ball@arm.com>\n\ngcc/ChangeLog:\n\n\t* config/aarch64/aarch64-builtins.cc\n\t(enum aarch64_builtins): Add new builtins.\n\t(aarch64_init_atomic_hints_builtins): Likewise.\n\t(aarch64_expand_atomic_hints_builtins_fetch): Handle Fetch intrinsics.\n\t(aarch64_general_expand_builtin): Add call for new builtins.\n\t(aarch64_resolve_overloaded_builtin_atomic_hint_fetch): Handle Fetch intrinsics.\n\t(aarch64_resolve_overloaded_builtin_general): Add new call.\n\t* config/aarch64/arm_acle.h\n\t(enum atomic_fetch): Store different Fetch types.\n\t(__arm_atomic_fetch_add_with_hint): Add new builtin.\n\t(__arm_atomic_fetch_sub_with_hint): Likewise.\n\t(__arm_atomic_fetch_and_with_hint): Likewise.\n\t(__arm_atomic_fetch_xor_with_hint): Likewise.\n\t(__arm_atomic_fetch_or_with_hint): Likewise.\n\t* config/aarch64/atomics.md\n\t(aarch64_atomic_fetch_<atomic_ldoptab><mode>_atomic_hint): New pattern for atomic_fetch.\n\t(@aarch64_atomic_hints_fetch<mode>): Likewise.\n\t* config/aarch64/iterators.md: New unspecs.\n\ngcc/testsuite/ChangeLog:\n\n\t* gcc.target/aarch64/atomic_fetch_add_with_shuh.c: New test.\n\t* gcc.target/aarch64/atomic_fetch_and_with_shuh.c: New test.\n\t* gcc.target/aarch64/atomic_fetch_or_with_shuh.c: New test.\n\t* gcc.target/aarch64/atomic_fetch_sub_with_shuh.c: New test.\n\t* gcc.target/aarch64/atomic_fetch_xor_with_shuh.c: New test.\n---\n gcc/config/aarch64/aarch64-builtins.cc | 199 ++++++++++++++++-\n gcc/config/aarch64/arm_acle.h | 39 ++++\n gcc/config/aarch64/atomics.md | 77 +++++++\n gcc/config/aarch64/iterators.md | 2 +\n .../aarch64/atomic_fetch_add_with_shuh.c | 186 ++++++++++++++++\n .../aarch64/atomic_fetch_and_with_shuh.c | 186 ++++++++++++++++\n .../aarch64/atomic_fetch_or_with_shuh.c | 186 ++++++++++++++++\n .../aarch64/atomic_fetch_sub_with_shuh.c | 208 ++++++++++++++++++\n .../aarch64/atomic_fetch_xor_with_shuh.c | 186 ++++++++++++++++\n 9 files changed, 1267 insertions(+), 2 deletions(-)\n create mode 100644 gcc/testsuite/gcc.target/aarch64/atomic_fetch_add_with_shuh.c\n create mode 100644 gcc/testsuite/gcc.target/aarch64/atomic_fetch_and_with_shuh.c\n create mode 100644 gcc/testsuite/gcc.target/aarch64/atomic_fetch_or_with_shuh.c\n create mode 100644 gcc/testsuite/gcc.target/aarch64/atomic_fetch_sub_with_shuh.c\n create mode 100644 gcc/testsuite/gcc.target/aarch64/atomic_fetch_xor_with_shuh.c", "diff": "diff --git a/gcc/config/aarch64/aarch64-builtins.cc b/gcc/config/aarch64/aarch64-builtins.cc\nindex 2a6ecddd91b..79250e5bb82 100644\n--- a/gcc/config/aarch64/aarch64-builtins.cc\n+++ b/gcc/config/aarch64/aarch64-builtins.cc\n@@ -911,6 +911,14 @@ enum aarch64_builtins\n AARCH64_BUILTIN_ATOMIC_HINTS_STORE_SF,\n AARCH64_BUILTIN_ATOMIC_HINTS_STORE_DF,\n AARCH64_BUILTIN_ATOMIC_HINTS_STORE_PTR,\n+ AARCH64_BUILTIN_ATOMIC_HINTS_FETCH,\n+ AARCH64_BUILTIN_ATOMIC_HINTS_FETCH_QI,\n+ AARCH64_BUILTIN_ATOMIC_HINTS_FETCH_HI,\n+ AARCH64_BUILTIN_ATOMIC_HINTS_FETCH_SI,\n+ AARCH64_BUILTIN_ATOMIC_HINTS_FETCH_DI,\n+ AARCH64_BUILTIN_ATOMIC_HINTS_FETCH_SF,\n+ AARCH64_BUILTIN_ATOMIC_HINTS_FETCH_DF,\n+ AARCH64_BUILTIN_ATOMIC_HINTS_FETCH_PTR,\n AARCH64_BUILTIN_MAX\n };\n \n@@ -2561,6 +2569,86 @@ aarch64_init_atomic_hints_builtins (void)\n \t\t\t\t ftype,\n \t\t\t\t AARCH64_BUILTIN_ATOMIC_HINTS_STORE_PTR);\n \n+ ftype = build_function_type_list (void_type_node, ptr_type_node,\n+\t\t\t\t void_type_node,\n+\t\t\t\t unsigned_type_node,\n+\t\t\t\t unsigned_type_node,\n+\t\t\t\t unsigned_type_node, NULL_TREE);\n+ aarch64_builtin_decls[AARCH64_BUILTIN_ATOMIC_HINTS_FETCH]\n+ = aarch64_general_add_builtin (\"__builtin_aarch64_atomic_hints_fetch\",\n+\t\t\t\t ftype,\n+\t\t\t\t AARCH64_BUILTIN_ATOMIC_HINTS_FETCH);\n+\n+ ftype = build_function_type_list (unsigned_char_type_node, ptr_type_node,\n+\t\t\t\t unsigned_char_type_node,\n+\t\t\t\t unsigned_type_node,\n+\t\t\t\t unsigned_type_node,\n+\t\t\t\t unsigned_type_node, NULL_TREE);\n+ aarch64_builtin_decls[AARCH64_BUILTIN_ATOMIC_HINTS_FETCH_QI]\n+ = aarch64_general_add_builtin (\"__builtin_aarch64_atomic_hints_fetch_qi\",\n+\t\t\t\t ftype,\n+\t\t\t\t AARCH64_BUILTIN_ATOMIC_HINTS_FETCH_QI);\n+\n+ ftype = build_function_type_list (short_unsigned_type_node, ptr_type_node,\n+\t\t\t\t short_unsigned_type_node,\n+\t\t\t\t unsigned_type_node,\n+\t\t\t\t unsigned_type_node,\n+\t\t\t\t unsigned_type_node, NULL_TREE);\n+ aarch64_builtin_decls[AARCH64_BUILTIN_ATOMIC_HINTS_FETCH_HI]\n+ = aarch64_general_add_builtin (\"__builtin_aarch64_atomic_hints_fetch_hi\",\n+\t\t\t\t ftype,\n+\t\t\t\t AARCH64_BUILTIN_ATOMIC_HINTS_FETCH_HI);\n+\n+ ftype = build_function_type_list (unsigned_type_node, ptr_type_node,\n+\t\t\t\t unsigned_type_node,\n+\t\t\t\t unsigned_type_node,\n+\t\t\t\t unsigned_type_node,\n+\t\t\t\t unsigned_type_node, NULL_TREE);\n+ aarch64_builtin_decls[AARCH64_BUILTIN_ATOMIC_HINTS_FETCH_SI]\n+ = aarch64_general_add_builtin (\"__builtin_aarch64_atomic_hints_fetch_si\",\n+\t\t\t\t ftype,\n+\t\t\t\t AARCH64_BUILTIN_ATOMIC_HINTS_FETCH_SI);\n+\n+ ftype = build_function_type_list (long_long_unsigned_type_node, ptr_type_node,\n+\t\t\t\t long_long_unsigned_type_node,\n+\t\t\t\t unsigned_type_node,\n+\t\t\t\t unsigned_type_node,\n+\t\t\t\t unsigned_type_node, NULL_TREE);\n+ aarch64_builtin_decls[AARCH64_BUILTIN_ATOMIC_HINTS_FETCH_DI]\n+ = aarch64_general_add_builtin (\"__builtin_aarch64_atomic_hints_fetch_di\",\n+\t\t\t\t ftype,\n+\t\t\t\t AARCH64_BUILTIN_ATOMIC_HINTS_FETCH_DI);\n+\n+ ftype = build_function_type_list (float_type_node, ptr_type_node,\n+\t\t\t\t float_type_node,\n+\t\t\t\t unsigned_type_node,\n+\t\t\t\t unsigned_type_node,\n+\t\t\t\t unsigned_type_node, NULL_TREE);\n+ aarch64_builtin_decls[AARCH64_BUILTIN_ATOMIC_HINTS_FETCH_SF]\n+ = aarch64_general_add_builtin (\"__builtin_aarch64_atomic_hints_fetch_sf\",\n+\t\t\t\t ftype,\n+\t\t\t\t AARCH64_BUILTIN_ATOMIC_HINTS_FETCH_SF);\n+\n+ ftype = build_function_type_list (double_type_node, ptr_type_node,\n+\t\t\t\t double_type_node,\n+\t\t\t\t unsigned_type_node,\n+\t\t\t\t unsigned_type_node,\n+\t\t\t\t unsigned_type_node, NULL_TREE);\n+ aarch64_builtin_decls[AARCH64_BUILTIN_ATOMIC_HINTS_FETCH_DF]\n+ = aarch64_general_add_builtin (\"__builtin_aarch64_atomic_hints_fetch_df\",\n+\t\t\t\t ftype,\n+\t\t\t\t AARCH64_BUILTIN_ATOMIC_HINTS_FETCH_DF);\n+\n+ ftype = build_function_type_list (ptr_type_node, ptr_type_node,\n+\t\t\t\t ptr_type_node,\n+\t\t\t\t unsigned_type_node,\n+\t\t\t\t unsigned_type_node,\n+\t\t\t\t unsigned_type_node, NULL_TREE);\n+ aarch64_builtin_decls[AARCH64_BUILTIN_ATOMIC_HINTS_FETCH_PTR]\n+ = aarch64_general_add_builtin (\"__builtin_aarch64_atomic_hints_fetch_ptr\",\n+\t\t\t\t ftype,\n+\t\t\t\t AARCH64_BUILTIN_ATOMIC_HINTS_FETCH_PTR);\n+\n }\n \n /* Initialize all builtins in the AARCH64_BUILTIN_GENERAL group. */\n@@ -4115,6 +4203,61 @@ aarch64_expand_atomic_hints_builtins (tree exp, int fcode)\n expand_insn (icode, 4, ops);\n }\n \n+static rtx\n+aarch64_expand_atomic_hints_builtins_fetch (tree exp, int fcode)\n+{\n+ machine_mode mode = TYPE_MODE (TREE_TYPE (CALL_EXPR_ARG (exp, 1)));\n+ rtx val = expand_normal (CALL_EXPR_ARG (exp, 1));\n+ rtx mem_order = expand_normal (CALL_EXPR_ARG (exp, 2));\n+ rtx hint = expand_normal (CALL_EXPR_ARG (exp, 3));\n+ rtx fetch_type = expand_normal (CALL_EXPR_ARG (exp, 4));\n+\n+ require_const_argument (exp, 3, 0, 2);\n+ require_const_argument (exp, 2, 0, 6);\n+ require_const_argument (exp, 4, 0, 6);\n+ if (seen_error ())\n+ return NULL_RTX;\n+\n+ switch (fcode)\n+ {\n+ case AARCH64_BUILTIN_ATOMIC_HINTS_FETCH_SF:\n+\t{\n+\t val = force_lowpart_subreg (SImode, val, SFmode);\n+\t mode = SImode;\n+\t break;\n+\t}\n+ case AARCH64_BUILTIN_ATOMIC_HINTS_FETCH_DF:\n+\t{\n+\t val = force_lowpart_subreg (DImode, val, DFmode);\n+\t mode = DImode;\n+\t break;\n+\t}\n+ default:\n+\t{\n+\t if (val != CONST0_RTX (mode))\n+\t val = force_reg (mode, val);\n+\t break;\n+\t}\n+ }\n+\n+ rtx addr = expand_normal (CALL_EXPR_ARG (exp, 0));\n+ addr = force_reg (Pmode, addr);\n+ rtx mem = gen_rtx_MEM (mode, addr);\n+\n+ rtx return_val = gen_reg_rtx (mode);\n+ expand_operand ops[6];\n+ enum insn_code icode;\n+ create_output_operand (&ops[0], return_val, mode);\n+ create_input_operand (&ops[1], mem, mode);\n+ create_input_operand (&ops[2], val, mode);\n+ create_input_operand (&ops[3], mem_order, SImode);\n+ create_input_operand (&ops[4], hint, SImode);\n+ create_input_operand (&ops[5], fetch_type, SImode);\n+ icode = code_for_aarch64_atomic_hints_fetch (mode);\n+ expand_insn (icode, 6, ops);\n+ return (ops[0].value);\n+}\n+\n void\n aarch64_expand_pldir_builtin (tree exp)\n {\n@@ -4627,6 +4770,15 @@ aarch64_general_expand_builtin (unsigned int fcode, tree exp, rtx target,\n case AARCH64_BUILTIN_ATOMIC_HINTS_STORE_PTR:\n aarch64_expand_atomic_hints_builtins (exp, fcode);\n return target;\n+\n+ case AARCH64_BUILTIN_ATOMIC_HINTS_FETCH_QI:\n+ case AARCH64_BUILTIN_ATOMIC_HINTS_FETCH_HI:\n+ case AARCH64_BUILTIN_ATOMIC_HINTS_FETCH_SI:\n+ case AARCH64_BUILTIN_ATOMIC_HINTS_FETCH_DI:\n+ case AARCH64_BUILTIN_ATOMIC_HINTS_FETCH_SF:\n+ case AARCH64_BUILTIN_ATOMIC_HINTS_FETCH_DF:\n+ case AARCH64_BUILTIN_ATOMIC_HINTS_FETCH_PTR:\n+ return aarch64_expand_atomic_hints_builtins_fetch (exp, fcode);\n }\n \n if (fcode >= AARCH64_SIMD_BUILTIN_BASE && fcode <= AARCH64_SIMD_BUILTIN_MAX)\n@@ -5788,7 +5940,7 @@ aarch64_resolve_overloaded_memtag (location_t loc,\n }\n \n static tree\n-aarch64_resolve_overloaded_builtin_atomic_hints (void *pass_params)\n+aarch64_resolve_overloaded_builtin_atomic_hint_store (void *pass_params)\n {\n vec<tree, va_gc> *params = static_cast<vec<tree, va_gc> *> (pass_params);\n \n@@ -5827,6 +5979,46 @@ aarch64_resolve_overloaded_builtin_atomic_hints (void *pass_params)\n }\n }\n \n+static tree\n+aarch64_resolve_overloaded_builtin_atomic_hint_fetch (void *pass_params)\n+{\n+ vec<tree, va_gc> *params = static_cast<vec<tree, va_gc> *> (pass_params);\n+\n+ tree addr = (*params)[0];\n+ tree val = (*params)[1];\n+ addr = tree_strip_nop_conversions (addr);\n+ val = tree_strip_nop_conversions (val);\n+\n+ tree addr_type = TREE_TYPE (addr);\n+ if (!POINTER_TYPE_P (addr_type))\n+ return NULL_TREE;\n+\n+ tree ptr_type = TYPE_MAIN_VARIANT (TREE_TYPE (addr_type));\n+\n+ if (vec_safe_length (params) != 5)\n+ return NULL_TREE;\n+ if (POINTER_TYPE_P (ptr_type))\n+ return aarch64_builtin_decls[AARCH64_BUILTIN_ATOMIC_HINTS_FETCH_PTR];\n+\n+ switch (TYPE_MODE (ptr_type))\n+ {\n+ case QImode:\n+ return aarch64_builtin_decls[AARCH64_BUILTIN_ATOMIC_HINTS_FETCH_QI];\n+ case HImode:\n+ return aarch64_builtin_decls[AARCH64_BUILTIN_ATOMIC_HINTS_FETCH_HI];\n+ case SImode:\n+ return aarch64_builtin_decls[AARCH64_BUILTIN_ATOMIC_HINTS_FETCH_SI];\n+ case DImode:\n+ return aarch64_builtin_decls[AARCH64_BUILTIN_ATOMIC_HINTS_FETCH_DI];\n+ case SFmode:\n+ return aarch64_builtin_decls[AARCH64_BUILTIN_ATOMIC_HINTS_FETCH_SF];\n+ case DFmode:\n+ return aarch64_builtin_decls[AARCH64_BUILTIN_ATOMIC_HINTS_FETCH_DF];\n+ default:\n+ return NULL_TREE;\n+ }\n+}\n+\n /* Called at aarch64_resolve_overloaded_builtin in aarch64-c.cc. */\n tree\n aarch64_resolve_overloaded_builtin_general (location_t loc, tree function,\n@@ -5839,7 +6031,10 @@ aarch64_resolve_overloaded_builtin_general (location_t loc, tree function,\n return aarch64_resolve_overloaded_memtag(loc, function, pass_params);\n \n if (fcode == AARCH64_BUILTIN_ATOMIC_HINTS_STORE)\n- return aarch64_resolve_overloaded_builtin_atomic_hints (pass_params);\n+ return aarch64_resolve_overloaded_builtin_atomic_hint_store (pass_params);\n+\n+ if (fcode == AARCH64_BUILTIN_ATOMIC_HINTS_FETCH)\n+ return aarch64_resolve_overloaded_builtin_atomic_hint_fetch (pass_params);\n \n return NULL_TREE;\n }\ndiff --git a/gcc/config/aarch64/arm_acle.h b/gcc/config/aarch64/arm_acle.h\nindex 9317f1d2371..84ba62e3318 100644\n--- a/gcc/config/aarch64/arm_acle.h\n+++ b/gcc/config/aarch64/arm_acle.h\n@@ -46,6 +46,15 @@ NAME (TYPE __value, uint32_t __rotate)\t\t\t\t\t \\\n return __value >> __rotate | __value << ((__size - __rotate) % __size); \\\n }\n \n+enum atomic_fetch\n+{\n+ FETCH_ADD,\n+ FETCH_SUB,\n+ FETCH_AND,\n+ FETCH_XOR,\n+ FETCH_OR,\n+};\n+\n _GCC_ARM_ACLE_ROR_FN (__ror, uint32_t)\n _GCC_ARM_ACLE_ROR_FN (__rorl, unsigned long)\n _GCC_ARM_ACLE_ROR_FN (__rorll, uint64_t)\n@@ -106,6 +115,36 @@ __sqrtf (float __x)\n __builtin_aarch64_atomic_hints_store ((__addr), (__value), \\\n \t\t\t\t\t (__memory_order), (__hint))\n \n+#define __arm_atomic_fetch_add_with_hint(__addr, __value, __memory_order, \\\n+\t\t\t\t\t __hint) \\\n+ __builtin_aarch64_atomic_hints_fetch ((__addr), (__value), \\\n+\t\t\t\t\t(__memory_order), (__hint), \\\n+\t\t\t\t\t(FETCH_ADD))\n+\n+#define __arm_atomic_fetch_sub_with_hint(__addr, __value, __memory_order, \\\n+\t\t\t\t\t __hint) \\\n+ __builtin_aarch64_atomic_hints_fetch ((__addr), (__value), \\\n+\t\t\t\t\t(__memory_order), (__hint), \\\n+\t\t\t\t\t(FETCH_SUB))\n+\n+#define __arm_atomic_fetch_and_with_hint(__addr, __value, __memory_order, \\\n+\t\t\t\t\t __hint) \\\n+ __builtin_aarch64_atomic_hints_fetch ((__addr), (__value), \\\n+\t\t\t\t\t(__memory_order), (__hint), \\\n+\t\t\t\t\t(FETCH_AND))\n+\n+#define __arm_atomic_fetch_xor_with_hint(__addr, __value, __memory_order, \\\n+\t\t\t\t\t __hint) \\\n+ __builtin_aarch64_atomic_hints_fetch ((__addr), (__value), \\\n+\t\t\t\t\t(__memory_order), (__hint), \\\n+\t\t\t\t\t(FETCH_XOR))\n+\n+#define __arm_atomic_fetch_or_with_hint(__addr, __value, __memory_order, \\\n+\t\t\t\t\t __hint) \\\n+ __builtin_aarch64_atomic_hints_fetch ((__addr), (__value), \\\n+\t\t\t\t\t(__memory_order), (__hint), \\\n+\t\t\t\t\t(FETCH_OR))\n+\n #pragma GCC push_options\n #pragma GCC target (\"+nothing+jscvt\")\n __extension__ extern __inline int32_t\ndiff --git a/gcc/config/aarch64/atomics.md b/gcc/config/aarch64/atomics.md\nindex b86dae31dc1..eb985fd8e2d 100644\n--- a/gcc/config/aarch64/atomics.md\n+++ b/gcc/config/aarch64/atomics.md\n@@ -791,6 +791,83 @@\n [(set_attr \"arch\" \"*,rcpc8_4\")]\n )\n \n+(define_insn \"aarch64_atomic_fetch_<atomic_ldoptab><mode>_atomic_hint\"\n+ [(set (match_operand:ALLI 0 \"register_operand\" \"=r\")\n+\t(match_operand:ALLI 1 \"aarch64_sync_memory_operand\" \"+Q\"))\n+ (set (match_dup 1)\n+\t(unspec_volatile:ALLI\n+\t [(match_dup 1)\n+\t (match_operand:ALLI 2 \"register_operand\" \"r\")\n+\t (match_operand:SI 3 \"const_int_operand\")\n+\t (match_operand:SI 4 \"const_int_operand\")]\n+\t ATOMIC_LDOP))]\n+ \"TARGET_LSE\"\n+ {\n+ switch (INTVAL (operands[4]))\n+ {\n+ case 0:\n+\toutput_asm_insn (\"shuh\", operands);\n+\tbreak;\n+ case 1:\n+\toutput_asm_insn (\"shuh\\tph\", operands);\n+\tbreak;\n+ default:\n+\tgcc_unreachable ();\n+ }\n+ enum memmodel model = memmodel_from_int (INTVAL (operands[3]));\n+ if (is_mm_relaxed (model))\n+ return \"ld<atomic_ldop><atomic_sfx>\\t%<w>2, %<w>0, %1\";\n+ else if (is_mm_acquire (model) || is_mm_consume (model))\n+ return \"ld<atomic_ldop>a<atomic_sfx>\\t%<w>2, %<w>0, %1\";\n+ else if (is_mm_release (model))\n+ return \"ld<atomic_ldop>l<atomic_sfx>\\t%<w>2, %<w>0, %1\";\n+ else\n+ return \"ld<atomic_ldop>al<atomic_sfx>\\t%<w>2, %<w>0, %1\";\n+ }\n+)\n+\n+(define_expand \"@aarch64_atomic_hints_fetch<mode>\"\n+[(set (match_operand:ALLI 0 \"register_operand\")\n+\t(unspec_volatile:ALLI\n+\t [(match_operand:ALLI 1 \"aarch64_sync_memory_operand\")\n+\t (match_operand:ALLI 2 \"aarch64_reg_or_zero\")\n+\t (match_operand:SI 3 \"const_int_operand\") ;; model\n+\t (match_operand:SI 4 \"const_int_operand\") ;; hint\n+\t (match_operand:SI 5 \"const_int_operand\")] ;; fetch_type\n+\t UNSPECV_ATOMIC_HINTS_FETCH))]\n+ \"TARGET_LSE\"\n+ {\n+ rtx (*gen) (rtx, rtx, rtx, rtx, rtx);\n+ switch (INTVAL (operands[5]))\n+ {\n+ case 1:\n+\toperands[2] = expand_simple_unop (<MODE>mode, NEG, operands[2],\n+\t\t\t\t\t NULL, 1);\n+\t/* fallthrough. */\n+ case 0:\n+\tgen = gen_aarch64_atomic_fetch_add<mode>_atomic_hint;\n+\tbreak;\n+ case 2:\n+\toperands[2] = expand_simple_unop (<MODE>mode, NOT, operands[2],\n+\t\t\t\t\t NULL, 1);\n+\tgen = gen_aarch64_atomic_fetch_bic<mode>_atomic_hint;\n+\tbreak;\n+ case 3:\n+\tgen = gen_aarch64_atomic_fetch_xor<mode>_atomic_hint;\n+\tbreak;\n+ case 4:\n+\tgen = gen_aarch64_atomic_fetch_ior<mode>_atomic_hint;\n+\tbreak;\n+ default:\n+\tgcc_unreachable ();\n+ }\n+ operands[2] = force_reg (<MODE>mode, operands[2]);\n+ emit_insn (gen (operands[0], operands[1], operands[2], operands[3],\n+\t\t operands[4]));\n+ DONE;\n+ }\n+)\n+\n (define_insn \"@aarch64_load_exclusive<mode>\"\n [(set (match_operand:SI 0 \"register_operand\" \"=r\")\n (zero_extend:SI\ndiff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md\nindex df61f9b4f53..5fae26fb2b7 100644\n--- a/gcc/config/aarch64/iterators.md\n+++ b/gcc/config/aarch64/iterators.md\n@@ -1357,6 +1357,8 @@\n UNSPECV_LDAP\t\t; Represent an atomic acquire load with RCpc semantics.\n UNSPECV_STL\t\t\t; Represent an atomic store or store-release.\n UNSPECV_ATOMIC_HINTS_STORE\t; Represent an atomic store with a hint.\n+ UNSPECV_ATOMIC_HINTS_FETCH\t; Represent an atomic fetch with a hint.\n+ UNSPECV_HINTS_FETCH\t\t; Likewise.\n UNSPECV_ATOMIC_CMPSW\t; Represent an atomic compare swap.\n UNSPECV_ATOMIC_EXCHG\t; Represent an atomic exchange.\n UNSPECV_ATOMIC_CAS\t\t; Represent an atomic CAS.\ndiff --git a/gcc/testsuite/gcc.target/aarch64/atomic_fetch_add_with_shuh.c b/gcc/testsuite/gcc.target/aarch64/atomic_fetch_add_with_shuh.c\nnew file mode 100644\nindex 00000000000..32b23422fd8\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/aarch64/atomic_fetch_add_with_shuh.c\n@@ -0,0 +1,186 @@\n+/* { dg-do compile } */\n+/* { dg-options \"-O2 -march=armv8.1-a -save-temps\" } */\n+/* { dg-final { check-function-bodies \"**\" \"\" } } */\n+\n+#include <arm_acle.h>\n+\n+/*\n+** testFun1:\n+** ...\n+**\tshuh\n+**\tldaddb\t(w[0-9]+), \\1, \\[x[0-9]+\\]\n+** ...\n+*/\n+char\n+testFun1 ()\n+{\n+ char item1 = 0;\n+ char* ptr1 = &item1;\n+ char test1 = 1;\n+\n+ return __arm_atomic_fetch_add_with_hint (ptr1, test1, __ATOMIC_RELAXED, 0);\n+}\n+\n+/*\n+** testFun2:\n+** ...\n+**\tshuh\n+**\tldaddlh\t(w[0-9]+), \\1, \\[x[0-9]+\\]\n+** ...\n+*/\n+short\n+testFun2 ()\n+{\n+ short item2 = 10;\n+ short* ptr2 = &item2;\n+ short test2 = 11;\n+ return __arm_atomic_fetch_add_with_hint (ptr2, test2, __ATOMIC_RELEASE, 0);\n+}\n+\n+/*\n+** testFun3:\n+** ...\n+**\tshuh\tph\n+**\tldaddal\t(w[0-9]+), \\1, \\[x[0-9]+\\]\n+** ...\n+*/\n+int\n+testFun3 ()\n+{\n+ unsigned int item3 = 10;\n+ unsigned int* ptr3 = &item3;\n+ unsigned int test3 = 11;\n+ return __arm_atomic_fetch_add_with_hint (ptr3, test3, __ATOMIC_SEQ_CST, 1);\n+}\n+\n+/*\n+** testFun4:\n+** ...\n+**\tshuh\tph\n+**\tldadd\t(x[0-9]+), \\1, \\[x[0-9]+\\]\n+** ...\n+*/\n+void\n+testFun4 ()\n+{\n+ long item4 = 10;\n+ long* ptr4 = &item4;\n+ long test4 = 11;\n+ __arm_atomic_fetch_add_with_hint (ptr4, test4, __ATOMIC_RELAXED, 1);\n+}\n+\n+/*\n+** testFun5:\n+** ...\n+**\tshuh\n+**\tldaddal\t(x[0-9]+), \\1, \\[x[0-9]+\\]\n+** ...\n+*/\n+void\n+testFun5 ()\n+{\n+ long item5 = 10;\n+ long *ptritem = &item5;\n+ long **ptr5 = &ptritem;\n+ long test5item = 11;\n+ long *test5 = &test5item;\n+ __arm_atomic_fetch_add_with_hint (ptr5, test5, __ATOMIC_SEQ_CST, 0);\n+}\n+\n+/*\n+** testFun6:\n+** ...\n+**\tshuh\n+**\tldaddal\t(w[0-9]+), \\1, \\[x[0-9]+\\]\n+** ...\n+*/\n+void\n+testFun6 ()\n+{\n+ float item6 = 10;\n+ float* ptr6 = &item6;\n+ float test6 = 11;\n+ __arm_atomic_fetch_add_with_hint (ptr6, test6, __ATOMIC_SEQ_CST, 0);\n+}\n+\n+/*\n+** testFun7:\n+** ...\n+**\tshuh\tph\n+**\tldadd\t(x[0-9]+), \\1, \\[x[0-9]+\\]\n+** ...\n+*/\n+void\n+testFun7 ()\n+{\n+ double item7 = 10;\n+ double* ptr7 = &item7;\n+ double test7 = 11;\n+ __arm_atomic_fetch_add_with_hint (ptr7, test7, __ATOMIC_RELAXED, 1);\n+}\n+\n+/*\n+** testFun8:\n+** ...\n+**\tshuh\n+**\tldaddb\t(w[0-9]+), \\1, \\[x[0-9]+\\]\n+** ...\n+*/\n+void\n+testFun8 ()\n+{\n+ char item8 = 0;\n+ char* ptr8 = &item8;\n+ long test8 = 1;\n+\n+ __arm_atomic_fetch_add_with_hint (ptr8, test8, __ATOMIC_RELAXED, 0);\n+}\n+\n+/*\n+** testFun9:\n+** ...\n+**\tshuh\tph\n+**\tldadd\t(w[0-9]+), \\1, \\[x[0-9]+\\]\n+** ...\n+*/\n+void\n+testFun9 ()\n+{\n+ int item9 = 0;\n+ int* ptr9 = &item9;\n+ float test9 = 1;\n+\n+ __arm_atomic_fetch_add_with_hint (ptr9, test9, __ATOMIC_RELAXED, 1);\n+}\n+\n+/*\n+** testFun10:\n+** ...\n+**\tadd\t(x[0-9]+), \\1, 1\n+**\tmov\t(w[0-9]+), 7\n+**\tshuh\tph\n+**\tldaddb\t\\2, \\2, \\[x[0-9]+\\]\n+** ...\n+*/\n+static char buf[8];\n+void\n+testFun10 (void)\n+{\n+ __arm_atomic_fetch_add_with_hint((buf + 1), (char)7, __ATOMIC_RELAXED, 1);\n+}\n+\n+/*\n+** testFun11:\n+** ...\n+**\tshuh\tph\n+**\tldadd\t(w[0-9]+), \\1, \\[x[0-9]+\\]\n+** ...\n+*/\n+void\n+testFun11 ()\n+{\n+ int item11 = 10;\n+ int* ptr11 = &item11;\n+\n+ __arm_atomic_fetch_add_with_hint (ptr11, 0, __ATOMIC_RELAXED, 1);\n+}\ndiff --git a/gcc/testsuite/gcc.target/aarch64/atomic_fetch_and_with_shuh.c b/gcc/testsuite/gcc.target/aarch64/atomic_fetch_and_with_shuh.c\nnew file mode 100644\nindex 00000000000..7ba3dd2c2fd\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/aarch64/atomic_fetch_and_with_shuh.c\n@@ -0,0 +1,186 @@\n+/* { dg-do compile } */\n+/* { dg-options \"-O2 -march=armv8.1-a -save-temps\" } */\n+/* { dg-final { check-function-bodies \"**\" \"\" } } */\n+\n+#include <arm_acle.h>\n+\n+/*\n+** testFun1:\n+** ...\n+**\tshuh\n+**\tldclrb\t(w[0-9]+), \\1, \\[x[0-9]+\\]\n+** ...\n+*/\n+char\n+testFun1 ()\n+{\n+ char item1 = 0;\n+ char* ptr1 = &item1;\n+ char test1 = 1;\n+\n+ return __arm_atomic_fetch_and_with_hint (ptr1, test1, __ATOMIC_RELAXED, 0);\n+}\n+\n+/*\n+** testFun2:\n+** ...\n+**\tshuh\n+**\tldclrlh\t(w[0-9]+), \\1, \\[x[0-9]+\\]\n+** ...\n+*/\n+short\n+testFun2 ()\n+{\n+ short item2 = 10;\n+ short* ptr2 = &item2;\n+ short test2 = 11;\n+ return __arm_atomic_fetch_and_with_hint (ptr2, test2, __ATOMIC_RELEASE, 0);\n+}\n+\n+/*\n+** testFun3:\n+** ...\n+**\tshuh\tph\n+**\tldclral\t(w[0-9]+), \\1, \\[x[0-9]+\\]\n+** ...\n+*/\n+int\n+testFun3 ()\n+{\n+ unsigned int item3 = 10;\n+ unsigned int* ptr3 = &item3;\n+ unsigned int test3 = 11;\n+ return __arm_atomic_fetch_and_with_hint (ptr3, test3, __ATOMIC_SEQ_CST, 1);\n+}\n+\n+/*\n+** testFun4:\n+** ...\n+**\tshuh\tph\n+**\tldclr\t(x[0-9]+), \\1, \\[x[0-9]+\\]\n+** ...\n+*/\n+void\n+testFun4 ()\n+{\n+ long item4 = 10;\n+ long* ptr4 = &item4;\n+ long test4 = 11;\n+ __arm_atomic_fetch_and_with_hint (ptr4, test4, __ATOMIC_RELAXED, 1);\n+}\n+\n+/*\n+** testFun5:\n+** ...\n+**\tshuh\n+**\tldclral\t(x[0-9]+), \\1, \\[x[0-9]+\\]\n+** ...\n+*/\n+void\n+testFun5 ()\n+{\n+ long item5 = 10;\n+ long *ptritem = &item5;\n+ long **ptr5 = &ptritem;\n+ long test5item = 11;\n+ long *test5 = &test5item;\n+ __arm_atomic_fetch_and_with_hint (ptr5, test5, __ATOMIC_SEQ_CST, 0);\n+}\n+\n+/*\n+** testFun6:\n+** ...\n+**\tshuh\n+**\tldclral\t(w[0-9]+), \\1, \\[x[0-9]+\\]\n+** ...\n+*/\n+void\n+testFun6 ()\n+{\n+ float item6 = 10;\n+ float* ptr6 = &item6;\n+ float test6 = 11;\n+ __arm_atomic_fetch_and_with_hint (ptr6, test6, __ATOMIC_SEQ_CST, 0);\n+}\n+\n+/*\n+** testFun7:\n+** ...\n+**\tshuh\tph\n+**\tldclr\t(x[0-9]+), \\1, \\[x[0-9]+\\]\n+** ...\n+*/\n+void\n+testFun7 ()\n+{\n+ double item7 = 10;\n+ double* ptr7 = &item7;\n+ double test7 = 11;\n+ __arm_atomic_fetch_and_with_hint (ptr7, test7, __ATOMIC_RELAXED, 1);\n+}\n+\n+/*\n+** testFun8:\n+** ...\n+**\tshuh\n+**\tldclrb\t(w[0-9]+), \\1, \\[x[0-9]+\\]\n+** ...\n+*/\n+void\n+testFun8 ()\n+{\n+ char item8 = 0;\n+ char* ptr8 = &item8;\n+ long test8 = 1;\n+\n+ __arm_atomic_fetch_and_with_hint (ptr8, test8, __ATOMIC_RELAXED, 0);\n+}\n+\n+/*\n+** testFun9:\n+** ...\n+**\tshuh\tph\n+**\tldclr\t(w[0-9]+), \\1, \\[x[0-9]+\\]\n+** ...\n+*/\n+void\n+testFun9 ()\n+{\n+ int item9 = 0;\n+ int* ptr9 = &item9;\n+ float test9 = 1;\n+\n+ __arm_atomic_fetch_and_with_hint (ptr9, test9, __ATOMIC_RELAXED, 1);\n+}\n+\n+/*\n+** testFun10:\n+** ...\n+**\tadd\t(x[0-9]+), \\1, 1\n+**\tmov\t(w[0-9]+), -8\n+**\tshuh\tph\n+**\tldclrb\t\\2, \\2, \\[x[0-9]+\\]\n+** ...\n+*/\n+static char buf[8];\n+void\n+testFun10 (void)\n+{\n+ __arm_atomic_fetch_and_with_hint((buf + 1), (char)7, __ATOMIC_RELAXED, 1);\n+}\n+\n+/*\n+** testFun11:\n+** ...\n+**\tshuh\tph\n+**\tldclr\t(w[0-9]+), \\1, \\[x[0-9]+\\]\n+** ...\n+*/\n+void\n+testFun11 ()\n+{\n+ int item11 = 10;\n+ int* ptr11 = &item11;\n+\n+ __arm_atomic_fetch_and_with_hint (ptr11, 0, __ATOMIC_RELAXED, 1);\n+}\ndiff --git a/gcc/testsuite/gcc.target/aarch64/atomic_fetch_or_with_shuh.c b/gcc/testsuite/gcc.target/aarch64/atomic_fetch_or_with_shuh.c\nnew file mode 100644\nindex 00000000000..818f40f904c\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/aarch64/atomic_fetch_or_with_shuh.c\n@@ -0,0 +1,186 @@\n+/* { dg-do compile } */\n+/* { dg-options \"-O2 -march=armv8.1-a -save-temps\" } */\n+/* { dg-final { check-function-bodies \"**\" \"\" } } */\n+\n+#include <arm_acle.h>\n+\n+/*\n+** testFun1:\n+** ...\n+**\tshuh\n+**\tldsetb\t(w[0-9]+), \\1, \\[x[0-9]+\\]\n+** ...\n+*/\n+char\n+testFun1 ()\n+{\n+ char item1 = 0;\n+ char* ptr1 = &item1;\n+ char test1 = 1;\n+\n+ return __arm_atomic_fetch_or_with_hint (ptr1, test1, __ATOMIC_RELAXED, 0);\n+}\n+\n+/*\n+** testFun2:\n+** ...\n+**\tshuh\n+**\tldsetlh\t(w[0-9]+), \\1, \\[x[0-9]+\\]\n+** ...\n+*/\n+short\n+testFun2 ()\n+{\n+ short item2 = 10;\n+ short* ptr2 = &item2;\n+ short test2 = 11;\n+ return __arm_atomic_fetch_or_with_hint (ptr2, test2, __ATOMIC_RELEASE, 0);\n+}\n+\n+/*\n+** testFun3:\n+** ...\n+**\tshuh\tph\n+**\tldsetal\t(w[0-9]+), \\1, \\[x[0-9]+\\]\n+** ...\n+*/\n+int\n+testFun3 ()\n+{\n+ unsigned int item3 = 10;\n+ unsigned int* ptr3 = &item3;\n+ unsigned int test3 = 11;\n+ return __arm_atomic_fetch_or_with_hint (ptr3, test3, __ATOMIC_SEQ_CST, 1);\n+}\n+\n+/*\n+** testFun4:\n+** ...\n+**\tshuh\tph\n+**\tldset\t(x[0-9]+), \\1, \\[x[0-9]+\\]\n+** ...\n+*/\n+void\n+testFun4 ()\n+{\n+ long item4 = 10;\n+ long* ptr4 = &item4;\n+ long test4 = 11;\n+ __arm_atomic_fetch_or_with_hint (ptr4, test4, __ATOMIC_RELAXED, 1);\n+}\n+\n+/*\n+** testFun5:\n+** ...\n+**\tshuh\n+**\tldsetal\t(x[0-9]+), \\1, \\[x[0-9]+\\]\n+** ...\n+*/\n+void\n+testFun5 ()\n+{\n+ long item5 = 10;\n+ long *ptritem = &item5;\n+ long **ptr5 = &ptritem;\n+ long test5item = 11;\n+ long *test5 = &test5item;\n+ __arm_atomic_fetch_or_with_hint (ptr5, test5, __ATOMIC_SEQ_CST, 0);\n+}\n+\n+/*\n+** testFun6:\n+** ...\n+**\tshuh\n+**\tldsetal\t(w[0-9]+), \\1, \\[x[0-9]+\\]\n+** ...\n+*/\n+void\n+testFun6 ()\n+{\n+ float item6 = 10;\n+ float* ptr6 = &item6;\n+ float test6 = 11;\n+ __arm_atomic_fetch_or_with_hint (ptr6, test6, __ATOMIC_SEQ_CST, 0);\n+}\n+\n+/*\n+** testFun7:\n+** ...\n+**\tshuh\tph\n+**\tldset\t(x[0-9]+), \\1, \\[x[0-9]+\\]\n+** ...\n+*/\n+void\n+testFun7 ()\n+{\n+ double item7 = 10;\n+ double* ptr7 = &item7;\n+ double test7 = 11;\n+ __arm_atomic_fetch_or_with_hint (ptr7, test7, __ATOMIC_RELAXED, 1);\n+}\n+\n+/*\n+** testFun8:\n+** ...\n+**\tshuh\n+**\tldsetb\t(w[0-9]+), \\1, \\[x[0-9]+\\]\n+** ...\n+*/\n+void\n+testFun8 ()\n+{\n+ char item8 = 0;\n+ char* ptr8 = &item8;\n+ long test8 = 1;\n+\n+ __arm_atomic_fetch_or_with_hint (ptr8, test8, __ATOMIC_RELAXED, 0);\n+}\n+\n+/*\n+** testFun9:\n+** ...\n+**\tshuh\tph\n+**\tldset\t(w[0-9]+), \\1, \\[x[0-9]+\\]\n+** ...\n+*/\n+void\n+testFun9 ()\n+{\n+ int item9 = 0;\n+ int* ptr9 = &item9;\n+ float test9 = 1;\n+\n+ __arm_atomic_fetch_or_with_hint (ptr9, test9, __ATOMIC_RELAXED, 1);\n+}\n+\n+/*\n+** testFun10:\n+** ...\n+**\tadd\t(x[0-9]+), \\1, 1\n+**\tmov\t(w[0-9]+), 7\n+**\tshuh\tph\n+**\tldsetb\t\\2, \\2, \\[x[0-9]+\\]\n+** ...\n+*/\n+static char buf[8];\n+void\n+testFun10 (void)\n+{\n+ __arm_atomic_fetch_or_with_hint((buf + 1), (char)7, __ATOMIC_RELAXED, 1);\n+}\n+\n+/*\n+** testFun11:\n+** ...\n+**\tshuh\tph\n+**\tldset\t(w[0-9]+), \\1, \\[x[0-9]+\\]\n+** ...\n+*/\n+void\n+testFun11 ()\n+{\n+ int item11 = 10;\n+ int* ptr11 = &item11;\n+\n+ __arm_atomic_fetch_or_with_hint (ptr11, 0, __ATOMIC_RELAXED, 1);\n+}\ndiff --git a/gcc/testsuite/gcc.target/aarch64/atomic_fetch_sub_with_shuh.c b/gcc/testsuite/gcc.target/aarch64/atomic_fetch_sub_with_shuh.c\nnew file mode 100644\nindex 00000000000..47dcfceaea6\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/aarch64/atomic_fetch_sub_with_shuh.c\n@@ -0,0 +1,208 @@\n+/* { dg-do compile } */\n+/* { dg-options \"-O2 -march=armv8.1-a -save-temps\" } */\n+/* { dg-final { check-function-bodies \"**\" \"\" } } */\n+\n+#include <arm_acle.h>\n+\n+/*\n+** testFun1:\n+** ...\n+**\tmov\t(w[0-9]+), -1\n+**\tadd\t(x[0-9]+), sp, 15\n+**\tstrb\twzr, \\[sp, 15\\]\n+**\tshuh\n+**\tldaddb\t\\1, \\1, \\[\\2\\]\n+** ...\n+*/\n+char\n+testFun1 ()\n+{\n+ char item1 = 0;\n+ char* ptr1 = &item1;\n+ char test1 = 1;\n+\n+ return __arm_atomic_fetch_sub_with_hint (ptr1, test1, __ATOMIC_RELAXED, 0);\n+}\n+\n+/*\n+** testFun2:\n+** ...\n+**\tmov\t(w[0-9]+), -11\n+**\tshuh\n+**\tldaddlh\t(w[0-9]+), \\1, \\[x[0-9]+\\]\n+** ...\n+*/\n+short\n+testFun2 ()\n+{\n+ short item2 = 10;\n+ short* ptr2 = &item2;\n+ short test2 = 11;\n+ return __arm_atomic_fetch_sub_with_hint (ptr2, test2, __ATOMIC_RELEASE, 0);\n+}\n+\n+/*\n+** testFun3:\n+** ...\n+**\tmov\t(w[0-9]+), -11\n+**\tshuh\tph\n+**\tldaddal\t(w[0-9]+), \\1, \\[x[0-9]+\\]\n+** ...\n+*/\n+int\n+testFun3 ()\n+{\n+ unsigned int item3 = 10;\n+ unsigned int* ptr3 = &item3;\n+ unsigned int test3 = 11;\n+ return __arm_atomic_fetch_sub_with_hint (ptr3, test3, __ATOMIC_SEQ_CST, 1);\n+}\n+\n+/*\n+** testFun4:\n+** ...\n+**\tmov\t(x[0-9]+), -11\n+**\tstr\t(x[0-9]+), \\[sp, 8\\]\n+**\tadd\t\\2, sp, 8\n+**\tshuh\tph\n+**\tldadd\t\\1, \\1, \\[\\2\\]\n+** ...\n+*/\n+void\n+testFun4 ()\n+{\n+ long item4 = 10;\n+ long* ptr4 = &item4;\n+ long test4 = 11;\n+ __arm_atomic_fetch_sub_with_hint (ptr4, test4, __ATOMIC_RELAXED, 1);\n+}\n+\n+/*\n+** testFun5:\n+** ...\n+**\tneg\t(x[0-9]+), \\1\n+**\tshuh\n+**\tldaddal\t\\1, \\1, \\[x[0-9]+\\]\n+** ...\n+*/\n+void\n+testFun5 ()\n+{\n+ long item5 = 10;\n+ long *ptritem = &item5;\n+ long **ptr5 = &ptritem;\n+ long test5item = 11;\n+ long *test5 = &test5item;\n+ __arm_atomic_fetch_sub_with_hint (ptr5, test5, __ATOMIC_SEQ_CST, 0);\n+}\n+\n+/*\n+** testFun6:\n+** ...\n+**\tmov\t(w[0-9]+), -1093664768\n+**\tstr\ts31, \\[sp, 12\\]\n+**\tshuh\n+**\tldaddal\t\\1, \\1, \\[x[0-9]+\\]\n+** ...\n+*/\n+void\n+testFun6 ()\n+{\n+ float item6 = 10;\n+ float* ptr6 = &item6;\n+ float test6 = 11;\n+ __arm_atomic_fetch_sub_with_hint (ptr6, test6, __ATOMIC_SEQ_CST, 0);\n+}\n+\n+/*\n+** testFun7:\n+** ...\n+**\tmov\t(x[0-9]+), -4622382067542392832\n+**\tstr\td31, \\[sp, 8\\]\n+**\tshuh\tph\n+**\tldadd\t\\1, \\1, \\[x[0-9]+\\]\n+** ...\n+*/\n+void\n+testFun7 ()\n+{\n+ double item7 = 10;\n+ double* ptr7 = &item7;\n+ double test7 = 11;\n+ __arm_atomic_fetch_sub_with_hint (ptr7, test7, __ATOMIC_RELAXED, 1);\n+}\n+\n+/*\n+** testFun8:\n+** ...\n+**\tmov\t(w[0-9]+), -1\n+**\tadd\t(x[0-9]+), sp, 15\n+**\tstrb\twzr, \\[sp, 15\\]\n+**\tshuh\n+**\tldaddb\t(w[0-9]+), \\1, \\[\\2\\]\n+** ...\n+*/\n+void\n+testFun8 ()\n+{\n+ char item8 = 0;\n+ char* ptr8 = &item8;\n+ long test8 = 1;\n+\n+ __arm_atomic_fetch_sub_with_hint (ptr8, test8, __ATOMIC_RELAXED, 0);\n+}\n+\n+/*\n+** testFun9:\n+** ...\n+**\tmov\t(w[0-9]+), -1\n+**\tadd\t(x[0-9]+), sp, 12\n+**\tstr\twzr, \\[sp, 12\\]\n+**\tshuh\tph\n+**\tldadd\t(w[0-9]+), \\1, \\[\\2\\]\n+** ...\n+*/\n+void\n+testFun9 ()\n+{\n+ int item9 = 0;\n+ int* ptr9 = &item9;\n+ float test9 = 1;\n+\n+ __arm_atomic_fetch_sub_with_hint (ptr9, test9, __ATOMIC_RELAXED, 1);\n+}\n+\n+/*\n+** testFun10:\n+** ...\n+**\tadd\t(x[0-9]+), \\1, 1\n+**\tmov\t(w[0-9]+), -7\n+**\tshuh\tph\n+**\tldaddb\t\\2, \\2, \\[\\1\\]\n+** ...\n+*/\n+static char buf[8];\n+void\n+testFun10 (void)\n+{\n+ __arm_atomic_fetch_sub_with_hint((buf + 1), (char)7, __ATOMIC_RELAXED, 1);\n+}\n+\n+/*\n+** testFun11:\n+** ...\n+**\tmov\t(w[0-9]+), 0\n+**\tstr\tw0, \\[sp, 12\\]\n+**\tadd\t(x[0-9]+), sp, 12\n+**\tshuh\tph\n+**\tldadd\t(w[0-9]+), \\1, \\[\\2\\]\n+** ...\n+*/\n+void\n+testFun11 ()\n+{\n+ int item11 = 10;\n+ int* ptr11 = &item11;\n+\n+ __arm_atomic_fetch_sub_with_hint (ptr11, 0, __ATOMIC_RELAXED, 1);\n+}\ndiff --git a/gcc/testsuite/gcc.target/aarch64/atomic_fetch_xor_with_shuh.c b/gcc/testsuite/gcc.target/aarch64/atomic_fetch_xor_with_shuh.c\nnew file mode 100644\nindex 00000000000..d5d2aa87f27\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/aarch64/atomic_fetch_xor_with_shuh.c\n@@ -0,0 +1,186 @@\n+/* { dg-do compile } */\n+/* { dg-options \"-O2 -march=armv8.1-a -save-temps\" } */\n+/* { dg-final { check-function-bodies \"**\" \"\" } } */\n+\n+#include <arm_acle.h>\n+\n+/*\n+** testFun1:\n+** ...\n+**\tshuh\n+**\tldeorb\t(w[0-9]+), \\1, \\[x[0-9]+\\]\n+** ...\n+*/\n+char\n+testFun1 ()\n+{\n+ char item1 = 0;\n+ char* ptr1 = &item1;\n+ char test1 = 1;\n+\n+ return __arm_atomic_fetch_xor_with_hint (ptr1, test1, __ATOMIC_RELAXED, 0);\n+}\n+\n+/*\n+** testFun2:\n+** ...\n+**\tshuh\n+**\tldeorlh\t(w[0-9]+), \\1, \\[x[0-9]+\\]\n+** ...\n+*/\n+short\n+testFun2 ()\n+{\n+ short item2 = 10;\n+ short* ptr2 = &item2;\n+ short test2 = 11;\n+ return __arm_atomic_fetch_xor_with_hint (ptr2, test2, __ATOMIC_RELEASE, 0);\n+}\n+\n+/*\n+** testFun3:\n+** ...\n+**\tshuh\tph\n+**\tldeoral\t(w[0-9]+), \\1, \\[x[0-9]+\\]\n+** ...\n+*/\n+int\n+testFun3 ()\n+{\n+ unsigned int item3 = 10;\n+ unsigned int* ptr3 = &item3;\n+ unsigned int test3 = 11;\n+ return __arm_atomic_fetch_xor_with_hint (ptr3, test3, __ATOMIC_SEQ_CST, 1);\n+}\n+\n+/*\n+** testFun4:\n+** ...\n+**\tshuh\tph\n+**\tldeor\t(x[0-9]+), \\1, \\[x[0-9]+\\]\n+** ...\n+*/\n+void\n+testFun4 ()\n+{\n+ long item4 = 10;\n+ long* ptr4 = &item4;\n+ long test4 = 11;\n+ __arm_atomic_fetch_xor_with_hint (ptr4, test4, __ATOMIC_RELAXED, 1);\n+}\n+\n+/*\n+** testFun5:\n+** ...\n+**\tshuh\n+**\tldeoral\t(x[0-9]+), \\1, \\[x[0-9]+\\]\n+** ...\n+*/\n+void\n+testFun5 ()\n+{\n+ long item5 = 10;\n+ long *ptritem = &item5;\n+ long **ptr5 = &ptritem;\n+ long test5item = 11;\n+ long *test5 = &test5item;\n+ __arm_atomic_fetch_xor_with_hint (ptr5, test5, __ATOMIC_SEQ_CST, 0);\n+}\n+\n+/*\n+** testFun6:\n+** ...\n+**\tshuh\n+**\tldeoral\t(w[0-9]+), \\1, \\[x[0-9]+\\]\n+** ...\n+*/\n+void\n+testFun6 ()\n+{\n+ float item6 = 10;\n+ float* ptr6 = &item6;\n+ float test6 = 11;\n+ __arm_atomic_fetch_xor_with_hint (ptr6, test6, __ATOMIC_SEQ_CST, 0);\n+}\n+\n+/*\n+** testFun7:\n+** ...\n+**\tshuh\tph\n+**\tldeor\t(x[0-9]+), \\1, \\[x[0-9]+\\]\n+** ...\n+*/\n+void\n+testFun7 ()\n+{\n+ double item7 = 10;\n+ double* ptr7 = &item7;\n+ double test7 = 11;\n+ __arm_atomic_fetch_xor_with_hint (ptr7, test7, __ATOMIC_RELAXED, 1);\n+}\n+\n+/*\n+** testFun8:\n+** ...\n+**\tshuh\n+**\tldeorb\t(w[0-9]+), \\1, \\[x[0-9]+\\]\n+** ...\n+*/\n+void\n+testFun8 ()\n+{\n+ char item8 = 0;\n+ char* ptr8 = &item8;\n+ long test8 = 1;\n+\n+ __arm_atomic_fetch_xor_with_hint (ptr8, test8, __ATOMIC_RELAXED, 0);\n+}\n+\n+/*\n+** testFun9:\n+** ...\n+**\tshuh\tph\n+**\tldeor\t(w[0-9]+), \\1, \\[x[0-9]+\\]\n+** ...\n+*/\n+void\n+testFun9 ()\n+{\n+ int item9 = 0;\n+ int* ptr9 = &item9;\n+ float test9 = 1;\n+\n+ __arm_atomic_fetch_xor_with_hint (ptr9, test9, __ATOMIC_RELAXED, 1);\n+}\n+\n+/*\n+** testFun10:\n+** ...\n+**\tadd\t(x[0-9]+), \\1, 1\n+**\tmov\t(w[0-9]+), 7\n+**\tshuh\tph\n+**\tldeorb\t\\2, \\2, \\[x[0-9]+\\]\n+** ...\n+*/\n+static char buf[8];\n+void\n+testFun10 (void)\n+{\n+ __arm_atomic_fetch_xor_with_hint((buf + 1), (char)7, __ATOMIC_RELAXED, 1);\n+}\n+\n+/*\n+** testFun11:\n+** ...\n+**\tshuh\tph\n+**\tldeor\t(w[0-9]+), \\1, \\[x[0-9]+\\]\n+** ...\n+*/\n+void\n+testFun11 ()\n+{\n+ int item11 = 10;\n+ int* ptr11 = &item11;\n+\n+ __arm_atomic_fetch_xor_with_hint (ptr11, 0, __ATOMIC_RELAXED, 1);\n+}\n", "prefixes": [ "2/2" ] }