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GET /api/1.2/patches/2234308/?format=api
{ "id": 2234308, "url": "http://patchwork.ozlabs.org/api/1.2/patches/2234308/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/patch/20260507155010.23784-2-richard.ball@arm.com/", "project": { "id": 17, "url": "http://patchwork.ozlabs.org/api/1.2/projects/17/?format=api", "name": "GNU Compiler Collection", "link_name": "gcc", "list_id": "gcc-patches.gcc.gnu.org", "list_email": "gcc-patches@gcc.gnu.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260507155010.23784-2-richard.ball@arm.com>", "list_archive_url": null, "date": "2026-05-07T15:50:09", "name": "[1/2] aarch64: Add support for FEAT_CMH atomic store intrinsics", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "4390bba21639bb8ff7cbc5e11affb6703fe866ea", "submitter": { "id": 84470, "url": "http://patchwork.ozlabs.org/api/1.2/people/84470/?format=api", "name": "Richard Ball", "email": "richard.ball@arm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/gcc/patch/20260507155010.23784-2-richard.ball@arm.com/mbox/", "series": [ { "id": 503209, "url": "http://patchwork.ozlabs.org/api/1.2/series/503209/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/list/?series=503209", "date": "2026-05-07T15:50:08", "name": "aarch64: Add support for FEAT_CMH", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/503209/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2234308/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2234308/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "gcc-patches@gcc.gnu.org" ], "Delivered-To": [ "patchwork-incoming@legolas.ozlabs.org", "gcc-patches@gcc.gnu.org" ], "Authentication-Results": [ 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receiver=protection.outlook.com;\n client-ip=172.205.89.229; helo=nebula.arm.com; pr=C" ], "From": "<richard.ball@arm.com>", "To": "<gcc-patches@gcc.gnu.org>", "CC": "<richard.earnshaw@arm.com>, <tamar.christina@arm.com>,\n <ktkachov@nvidia.com>, <Wilco.Dijkstra@arm.com>, <Alex.Coplan@arm.com>,\n <Alice.Carlotti@arm.com>, Richard Ball <Richard.Ball@arm.com>", "Subject": "[PATCH 1/2] aarch64: Add support for FEAT_CMH atomic store intrinsics", "Date": "Thu, 7 May 2026 16:50:09 +0100", "Message-ID": "<20260507155010.23784-2-richard.ball@arm.com>", "X-Mailer": "git-send-email 2.34.1", "In-Reply-To": "<20260507155010.23784-1-richard.ball@arm.com>", "References": "<20260507155010.23784-1-richard.ball@arm.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-EOPAttributedMessage": "1", "X-MS-TrafficTypeDiagnostic": "\n AMS1EPF0000008E:EE_|DB9PR08MB11402:EE_|DB1PEPF000509F5:EE_|AS8PR08MB6502:EE_", "X-MS-Office365-Filtering-Correlation-Id": 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e0401294-4b61-4c0e-dca3-08deac508791", "X-MS-Exchange-CrossTenant-Id": "f34e5979-57d9-4aaa-ad4d-b122a662184d", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d; Ip=[4.158.2.129];\n Helo=[outbound-uk1.az.dlp.m.darktrace.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n DB1PEPF000509F5.eurprd02.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-BeenThere": "gcc-patches@gcc.gnu.org", "X-Mailman-Version": "2.1.30", "Precedence": "list", "List-Id": "Gcc-patches mailing list <gcc-patches.gcc.gnu.org>", "List-Unsubscribe": "<https://gcc.gnu.org/mailman/options/gcc-patches>,\n <mailto:gcc-patches-request@gcc.gnu.org?subject=unsubscribe>", "List-Archive": "<https://gcc.gnu.org/pipermail/gcc-patches/>", "List-Post": "<mailto:gcc-patches@gcc.gnu.org>", "List-Help": "<mailto:gcc-patches-request@gcc.gnu.org?subject=help>", "List-Subscribe": "<https://gcc.gnu.org/mailman/listinfo/gcc-patches>,\n <mailto:gcc-patches-request@gcc.gnu.org?subject=subscribe>", "Errors-To": "gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org" }, "content": "From: Richard Ball <Richard.Ball@arm.com>\n\ngcc/ChangeLog:\n\n\t* config/aarch64/aarch64-builtins.cc\n\t(enum aarch64_builtins): Change Function/Builtin names.\n\t(aarch64_init_pcdphint_builtins): Likewise.\n\t(aarch64_init_atomic_hints_builtins): Likewise.\n\t(aarch64_general_init_builtins): Likewise.\n\t(aarch64_expand_stshh_builtin): Likewise.\n\t(aarch64_expand_atomic_hints_builtins): Likewise.\n\t(aarch64_general_expand_builtin): Likewise.\n\t(aarch64_resolve_overloaded_builtin_stshh): Likewise.\n\t(aarch64_resolve_overloaded_builtin_atomic_hint_store): Likewise\n\t(aarch64_resolve_overloaded_builtin_general): Likewise.\n\t* config/aarch64/arm_acle.h\n\t(__atomic_store_with_stshh): Likewise.\n\t(__arm_atomic_store_with_hint): Likewise.\n\t* config/aarch64/atomics.md\n\t(@aarch64_atomic_store_stshh<mode>): Add new hints to pattern\n\t(@aarch64_atomic_hints_store<mode>): Likewise.\n\t* config/aarch64/iterators.md: Add Unspec for new hints.\n\ngcc/testsuite/ChangeLog:\n\n\t* g++.target/aarch64/atomic_store_with_stshh.C: Change Function name.\n\t* gcc.target/aarch64/atomic_store_with_stshh.c: Likewise.\n\t* gcc.target/aarch64/atomic_store_with_shuh.c: New test.\n\t* gcc.target/aarch64/atomic_store_with_stcph.c: New test.\n---\n gcc/config/aarch64/aarch64-builtins.cc | 133 +++++++------\n gcc/config/aarch64/arm_acle.h | 6 +-\n gcc/config/aarch64/atomics.md | 28 ++-\n gcc/config/aarch64/iterators.md | 2 +-\n .../aarch64/atomic_store_with_stshh.C | 22 +--\n .../aarch64/atomic_store_with_shuh.c | 186 ++++++++++++++++++\n .../aarch64/atomic_store_with_stcph.c | 186 ++++++++++++++++++\n .../aarch64/atomic_store_with_stshh.c | 22 +--\n 8 files changed, 490 insertions(+), 95 deletions(-)\n create mode 100644 gcc/testsuite/gcc.target/aarch64/atomic_store_with_shuh.c\n create mode 100644 gcc/testsuite/gcc.target/aarch64/atomic_store_with_stcph.c", "diff": "diff --git a/gcc/config/aarch64/aarch64-builtins.cc b/gcc/config/aarch64/aarch64-builtins.cc\nindex 611f6dc45e0..2a6ecddd91b 100644\n--- a/gcc/config/aarch64/aarch64-builtins.cc\n+++ b/gcc/config/aarch64/aarch64-builtins.cc\n@@ -903,14 +903,14 @@ enum aarch64_builtins\n AARCH64_BUILTIN_GCSPOPM,\n AARCH64_BUILTIN_GCSSS,\n /* Armv9.6-A builtins. */\n- AARCH64_BUILTIN_STSHH,\n- AARCH64_BUILTIN_STSHH_QI,\n- AARCH64_BUILTIN_STSHH_HI,\n- AARCH64_BUILTIN_STSHH_SI,\n- AARCH64_BUILTIN_STSHH_DI,\n- AARCH64_BUILTIN_STSHH_SF,\n- AARCH64_BUILTIN_STSHH_DF,\n- AARCH64_BUILTIN_STSHH_PTR,\n+ AARCH64_BUILTIN_ATOMIC_HINTS_STORE,\n+ AARCH64_BUILTIN_ATOMIC_HINTS_STORE_QI,\n+ AARCH64_BUILTIN_ATOMIC_HINTS_STORE_HI,\n+ AARCH64_BUILTIN_ATOMIC_HINTS_STORE_SI,\n+ AARCH64_BUILTIN_ATOMIC_HINTS_STORE_DI,\n+ AARCH64_BUILTIN_ATOMIC_HINTS_STORE_SF,\n+ AARCH64_BUILTIN_ATOMIC_HINTS_STORE_DF,\n+ AARCH64_BUILTIN_ATOMIC_HINTS_STORE_PTR,\n AARCH64_BUILTIN_MAX\n };\n \n@@ -2483,10 +2483,10 @@ aarch64_init_gcs_builtins (void)\n \t\t\t\t AARCH64_BUILTIN_GCSSS);\n }\n \n-/* Add builtins for FEAT_PCDPHINT. */\n+/* Add builtins for atomic hints. */\n \n static void\n-aarch64_init_pcdphint_builtins (void)\n+aarch64_init_atomic_hints_builtins (void)\n {\n tree ftype;\n \n@@ -2494,65 +2494,72 @@ aarch64_init_pcdphint_builtins (void)\n \t\t\t\t void_type_node,\n \t\t\t\t unsigned_type_node,\n \t\t\t\t unsigned_type_node, NULL_TREE);\n- aarch64_builtin_decls[AARCH64_BUILTIN_STSHH]\n- = aarch64_general_add_builtin (\"__builtin_aarch64_stshh\", ftype,\n-\t\t\t\t AARCH64_BUILTIN_STSHH);\n+ aarch64_builtin_decls[AARCH64_BUILTIN_ATOMIC_HINTS_STORE]\n+ = aarch64_general_add_builtin (\"__builtin_aarch64_atomic_hints_store\",\n+\t\t\t\t ftype, AARCH64_BUILTIN_ATOMIC_HINTS_STORE);\n \n ftype = build_function_type_list (void_type_node, ptr_type_node,\n \t\t\t\t unsigned_char_type_node,\n \t\t\t\t unsigned_type_node,\n \t\t\t\t unsigned_type_node, NULL_TREE);\n- aarch64_builtin_decls[AARCH64_BUILTIN_STSHH_QI]\n- = aarch64_general_add_builtin (\"__builtin_aarch64_stshh_qi\", ftype,\n-\t\t\t\t AARCH64_BUILTIN_STSHH_QI);\n+ aarch64_builtin_decls[AARCH64_BUILTIN_ATOMIC_HINTS_STORE_QI]\n+ = aarch64_general_add_builtin (\"__builtin_aarch64_atomic_hints_store_qi\",\n+\t\t\t\t ftype,\n+\t\t\t\t AARCH64_BUILTIN_ATOMIC_HINTS_STORE_QI);\n \n ftype = build_function_type_list (void_type_node, ptr_type_node,\n \t\t\t\t short_unsigned_type_node,\n \t\t\t\t unsigned_type_node,\n \t\t\t\t unsigned_type_node, NULL_TREE);\n- aarch64_builtin_decls[AARCH64_BUILTIN_STSHH_HI]\n- = aarch64_general_add_builtin (\"__builtin_aarch64_stshh_hi\", ftype,\n-\t\t\t\t AARCH64_BUILTIN_STSHH_HI);\n+ aarch64_builtin_decls[AARCH64_BUILTIN_ATOMIC_HINTS_STORE_HI]\n+ = aarch64_general_add_builtin (\"__builtin_aarch64_atomic_hints_store_hi\",\n+\t\t\t\t ftype,\n+\t\t\t\t AARCH64_BUILTIN_ATOMIC_HINTS_STORE_HI);\n \n ftype = build_function_type_list (void_type_node, ptr_type_node,\n \t\t\t\t unsigned_type_node,\n \t\t\t\t unsigned_type_node,\n \t\t\t\t unsigned_type_node, NULL_TREE);\n- aarch64_builtin_decls[AARCH64_BUILTIN_STSHH_SI]\n- = aarch64_general_add_builtin (\"__builtin_aarch64_stshh_si\", ftype,\n-\t\t\t\t AARCH64_BUILTIN_STSHH_SI);\n+ aarch64_builtin_decls[AARCH64_BUILTIN_ATOMIC_HINTS_STORE_SI]\n+ = aarch64_general_add_builtin (\"__builtin_aarch64_atomic_hints_store_si\",\n+\t\t\t\t ftype,\n+\t\t\t\t AARCH64_BUILTIN_ATOMIC_HINTS_STORE_SI);\n \n ftype = build_function_type_list (void_type_node, ptr_type_node,\n \t\t\t\t long_long_unsigned_type_node,\n \t\t\t\t unsigned_type_node,\n \t\t\t\t unsigned_type_node, NULL_TREE);\n- aarch64_builtin_decls[AARCH64_BUILTIN_STSHH_DI]\n- = aarch64_general_add_builtin (\"__builtin_aarch64_stshh_di\", ftype,\n-\t\t\t\t AARCH64_BUILTIN_STSHH_DI);\n+ aarch64_builtin_decls[AARCH64_BUILTIN_ATOMIC_HINTS_STORE_DI]\n+ = aarch64_general_add_builtin (\"__builtin_aarch64_atomic_hints_store_di\",\n+\t\t\t\t ftype,\n+\t\t\t\t AARCH64_BUILTIN_ATOMIC_HINTS_STORE_DI);\n \n ftype = build_function_type_list (void_type_node, ptr_type_node,\n \t\t\t\t float_type_node,\n \t\t\t\t unsigned_type_node,\n \t\t\t\t unsigned_type_node, NULL_TREE);\n- aarch64_builtin_decls[AARCH64_BUILTIN_STSHH_SF]\n- = aarch64_general_add_builtin (\"__builtin_aarch64_stshh_sf\", ftype,\n-\t\t\t\t AARCH64_BUILTIN_STSHH_SF);\n+ aarch64_builtin_decls[AARCH64_BUILTIN_ATOMIC_HINTS_STORE_SF]\n+ = aarch64_general_add_builtin (\"__builtin_aarch64_atomic_hints_store_sf\",\n+\t\t\t\t ftype,\n+\t\t\t\t AARCH64_BUILTIN_ATOMIC_HINTS_STORE_SF);\n \n ftype = build_function_type_list (void_type_node, ptr_type_node,\n \t\t\t\t double_type_node,\n \t\t\t\t unsigned_type_node,\n \t\t\t\t unsigned_type_node, NULL_TREE);\n- aarch64_builtin_decls[AARCH64_BUILTIN_STSHH_DF]\n- = aarch64_general_add_builtin (\"__builtin_aarch64_stshh_df\", ftype,\n-\t\t\t\t AARCH64_BUILTIN_STSHH_DF);\n+ aarch64_builtin_decls[AARCH64_BUILTIN_ATOMIC_HINTS_STORE_DF]\n+ = aarch64_general_add_builtin (\"__builtin_aarch64_atomic_hints_store_df\",\n+\t\t\t\t ftype,\n+\t\t\t\t AARCH64_BUILTIN_ATOMIC_HINTS_STORE_DF);\n \n ftype = build_function_type_list (void_type_node, ptr_type_node,\n \t\t\t\t ptr_type_node,\n \t\t\t\t unsigned_type_node,\n \t\t\t\t unsigned_type_node, NULL_TREE);\n- aarch64_builtin_decls[AARCH64_BUILTIN_STSHH_PTR]\n- = aarch64_general_add_builtin (\"__builtin_aarch64_stshh_ptr\", ftype,\n-\t\t\t\t AARCH64_BUILTIN_STSHH_PTR);\n+ aarch64_builtin_decls[AARCH64_BUILTIN_ATOMIC_HINTS_STORE_PTR]\n+ = aarch64_general_add_builtin (\"__builtin_aarch64_atomic_hints_store_ptr\",\n+\t\t\t\t ftype,\n+\t\t\t\t AARCH64_BUILTIN_ATOMIC_HINTS_STORE_PTR);\n \n }\n \n@@ -2603,7 +2610,7 @@ aarch64_general_init_builtins (void)\n \t\t\t\t AARCH64_BUILTIN_CHKFEAT);\n \n aarch64_init_gcs_builtins ();\n- aarch64_init_pcdphint_builtins ();\n+ aarch64_init_atomic_hints_builtins ();\n \n if (in_lto_p)\n handle_arm_acle_h ();\n@@ -4059,27 +4066,27 @@ aarch64_expand_tbl_tbx (vec<expand_operand> &ops, int unspec)\n }\n \n void\n-aarch64_expand_stshh_builtin (tree exp, int fcode)\n+aarch64_expand_atomic_hints_builtins (tree exp, int fcode)\n {\n machine_mode mode = TYPE_MODE (TREE_TYPE (CALL_EXPR_ARG (exp, 1)));\n rtx val = expand_normal (CALL_EXPR_ARG (exp, 1));\n rtx mem_order = expand_normal (CALL_EXPR_ARG (exp, 2));\n- rtx ret = expand_normal (CALL_EXPR_ARG (exp, 3));\n+ rtx hint = expand_normal (CALL_EXPR_ARG (exp, 3));\n \n- require_const_argument (exp, 3, 0, 2);\n+ require_const_argument (exp, 3, 0, 5);\n require_const_argument (exp, 2, 0, 6);\n if (seen_error ())\n return;\n \n switch (fcode)\n {\n- case AARCH64_BUILTIN_STSHH_SF:\n+ case AARCH64_BUILTIN_ATOMIC_HINTS_STORE_SF:\n \t{\n \t val = force_lowpart_subreg (SImode, val, SFmode);\n \t mode = SImode;\n \t break;\n \t}\n- case AARCH64_BUILTIN_STSHH_DF:\n+ case AARCH64_BUILTIN_ATOMIC_HINTS_STORE_DF:\n \t{\n \t val = force_lowpart_subreg (DImode, val, DFmode);\n \t mode = DImode;\n@@ -4099,12 +4106,12 @@ aarch64_expand_stshh_builtin (tree exp, int fcode)\n set_mem_align (mem, GET_MODE_ALIGNMENT (mode));\n \n expand_operand ops[4];\n- enum insn_code icode = code_for_aarch64_atomic_store_stshh (mode);\n+ enum insn_code icode;\n create_output_operand (&ops[0], mem, mode);\n create_input_operand (&ops[1], val, mode);\n create_input_operand (&ops[2], mem_order, SImode);\n- create_input_operand (&ops[3], ret, SImode);\n-\n+ create_input_operand (&ops[3], hint, SImode);\n+ icode = code_for_aarch64_atomic_hints_store (mode);\n expand_insn (icode, 4, ops);\n }\n \n@@ -4611,14 +4618,14 @@ aarch64_general_expand_builtin (unsigned int fcode, tree exp, rtx target,\n case AARCH64_BUILTIN_GCSSS:\n return aarch64_expand_gcs_builtin (exp, target, fcode, ignore);\n \n- case AARCH64_BUILTIN_STSHH_QI:\n- case AARCH64_BUILTIN_STSHH_HI:\n- case AARCH64_BUILTIN_STSHH_SI:\n- case AARCH64_BUILTIN_STSHH_DI:\n- case AARCH64_BUILTIN_STSHH_SF:\n- case AARCH64_BUILTIN_STSHH_DF:\n- case AARCH64_BUILTIN_STSHH_PTR:\n- aarch64_expand_stshh_builtin (exp, fcode);\n+ case AARCH64_BUILTIN_ATOMIC_HINTS_STORE_QI:\n+ case AARCH64_BUILTIN_ATOMIC_HINTS_STORE_HI:\n+ case AARCH64_BUILTIN_ATOMIC_HINTS_STORE_SI:\n+ case AARCH64_BUILTIN_ATOMIC_HINTS_STORE_DI:\n+ case AARCH64_BUILTIN_ATOMIC_HINTS_STORE_SF:\n+ case AARCH64_BUILTIN_ATOMIC_HINTS_STORE_DF:\n+ case AARCH64_BUILTIN_ATOMIC_HINTS_STORE_PTR:\n+ aarch64_expand_atomic_hints_builtins (exp, fcode);\n return target;\n }\n \n@@ -5781,11 +5788,9 @@ aarch64_resolve_overloaded_memtag (location_t loc,\n }\n \n static tree\n-aarch64_resolve_overloaded_builtin_stshh (void *pass_params)\n+aarch64_resolve_overloaded_builtin_atomic_hints (void *pass_params)\n {\n vec<tree, va_gc> *params = static_cast<vec<tree, va_gc> *> (pass_params);\n- if (vec_safe_length (params) != 4)\n- return NULL_TREE;\n \n tree addr = (*params)[0];\n tree val = (*params)[1];\n@@ -5798,23 +5803,25 @@ aarch64_resolve_overloaded_builtin_stshh (void *pass_params)\n \n tree ptr_type = TYPE_MAIN_VARIANT (TREE_TYPE (addr_type));\n \n+ if (vec_safe_length (params) != 4)\n+ return NULL_TREE;\n if (POINTER_TYPE_P (ptr_type))\n- return aarch64_builtin_decls[AARCH64_BUILTIN_STSHH_PTR];\n+ return aarch64_builtin_decls[AARCH64_BUILTIN_ATOMIC_HINTS_STORE_PTR];\n \n switch (TYPE_MODE (ptr_type))\n {\n case QImode:\n- return aarch64_builtin_decls[AARCH64_BUILTIN_STSHH_QI];\n+ return aarch64_builtin_decls[AARCH64_BUILTIN_ATOMIC_HINTS_STORE_QI];\n case HImode:\n- return aarch64_builtin_decls[AARCH64_BUILTIN_STSHH_HI];\n+ return aarch64_builtin_decls[AARCH64_BUILTIN_ATOMIC_HINTS_STORE_HI];\n case SImode:\n- return aarch64_builtin_decls[AARCH64_BUILTIN_STSHH_SI];\n+ return aarch64_builtin_decls[AARCH64_BUILTIN_ATOMIC_HINTS_STORE_SI];\n case DImode:\n- return aarch64_builtin_decls[AARCH64_BUILTIN_STSHH_DI];\n+ return aarch64_builtin_decls[AARCH64_BUILTIN_ATOMIC_HINTS_STORE_DI];\n case SFmode:\n- return aarch64_builtin_decls[AARCH64_BUILTIN_STSHH_SF];\n+ return aarch64_builtin_decls[AARCH64_BUILTIN_ATOMIC_HINTS_STORE_SF];\n case DFmode:\n- return aarch64_builtin_decls[AARCH64_BUILTIN_STSHH_DF];\n+ return aarch64_builtin_decls[AARCH64_BUILTIN_ATOMIC_HINTS_STORE_DF];\n default:\n return NULL_TREE;\n }\n@@ -5831,8 +5838,8 @@ aarch64_resolve_overloaded_builtin_general (location_t loc, tree function,\n && fcode <= AARCH64_MEMTAG_BUILTIN_END)\n return aarch64_resolve_overloaded_memtag(loc, function, pass_params);\n \n- if (fcode == AARCH64_BUILTIN_STSHH)\n- return aarch64_resolve_overloaded_builtin_stshh (pass_params);\n+ if (fcode == AARCH64_BUILTIN_ATOMIC_HINTS_STORE)\n+ return aarch64_resolve_overloaded_builtin_atomic_hints (pass_params);\n \n return NULL_TREE;\n }\ndiff --git a/gcc/config/aarch64/arm_acle.h b/gcc/config/aarch64/arm_acle.h\nindex b31e23e6cba..9317f1d2371 100644\n--- a/gcc/config/aarch64/arm_acle.h\n+++ b/gcc/config/aarch64/arm_acle.h\n@@ -102,9 +102,9 @@ __sqrtf (float __x)\n return __builtin_aarch64_sqrtsf (__x);\n }\n \n-#define __atomic_store_with_stshh(__addr, __value, __memory_order, __ret) \\\n- __builtin_aarch64_stshh ((__addr), (__value), \\\n-\t\t\t\t\t (__memory_order), (__ret))\n+#define __arm_atomic_store_with_hint(__addr, __value, __memory_order, __hint) \\\n+ __builtin_aarch64_atomic_hints_store ((__addr), (__value), \\\n+\t\t\t\t\t (__memory_order), (__hint))\n \n #pragma GCC push_options\n #pragma GCC target (\"+nothing+jscvt\")\ndiff --git a/gcc/config/aarch64/atomics.md b/gcc/config/aarch64/atomics.md\nindex c9534d43c0f..b86dae31dc1 100644\n--- a/gcc/config/aarch64/atomics.md\n+++ b/gcc/config/aarch64/atomics.md\n@@ -751,19 +751,35 @@\n [(set_attr \"arch\" \"*,rcpc8_4\")]\n )\n \n-(define_insn \"@aarch64_atomic_store_stshh<mode>\"\n+(define_insn \"@aarch64_atomic_hints_store<mode>\"\n [(set (match_operand:ALLI 0 \"aarch64_rcpc_memory_operand\" \"=Q,Ust\")\n (unspec_volatile:ALLI\n [(match_operand:ALLI 1 \"aarch64_reg_or_zero\" \"rZ,rZ\")\n (match_operand:SI 2 \"const_int_operand\")\t\t\t;; model\n (match_operand:SI 3 \"const_int_operand\")]\t\t;; ret_policy\n- UNSPECV_STSHH))]\n+ UNSPECV_ATOMIC_HINTS_STORE))]\n \"\"\n {\n- if (INTVAL (operands[3]) == 0)\n- output_asm_insn (\"stshh\\tkeep\", operands);\n- else\n- output_asm_insn (\"stshh\\tstrm\", operands);\n+ switch (INTVAL (operands[3]))\n+ {\n+ case 0:\n+\toutput_asm_insn (\"stshh\\tkeep\", operands);\n+\tbreak;\n+ case 1:\n+\toutput_asm_insn (\"stshh\\tstrm\", operands);\n+\tbreak;\n+ case 2:\n+\toutput_asm_insn (\"stcph\", operands);\n+\tbreak;\n+ case 3:\n+\toutput_asm_insn (\"shuh\", operands);\n+\tbreak;\n+ case 4:\n+\toutput_asm_insn (\"shuh\\tph\", operands);\n+\tbreak;\n+ default:\n+\tgcc_unreachable ();\n+ }\n enum memmodel model = memmodel_from_int (INTVAL (operands[2]));\n if (is_mm_relaxed (model) || is_mm_consume (model) || is_mm_acquire (model))\n return \"str<atomic_sfx>\\t%<w>1, %0\";\ndiff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md\nindex 39b1e84edcc..df61f9b4f53 100644\n--- a/gcc/config/aarch64/iterators.md\n+++ b/gcc/config/aarch64/iterators.md\n@@ -1356,7 +1356,7 @@\n UNSPECV_LDA\t\t\t; Represent an atomic load or load-acquire.\n UNSPECV_LDAP\t\t; Represent an atomic acquire load with RCpc semantics.\n UNSPECV_STL\t\t\t; Represent an atomic store or store-release.\n- UNSPECV_STSHH\t\t; Represent an atomic store with an stshh hint.\n+ UNSPECV_ATOMIC_HINTS_STORE\t; Represent an atomic store with a hint.\n UNSPECV_ATOMIC_CMPSW\t; Represent an atomic compare swap.\n UNSPECV_ATOMIC_EXCHG\t; Represent an atomic exchange.\n UNSPECV_ATOMIC_CAS\t\t; Represent an atomic CAS.\ndiff --git a/gcc/testsuite/g++.target/aarch64/atomic_store_with_stshh.C b/gcc/testsuite/g++.target/aarch64/atomic_store_with_stshh.C\nindex d22412369ef..5553c5d67df 100644\n--- a/gcc/testsuite/g++.target/aarch64/atomic_store_with_stshh.C\n+++ b/gcc/testsuite/g++.target/aarch64/atomic_store_with_stshh.C\n@@ -18,7 +18,7 @@ testFun1 ()\n char* ptr1 = &item1;\n char test1 = 1;\n \n- __atomic_store_with_stshh (ptr1, test1, __ATOMIC_RELAXED, 0);\n+ __arm_atomic_store_with_hint (ptr1, test1, __ATOMIC_RELAXED, 0);\n }\n \n /*\n@@ -34,7 +34,7 @@ testFun2 ()\n short item2 = 10;\n short* ptr2 = &item2;\n short test2 = 11;\n- __atomic_store_with_stshh (ptr2, test2, __ATOMIC_RELEASE, 0);\n+ __arm_atomic_store_with_hint (ptr2, test2, __ATOMIC_RELEASE, 0);\n }\n \n /*\n@@ -50,7 +50,7 @@ testFun3 ()\n unsigned int item3 = 10;\n unsigned int* ptr3 = &item3;\n unsigned int test3 = 11;\n- __atomic_store_with_stshh (ptr3, test3, __ATOMIC_SEQ_CST, 1);\n+ __arm_atomic_store_with_hint (ptr3, test3, __ATOMIC_SEQ_CST, 1);\n }\n \n /*\n@@ -66,7 +66,7 @@ testFun4 ()\n long item4 = 10;\n long* ptr4 = &item4;\n long test4 = 11;\n- __atomic_store_with_stshh (ptr4, test4, __ATOMIC_RELAXED, 1);\n+ __arm_atomic_store_with_hint (ptr4, test4, __ATOMIC_RELAXED, 1);\n }\n \n /*\n@@ -84,7 +84,7 @@ testFun5 ()\n long **ptr5 = &ptritem;\n long test5item = 11;\n long *test5 = &test5item;\n- __atomic_store_with_stshh (ptr5, test5, __ATOMIC_SEQ_CST, 0);\n+ __arm_atomic_store_with_hint (ptr5, test5, __ATOMIC_SEQ_CST, 0);\n }\n \n /*\n@@ -100,7 +100,7 @@ testFun6 ()\n float item6 = 10;\n float* ptr6 = &item6;\n float test6 = 11;\n- __atomic_store_with_stshh (ptr6, test6, __ATOMIC_SEQ_CST, 0);\n+ __arm_atomic_store_with_hint (ptr6, test6, __ATOMIC_SEQ_CST, 0);\n }\n \n /*\n@@ -116,7 +116,7 @@ testFun7 ()\n double item7 = 10;\n double* ptr7 = &item7;\n double test7 = 11;\n- __atomic_store_with_stshh (ptr7, test7, __ATOMIC_RELAXED, 1);\n+ __arm_atomic_store_with_hint (ptr7, test7, __ATOMIC_RELAXED, 1);\n }\n \n /*\n@@ -133,7 +133,7 @@ testFun8 ()\n char* ptr8 = &item8;\n long test8 = 1;\n \n- __atomic_store_with_stshh (ptr8, test8, __ATOMIC_RELAXED, 0);\n+ __arm_atomic_store_with_hint (ptr8, test8, __ATOMIC_RELAXED, 0);\n }\n \n /*\n@@ -150,7 +150,7 @@ testFun9 ()\n int* ptr9 = &item9;\n float test9 = 1;\n \n- __atomic_store_with_stshh (ptr9, test9, __ATOMIC_RELAXED, 1);\n+ __arm_atomic_store_with_hint (ptr9, test9, __ATOMIC_RELAXED, 1);\n }\n \n /*\n@@ -166,7 +166,7 @@ static char buf[8];\n void\n testFun10 (void)\n {\n- __atomic_store_with_stshh((buf + 1), (char)7, __ATOMIC_RELAXED, 1);\n+ __arm_atomic_store_with_hint((buf + 1), (char)7, __ATOMIC_RELAXED, 1);\n }\n \n /*\n@@ -182,5 +182,5 @@ testFun11 ()\n int item11 = 10;\n int* ptr11 = &item11;\n \n- __atomic_store_with_stshh (ptr11, 0, __ATOMIC_RELAXED, 1);\n+ __arm_atomic_store_with_hint (ptr11, 0, __ATOMIC_RELAXED, 1);\n }\ndiff --git a/gcc/testsuite/gcc.target/aarch64/atomic_store_with_shuh.c b/gcc/testsuite/gcc.target/aarch64/atomic_store_with_shuh.c\nnew file mode 100644\nindex 00000000000..ce457a85568\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/aarch64/atomic_store_with_shuh.c\n@@ -0,0 +1,186 @@\n+/* { dg-do compile } */\n+/* { dg-options \"-O2 -march=armv8-a -save-temps\" } */\n+/* { dg-final { check-function-bodies \"**\" \"\" } } */\n+\n+#include <arm_acle.h>\n+\n+/*\n+** testFun1:\n+** ...\n+**\tshuh\n+**\tstrb\tw[0-9]+, \\[x[0-9]+\\]\n+** ...\n+*/\n+void\n+testFun1 ()\n+{\n+ char item1 = 0;\n+ char* ptr1 = &item1;\n+ char test1 = 1;\n+\n+ __arm_atomic_store_with_hint (ptr1, test1, __ATOMIC_RELAXED, 3);\n+}\n+\n+/*\n+** testFun2:\n+** ...\n+**\tshuh\tph\n+**\tstlrh\tw[0-9]+, \\[x[0-9]+\\]\n+** ...\n+*/\n+void\n+testFun2 ()\n+{\n+ short item2 = 10;\n+ short* ptr2 = &item2;\n+ short test2 = 11;\n+ __arm_atomic_store_with_hint (ptr2, test2, __ATOMIC_RELEASE, 4);\n+}\n+\n+/*\n+** testFun3:\n+** ...\n+**\tshuh\n+**\tstlr\tw[0-9]+, \\[x[0-9]+\\]\n+** ...\n+*/\n+void\n+testFun3 ()\n+{\n+ unsigned int item3 = 10;\n+ unsigned int* ptr3 = &item3;\n+ unsigned int test3 = 11;\n+ __arm_atomic_store_with_hint (ptr3, test3, __ATOMIC_SEQ_CST, 3);\n+}\n+\n+/*\n+** testFun4:\n+** ...\n+**\tshuh\n+**\tstr\tx[0-9]+, \\[x[0-9]+\\]\n+** ...\n+*/\n+void\n+testFun4 ()\n+{\n+ long item4 = 10;\n+ long* ptr4 = &item4;\n+ long test4 = 11;\n+ __arm_atomic_store_with_hint (ptr4, test4, __ATOMIC_RELAXED, 3);\n+}\n+\n+/*\n+** testFun5:\n+** ...\n+**\tshuh\tph\n+**\tstlr\tx[0-9]+, \\[x[0-9]+\\]\n+** ...\n+*/\n+void\n+testFun5 ()\n+{\n+ long item5 = 10;\n+ long *ptritem = &item5;\n+ long **ptr5 = &ptritem;\n+ long test5item = 11;\n+ long *test5 = &test5item;\n+ __arm_atomic_store_with_hint (ptr5, test5, __ATOMIC_SEQ_CST, 4);\n+}\n+\n+/*\n+** testFun6:\n+** ...\n+**\tshuh\n+**\tstlr\tw[0-9]+, \\[x[0-9]+\\]\n+** ...\n+*/\n+void\n+testFun6 ()\n+{\n+ float item6 = 10;\n+ float* ptr6 = &item6;\n+ float test6 = 11;\n+ __arm_atomic_store_with_hint (ptr6, test6, __ATOMIC_SEQ_CST, 3);\n+}\n+\n+/*\n+** testFun7:\n+** ...\n+**\tshuh\tph\n+**\tstr\tx[0-9]+, \\[x[0-9]+\\]\n+** ...\n+*/\n+void\n+testFun7 ()\n+{\n+ double item7 = 10;\n+ double* ptr7 = &item7;\n+ double test7 = 11;\n+ __arm_atomic_store_with_hint (ptr7, test7, __ATOMIC_RELAXED, 4);\n+}\n+\n+/*\n+** testFun8:\n+** ...\n+**\tshuh\tph\n+**\tstrb\tw[0-9]+, \\[x[0-9]+\\]\n+** ...\n+*/\n+void\n+testFun8 ()\n+{\n+ char item8 = 0;\n+ char* ptr8 = &item8;\n+ long test8 = 1;\n+\n+ __arm_atomic_store_with_hint (ptr8, test8, __ATOMIC_RELAXED, 4);\n+}\n+\n+/*\n+** testFun9:\n+** ...\n+**\tshuh\n+**\tstr\tw[0-9]+, \\[x[0-9]+\\]\n+** ...\n+*/\n+void\n+testFun9 ()\n+{\n+ int item9 = 0;\n+ int* ptr9 = &item9;\n+ float test9 = 1;\n+\n+ __arm_atomic_store_with_hint (ptr9, test9, __ATOMIC_RELAXED, 3);\n+}\n+\n+/*\n+** testFun10:\n+** ...\n+**\tadd\t(x[0-9]+), \\1, 1\n+**\tmov\t(w[0-9]+), 7\n+**\tshuh\n+**\tstrb\t\\2, \\[\\1\\]\n+** ...\n+*/\n+static char buf[8];\n+void\n+testFun10 (void)\n+{\n+ __arm_atomic_store_with_hint((buf + 1), (char)7, __ATOMIC_RELAXED, 3);\n+}\n+\n+/*\n+** testFun11:\n+** ...\n+**\tshuh\n+**\tstr\twzr, \\[x[0-9]+\\]\n+** ...\n+*/\n+void\n+testFun11 ()\n+{\n+ int item11 = 10;\n+ int* ptr11 = &item11;\n+\n+ __arm_atomic_store_with_hint (ptr11, 0, __ATOMIC_RELAXED, 3);\n+}\ndiff --git a/gcc/testsuite/gcc.target/aarch64/atomic_store_with_stcph.c b/gcc/testsuite/gcc.target/aarch64/atomic_store_with_stcph.c\nnew file mode 100644\nindex 00000000000..a762da3e1f6\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/aarch64/atomic_store_with_stcph.c\n@@ -0,0 +1,186 @@\n+/* { dg-do compile } */\n+/* { dg-options \"-O2 -march=armv8-a -save-temps\" } */\n+/* { dg-final { check-function-bodies \"**\" \"\" } } */\n+\n+#include <arm_acle.h>\n+\n+/*\n+** testFun1:\n+** ...\n+**\tstcph\n+**\tstrb\tw[0-9]+, \\[x[0-9]+\\]\n+** ...\n+*/\n+void\n+testFun1 ()\n+{\n+ char item1 = 0;\n+ char* ptr1 = &item1;\n+ char test1 = 1;\n+\n+ __arm_atomic_store_with_hint (ptr1, test1, __ATOMIC_RELAXED, 2);\n+}\n+\n+/*\n+** testFun2:\n+** ...\n+**\tstcph\n+**\tstlrh\tw[0-9]+, \\[x[0-9]+\\]\n+** ...\n+*/\n+void\n+testFun2 ()\n+{\n+ short item2 = 10;\n+ short* ptr2 = &item2;\n+ short test2 = 11;\n+ __arm_atomic_store_with_hint (ptr2, test2, __ATOMIC_RELEASE, 2);\n+}\n+\n+/*\n+** testFun3:\n+** ...\n+**\tstcph\n+**\tstlr\tw[0-9]+, \\[x[0-9]+\\]\n+** ...\n+*/\n+void\n+testFun3 ()\n+{\n+ unsigned int item3 = 10;\n+ unsigned int* ptr3 = &item3;\n+ unsigned int test3 = 11;\n+ __arm_atomic_store_with_hint (ptr3, test3, __ATOMIC_SEQ_CST, 2);\n+}\n+\n+/*\n+** testFun4:\n+** ...\n+**\tstcph\n+**\tstr\tx[0-9]+, \\[x[0-9]+\\]\n+** ...\n+*/\n+void\n+testFun4 ()\n+{\n+ long item4 = 10;\n+ long* ptr4 = &item4;\n+ long test4 = 11;\n+ __arm_atomic_store_with_hint (ptr4, test4, __ATOMIC_RELAXED, 2);\n+}\n+\n+/*\n+** testFun5:\n+** ...\n+**\tstcph\n+**\tstlr\tx[0-9]+, \\[x[0-9]+\\]\n+** ...\n+*/\n+void\n+testFun5 ()\n+{\n+ long item5 = 10;\n+ long *ptritem = &item5;\n+ long **ptr5 = &ptritem;\n+ long test5item = 11;\n+ long *test5 = &test5item;\n+ __arm_atomic_store_with_hint (ptr5, test5, __ATOMIC_SEQ_CST, 2);\n+}\n+\n+/*\n+** testFun6:\n+** ...\n+**\tstcph\n+**\tstlr\tw[0-9]+, \\[x[0-9]+\\]\n+** ...\n+*/\n+void\n+testFun6 ()\n+{\n+ float item6 = 10;\n+ float* ptr6 = &item6;\n+ float test6 = 11;\n+ __arm_atomic_store_with_hint (ptr6, test6, __ATOMIC_SEQ_CST, 2);\n+}\n+\n+/*\n+** testFun7:\n+** ...\n+**\tstcph\n+**\tstr\tx[0-9]+, \\[x[0-9]+\\]\n+** ...\n+*/\n+void\n+testFun7 ()\n+{\n+ double item7 = 10;\n+ double* ptr7 = &item7;\n+ double test7 = 11;\n+ __arm_atomic_store_with_hint (ptr7, test7, __ATOMIC_RELAXED, 2);\n+}\n+\n+/*\n+** testFun8:\n+** ...\n+**\tstcph\n+**\tstrb\tw[0-9]+, \\[x[0-9]+\\]\n+** ...\n+*/\n+void\n+testFun8 ()\n+{\n+ char item8 = 0;\n+ char* ptr8 = &item8;\n+ long test8 = 1;\n+\n+ __arm_atomic_store_with_hint (ptr8, test8, __ATOMIC_RELAXED, 2);\n+}\n+\n+/*\n+** testFun9:\n+** ...\n+**\tstcph\n+**\tstr\tw[0-9]+, \\[x[0-9]+\\]\n+** ...\n+*/\n+void\n+testFun9 ()\n+{\n+ int item9 = 0;\n+ int* ptr9 = &item9;\n+ float test9 = 1;\n+\n+ __arm_atomic_store_with_hint (ptr9, test9, __ATOMIC_RELAXED, 2);\n+}\n+\n+/*\n+** testFun10:\n+** ...\n+**\tadd\t(x[0-9]+), \\1, 1\n+**\tmov\t(w[0-9]+), 7\n+**\tstcph\n+**\tstrb\t\\2, \\[\\1\\]\n+** ...\n+*/\n+static char buf[8];\n+void\n+testFun10 (void)\n+{\n+ __arm_atomic_store_with_hint((buf + 1), (char)7, __ATOMIC_RELAXED, 2);\n+}\n+\n+/*\n+** testFun11:\n+** ...\n+**\tstcph\n+**\tstr\twzr, \\[x[0-9]+\\]\n+** ...\n+*/\n+void\n+testFun11 ()\n+{\n+ int item11 = 10;\n+ int* ptr11 = &item11;\n+\n+ __arm_atomic_store_with_hint (ptr11, 0, __ATOMIC_RELAXED, 2);\n+}\ndiff --git a/gcc/testsuite/gcc.target/aarch64/atomic_store_with_stshh.c b/gcc/testsuite/gcc.target/aarch64/atomic_store_with_stshh.c\nindex 516a45aa781..3948ffcef28 100644\n--- a/gcc/testsuite/gcc.target/aarch64/atomic_store_with_stshh.c\n+++ b/gcc/testsuite/gcc.target/aarch64/atomic_store_with_stshh.c\n@@ -18,7 +18,7 @@ testFun1 ()\n char* ptr1 = &item1;\n char test1 = 1;\n \n- __atomic_store_with_stshh (ptr1, test1, __ATOMIC_RELAXED, 0);\n+ __arm_atomic_store_with_hint (ptr1, test1, __ATOMIC_RELAXED, 0);\n }\n \n /*\n@@ -34,7 +34,7 @@ testFun2 ()\n short item2 = 10;\n short* ptr2 = &item2;\n short test2 = 11;\n- __atomic_store_with_stshh (ptr2, test2, __ATOMIC_RELEASE, 0);\n+ __arm_atomic_store_with_hint (ptr2, test2, __ATOMIC_RELEASE, 0);\n }\n \n /*\n@@ -50,7 +50,7 @@ testFun3 ()\n unsigned int item3 = 10;\n unsigned int* ptr3 = &item3;\n unsigned int test3 = 11;\n- __atomic_store_with_stshh (ptr3, test3, __ATOMIC_SEQ_CST, 1);\n+ __arm_atomic_store_with_hint (ptr3, test3, __ATOMIC_SEQ_CST, 1);\n }\n \n /*\n@@ -66,7 +66,7 @@ testFun4 ()\n long item4 = 10;\n long* ptr4 = &item4;\n long test4 = 11;\n- __atomic_store_with_stshh (ptr4, test4, __ATOMIC_RELAXED, 1);\n+ __arm_atomic_store_with_hint (ptr4, test4, __ATOMIC_RELAXED, 1);\n }\n \n /*\n@@ -84,7 +84,7 @@ testFun5 ()\n long **ptr5 = &ptritem;\n long test5item = 11;\n long *test5 = &test5item;\n- __atomic_store_with_stshh (ptr5, test5, __ATOMIC_SEQ_CST, 0);\n+ __arm_atomic_store_with_hint (ptr5, test5, __ATOMIC_SEQ_CST, 0);\n }\n \n /*\n@@ -100,7 +100,7 @@ testFun6 ()\n float item6 = 10;\n float* ptr6 = &item6;\n float test6 = 11;\n- __atomic_store_with_stshh (ptr6, test6, __ATOMIC_SEQ_CST, 0);\n+ __arm_atomic_store_with_hint (ptr6, test6, __ATOMIC_SEQ_CST, 0);\n }\n \n /*\n@@ -116,7 +116,7 @@ testFun7 ()\n double item7 = 10;\n double* ptr7 = &item7;\n double test7 = 11;\n- __atomic_store_with_stshh (ptr7, test7, __ATOMIC_RELAXED, 1);\n+ __arm_atomic_store_with_hint (ptr7, test7, __ATOMIC_RELAXED, 1);\n }\n \n /*\n@@ -133,7 +133,7 @@ testFun8 ()\n char* ptr8 = &item8;\n long test8 = 1;\n \n- __atomic_store_with_stshh (ptr8, test8, __ATOMIC_RELAXED, 0);\n+ __arm_atomic_store_with_hint (ptr8, test8, __ATOMIC_RELAXED, 0);\n }\n \n /*\n@@ -150,7 +150,7 @@ testFun9 ()\n int* ptr9 = &item9;\n float test9 = 1;\n \n- __atomic_store_with_stshh (ptr9, test9, __ATOMIC_RELAXED, 1);\n+ __arm_atomic_store_with_hint (ptr9, test9, __ATOMIC_RELAXED, 1);\n }\n \n /*\n@@ -166,7 +166,7 @@ static char buf[8];\n void\n testFun10 (void)\n {\n- __atomic_store_with_stshh((buf + 1), (char)7, __ATOMIC_RELAXED, 1);\n+ __arm_atomic_store_with_hint((buf + 1), (char)7, __ATOMIC_RELAXED, 1);\n }\n \n /*\n@@ -182,5 +182,5 @@ testFun11 ()\n int item11 = 10;\n int* ptr11 = &item11;\n \n- __atomic_store_with_stshh (ptr11, 0, __ATOMIC_RELAXED, 1);\n+ __arm_atomic_store_with_hint (ptr11, 0, __ATOMIC_RELAXED, 1);\n }\n", "prefixes": [ "1/2" ] }