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GET /api/1.2/patches/2234294/?format=api
{ "id": 2234294, "url": "http://patchwork.ozlabs.org/api/1.2/patches/2234294/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/patch/20260507154557.2082697-4-kkartik@nvidia.com/", "project": { "id": 21, "url": "http://patchwork.ozlabs.org/api/1.2/projects/21/?format=api", "name": "Linux Tegra Development", "link_name": "linux-tegra", "list_id": "linux-tegra.vger.kernel.org", "list_email": "linux-tegra@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260507154557.2082697-4-kkartik@nvidia.com>", "list_archive_url": null, "date": "2026-05-07T15:45:56", "name": "[3/4] clocksource/drivers/timer-tegra186: Register all accessible watchdog timers", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "2f77ae6edc02dd473da68703367ed818f913f6ca", "submitter": { "id": 83016, "url": "http://patchwork.ozlabs.org/api/1.2/people/83016/?format=api", "name": "Kartik Rajput", "email": "kkartik@nvidia.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-tegra/patch/20260507154557.2082697-4-kkartik@nvidia.com/mbox/", "series": [ { "id": 503205, "url": "http://patchwork.ozlabs.org/api/1.2/series/503205/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/list/?series=503205", "date": "2026-05-07T15:45:55", "name": "Add support for Kernel WDT", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/503205/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2234294/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2234294/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-tegra+bounces-14293-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-tegra@vger.kernel.org" ], "Delivered-To": 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216.228.118.233 as permitted sender) receiver=protection.outlook.com;\n client-ip=216.228.118.233; helo=mail.nvidia.com; pr=C", "From": "Kartik Rajput <kkartik@nvidia.com>", "To": "<daniel.lezcano@kernel.org>, <tglx@kernel.org>, <wim@linux-watchdog.org>,\n\t<linux@roeck-us.net>, <thierry.reding@kernel.org>, <jonathanh@nvidia.com>,\n\t<kkartik@nvidia.com>, <linux-watchdog@vger.kernel.org>,\n\t<linux-kernel@vger.kernel.org>, <linux-tegra@vger.kernel.org>", "Subject": "[PATCH 3/4] clocksource/drivers/timer-tegra186: Register all\n accessible watchdog timers", "Date": "Thu, 7 May 2026 21:15:56 +0530", "Message-ID": "<20260507154557.2082697-4-kkartik@nvidia.com>", "X-Mailer": "git-send-email 2.43.0", "In-Reply-To": "<20260507154557.2082697-1-kkartik@nvidia.com>", "References": "<20260507154557.2082697-1-kkartik@nvidia.com>", "Precedence": "bulk", "X-Mailing-List": "linux-tegra@vger.kernel.org", "List-Id": "<linux-tegra.vger.kernel.org>", "List-Subscribe": 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"\n\tCX6l4f2oua/bAHPYI07SIu4Krf6crHyNmu86KptexAJRuuInlCaYVNxvwLEAJT+eGgq6p1CCRTQpJ/Fglmwedjj3ljey1WnvQe6tu+t/En8Hxwqm5zlwxrQUfnnKUmNPKFgzLoFns4aFEjH+PwWZDCNRmmErpVDzXMDGNFW8KAVhNsAQ4vghOMwLzS4vzdupu6SzupxnYQdxCT+piI27Z+F2KvvI0tUBxf1YntW3xrYlkydxeQ4S6U2m4/BHwVQK4XoCt644CdyB1YQA9VKIcJZyux+RtWRVQPnLmnbFsIWooetAEJcCI3opKAjQq9FSRiRB6frRu/GaO2yDNGak763op4duajr7n7jpc+ciHlfOms5lM46OR4W85DoW0ONB+A4coGwCRcE0upKnfrDJ4s+kGc2HR3q6EC0Pf/5J6qa8MuZdKxAhygKnyprgn6mzOHrqe5TtaI6dpO7cG2ErtI5BklDB4G/WjVb5plPA3xaYX8Pow1/ABS0yi+fPz90PPRNaenzuCJAeKqNO/fhTn5HswjrzftfPnt1Ucm9lixbjarKZS0R6v9RjFJNLgH1v4J8Yj5fYe+tmJ/qPW7r7zCyNYItAQsiWYAgVpBpbhdjEm9O4zyrxq5qGfCEgmEtibGxH2aLmZWFPvcy2vFoXoJdcXEAOTKvogWRQA0H3bXdNIQJGiawojeur/jKMVSZJ6f50caCxNpMJa1DZjocDbXdXPFzTHAq6QKSSC7m8QagCubz0zCS9gofH9vI8kXsZqqsAX7OyBxzI5vRzt/9Y4Q==", "X-Forefront-Antispam-Report": "\n\tCIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(1800799024)(36860700016)(376014)(22082099003)(18002099003)(56012099003)(921020);DIR:OUT;SFP:1101;", "X-MS-Exchange-AntiSpam-MessageData-ChunkCount": "1", "X-MS-Exchange-AntiSpam-MessageData-0": "\n\twuPkPpOVZNLe3gbn47IcmBMb3p76xi2hMSklNtxF+vL3q94iTkjDQdWT2FEoUM+sZAIhRicsgqPPoo6oxafm3EmSbS9vnCUNsAnIFJ741T65jg/0NrsaAHwHhq5GLr8VQtcpfACuqCCGQiEgHejhpR9QX/8S8JUFwVQP2To2LsU1HIYiDHDaGYKim8EQQBJXnLEVMNw4sxvkGBF6haLyTVXJ4O7Ici079nUEKk8SGThhmLh7rPpc8y0tugXlyJ5Z0TrN1v3QzM6OeqOYbrKbGsq5L+pPTUPBE3omboxMD2ffbTdOES6cC45PgSz9p4JeTF5rP6s2EcgSl/etSrEK3LQ/b/8EFxHb/Rx44ko16au0Vjc4IIH30xqefjdRLToNY/3MqmhPMDldY0nSwHKkBJqkpRUE+hJYq5VUnCllkHTUFBXpI3nlZ5SwWXGnqCCe", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "07 May 2026 15:46:46.7523\n (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 9b34cdac-b0fd-41e7-9cba-08deac4fd88c", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n\tDM2PEPF00003FC9.namprd04.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "SJ0PR12MB5676" }, "content": "Tegra186+ SoCs expose multiple watchdog timers, but the driver only\nregisters WDT(0).\n\nIterate over num_wdts and, for each WDT, check the SCR (firewall) registers\nin the TKE block to determine whether Linux has read and write access.\nRegister the watchdogs that are accessible.\n\nSigned-off-by: Kartik Rajput <kkartik@nvidia.com>\n---\n drivers/clocksource/timer-tegra186.c | 61 +++++++++++++++++++++++-----\n 1 file changed, 50 insertions(+), 11 deletions(-)", "diff": "diff --git a/drivers/clocksource/timer-tegra186.c b/drivers/clocksource/timer-tegra186.c\nindex fd82a73ab2d2..dd1d1a0dd63e 100644\n--- a/drivers/clocksource/timer-tegra186.c\n+++ b/drivers/clocksource/timer-tegra186.c\n@@ -57,6 +57,13 @@\n #define WDTUR 0x00c\n #define WDTUR_UNLOCK_PATTERN 0x0000c45a\n \n+/* WDT security configuration registers */\n+#define WDTSCR(x)\t\t(0xf02c + (x) * 4)\n+#define WDTSCR_SEC_WEN\t\tBIT(28)\n+#define WDTSCR_SEC_REN\t\tBIT(27)\n+#define WDTSCR_SEC_G1W\t\tBIT(9)\n+#define WDTSCR_SEC_G1R\t\tBIT(1)\n+\n struct tegra186_timer_soc {\n \tunsigned int num_timers;\n \tunsigned int num_wdts;\n@@ -89,7 +96,7 @@ struct tegra186_timer {\n \tstruct device *dev;\n \tvoid __iomem *regs;\n \n-\tstruct tegra186_wdt *wdt;\n+\tstruct tegra186_wdt **wdts;\n \tstruct clocksource usec;\n \tstruct clocksource tsc;\n \tstruct clocksource osc;\n@@ -298,6 +305,23 @@ static const struct watchdog_ops tegra186_wdt_ops = {\n \t.get_timeleft = tegra186_wdt_get_timeleft,\n };\n \n+static bool tegra186_wdt_is_accessible(struct tegra186_timer *tegra, unsigned int index)\n+{\n+\tu32 value;\n+\n+\tvalue = readl_relaxed(tegra->regs + WDTSCR(index));\n+\n+\t/* Check OS write access if write blocking is enabled. */\n+\tif ((value & WDTSCR_SEC_WEN) && !(value & WDTSCR_SEC_G1W))\n+\t\treturn false;\n+\n+\t/* Check OS read access if read blocking is enabled. */\n+\tif ((value & WDTSCR_SEC_REN) && !(value & WDTSCR_SEC_G1R))\n+\t\treturn false;\n+\n+\treturn true;\n+}\n+\n static struct tegra186_wdt *tegra186_wdt_create(struct tegra186_timer *tegra,\n \t\t\t\t\t\tunsigned int index)\n {\n@@ -424,6 +448,7 @@ static int tegra186_timer_probe(struct platform_device *pdev)\n {\n \tstruct device *dev = &pdev->dev;\n \tstruct tegra186_timer *tegra;\n+\tunsigned int i;\n \tint err;\n \n \ttegra = devm_kzalloc(dev, sizeof(*tegra), GFP_KERNEL);\n@@ -442,12 +467,20 @@ static int tegra186_timer_probe(struct platform_device *pdev)\n \tif (err < 0)\n \t\treturn err;\n \n-\t/* create a watchdog using a preconfigured timer */\n-\ttegra->wdt = tegra186_wdt_create(tegra, 0);\n-\tif (IS_ERR(tegra->wdt)) {\n-\t\terr = PTR_ERR(tegra->wdt);\n-\t\tdev_err(dev, \"failed to create WDT: %d\\n\", err);\n-\t\treturn err;\n+\ttegra->wdts = devm_kcalloc(dev, tegra->soc->num_wdts, sizeof(*tegra->wdts), GFP_KERNEL);\n+\tif (!tegra->wdts)\n+\t\treturn -ENOMEM;\n+\n+\tfor (i = 0; i < tegra->soc->num_wdts; i++) {\n+\t\tif (!tegra186_wdt_is_accessible(tegra, i)) {\n+\t\t\tdev_warn(dev, \"WDT%u is not accessible\\n\", i);\n+\t\t\tcontinue;\n+\t\t}\n+\n+\t\ttegra->wdts[i] = tegra186_wdt_create(tegra, i);\n+\t\tif (IS_ERR(tegra->wdts[i]))\n+\t\t\treturn dev_err_probe(dev, PTR_ERR(tegra->wdts[i]),\n+\t\t\t\t\t \"failed to create WDT%u\\n\", i);\n \t}\n \n \terr = tegra186_timer_tsc_init(tegra);\n@@ -489,9 +522,12 @@ static void tegra186_timer_remove(struct platform_device *pdev)\n static int __maybe_unused tegra186_timer_suspend(struct device *dev)\n {\n \tstruct tegra186_timer *tegra = dev_get_drvdata(dev);\n+\tunsigned int i;\n \n-\tif (watchdog_active(&tegra->wdt->base))\n-\t\ttegra186_wdt_disable(tegra->wdt);\n+\tfor (i = 0; i < tegra->soc->num_wdts; i++) {\n+\t\tif (tegra->wdts[i] && watchdog_active(&tegra->wdts[i]->base))\n+\t\t\ttegra186_wdt_disable(tegra->wdts[i]);\n+\t}\n \n \treturn 0;\n }\n@@ -499,9 +535,12 @@ static int __maybe_unused tegra186_timer_suspend(struct device *dev)\n static int __maybe_unused tegra186_timer_resume(struct device *dev)\n {\n \tstruct tegra186_timer *tegra = dev_get_drvdata(dev);\n+\tunsigned int i;\n \n-\tif (watchdog_active(&tegra->wdt->base))\n-\t\ttegra186_wdt_enable(tegra->wdt);\n+\tfor (i = 0; i < tegra->soc->num_wdts; i++) {\n+\t\tif (tegra->wdts[i] && watchdog_active(&tegra->wdts[i]->base))\n+\t\t\ttegra186_wdt_enable(tegra->wdts[i]);\n+\t}\n \n \treturn 0;\n }\n", "prefixes": [ "3/4" ] }