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GET /api/1.2/patches/2234264/?format=api
{ "id": 2234264, "url": "http://patchwork.ozlabs.org/api/1.2/patches/2234264/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/patch/20260507135314.76817-2-clamor95@gmail.com/", "project": { "id": 21, "url": "http://patchwork.ozlabs.org/api/1.2/projects/21/?format=api", "name": "Linux Tegra Development", "link_name": "linux-tegra", "list_id": "linux-tegra.vger.kernel.org", "list_email": "linux-tegra@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260507135314.76817-2-clamor95@gmail.com>", "list_archive_url": null, "date": "2026-05-07T13:53:14", "name": "[v1,1/1,RESEND] clk: tegra: set up proper EMC clock implementation for Tegra114", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "9ff1e4b6a557d81ae3c73c53361c211738c2d632", "submitter": { "id": 84146, "url": "http://patchwork.ozlabs.org/api/1.2/people/84146/?format=api", "name": "Svyatoslav Ryhel", "email": "clamor95@gmail.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-tegra/patch/20260507135314.76817-2-clamor95@gmail.com/mbox/", "series": [ { "id": 503188, "url": "http://patchwork.ozlabs.org/api/1.2/series/503188/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/list/?series=503188", "date": "2026-05-07T13:53:13", "name": "clk: tegra: set up proper EMC clock implementation for Tegra114", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/503188/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2234264/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2234264/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-tegra+bounces-14290-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-tegra@vger.kernel.org" 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<pgaikwad@nvidia.com>,\n\tMichael Turquette <mturquette@baylibre.com>,\n\tStephen Boyd <sboyd@kernel.org>,\n\tThierry Reding <thierry.reding@kernel.org>,\n\tThierry Reding <treding@nvidia.com>,\n\tJonathan Hunter <jonathanh@nvidia.com>,\n\tMikko Perttunen <mperttunen@nvidia.com>,\n\tSvyatoslav Ryhel <clamor95@gmail.com>", "Cc": "linux-clk@vger.kernel.org,\n\tlinux-tegra@vger.kernel.org,\n\tlinux-kernel@vger.kernel.org", "Subject": "[PATCH v1 1/1 RESEND] clk: tegra: set up proper EMC clock\n implementation for Tegra114", "Date": "Thu, 7 May 2026 16:53:14 +0300", "Message-ID": "<20260507135314.76817-2-clamor95@gmail.com>", "X-Mailer": "git-send-email 2.51.0", "In-Reply-To": "<20260507135314.76817-1-clamor95@gmail.com>", "References": "<20260507135314.76817-1-clamor95@gmail.com>", "Precedence": "bulk", "X-Mailing-List": "linux-tegra@vger.kernel.org", "List-Id": "<linux-tegra.vger.kernel.org>", "List-Subscribe": "<mailto:linux-tegra+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-tegra+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit" }, "content": "Remove current emc and emc_mux clocks and replace them with the proper EMC\nclock implementation for correct EMC driver support.\n\nAcked-by: Thierry Reding <treding@nvidia.com>\nSigned-off-by: Svyatoslav Ryhel <clamor95@gmail.com>\nReviewed-by: Mikko Perttunen <mperttunen@nvidia.com>\n---\n drivers/clk/tegra/clk-tegra114.c | 39 ++++++++++++++++++++------------\n 1 file changed, 25 insertions(+), 14 deletions(-)", "diff": "diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c\nindex 8bde72aa5e68..853ef707654a 100644\n--- a/drivers/clk/tegra/clk-tegra114.c\n+++ b/drivers/clk/tegra/clk-tegra114.c\n@@ -622,10 +622,6 @@ static const char *mux_plld_out0_plld2_out0[] = {\n };\n #define mux_plld_out0_plld2_out0_idx NULL\n \n-static const char *mux_pllmcp_clkm[] = {\n-\t\"pll_m_out0\", \"pll_c_out0\", \"pll_p_out0\", \"clk_m\", \"pll_m_ud\",\n-};\n-\n static const struct clk_div_table pll_re_div_table[] = {\n \t{ .val = 0, .div = 1 },\n \t{ .val = 1, .div = 2 },\n@@ -672,7 +668,6 @@ static struct tegra_clk tegra114_clks[tegra_clk_max] __initdata = {\n \t[tegra_clk_csi] = { .dt_id = TEGRA114_CLK_CSI, .present = true },\n \t[tegra_clk_i2c2] = { .dt_id = TEGRA114_CLK_I2C2, .present = true },\n \t[tegra_clk_uartc] = { .dt_id = TEGRA114_CLK_UARTC, .present = true },\n-\t[tegra_clk_emc] = { .dt_id = TEGRA114_CLK_EMC, .present = true },\n \t[tegra_clk_usb2] = { .dt_id = TEGRA114_CLK_USB2, .present = true },\n \t[tegra_clk_usb3] = { .dt_id = TEGRA114_CLK_USB3, .present = true },\n \t[tegra_clk_vde_8] = { .dt_id = TEGRA114_CLK_VDE, .present = true },\n@@ -1048,14 +1043,7 @@ static __init void tegra114_periph_clk_init(void __iomem *clk_base,\n \t\t\t\t\t 0, 82, periph_clk_enb_refcnt);\n \tclks[TEGRA114_CLK_DSIB] = clk;\n \n-\t/* emc mux */\n-\tclk = clk_register_mux(NULL, \"emc_mux\", mux_pllmcp_clkm,\n-\t\t\t ARRAY_SIZE(mux_pllmcp_clkm),\n-\t\t\t CLK_SET_RATE_NO_REPARENT,\n-\t\t\t clk_base + CLK_SOURCE_EMC,\n-\t\t\t 29, 3, 0, &emc_lock);\n-\n-\tclk = tegra_clk_register_mc(\"mc\", \"emc_mux\", clk_base + CLK_SOURCE_EMC,\n+\tclk = tegra_clk_register_mc(\"mc\", \"emc\", clk_base + CLK_SOURCE_EMC,\n \t\t\t\t &emc_lock);\n \tclks[TEGRA114_CLK_MC] = clk;\n \n@@ -1321,6 +1309,26 @@ static int tegra114_reset_deassert(unsigned long id)\n \treturn 0;\n }\n \n+static struct clk *tegra114_clk_src_onecell_get(struct of_phandle_args *clkspec,\n+\t\t\t\t\t\tvoid *data)\n+{\n+\tstruct clk_hw *hw;\n+\tstruct clk *clk;\n+\n+\tclk = of_clk_src_onecell_get(clkspec, data);\n+\tif (IS_ERR(clk))\n+\t\treturn clk;\n+\n+\thw = __clk_get_hw(clk);\n+\n+\tif (clkspec->args[0] == TEGRA114_CLK_EMC) {\n+\t\tif (!tegra124_clk_emc_driver_available(hw))\n+\t\t\treturn ERR_PTR(-EPROBE_DEFER);\n+\t}\n+\n+\treturn clk;\n+}\n+\n static void __init tegra114_clock_init(struct device_node *np)\n {\n \tstruct device_node *node;\n@@ -1368,7 +1376,10 @@ static void __init tegra114_clock_init(struct device_node *np)\n \ttegra_init_special_resets(1, tegra114_reset_assert,\n \t\t\t\t tegra114_reset_deassert);\n \n-\ttegra_add_of_provider(np, of_clk_src_onecell_get);\n+\ttegra_add_of_provider(np, tegra114_clk_src_onecell_get);\n+\tclks[TEGRA114_CLK_EMC] = tegra124_clk_register_emc(clk_base, np,\n+\t\t\t\t\t\t\t &emc_lock);\n+\n \ttegra_register_devclks(devclks, ARRAY_SIZE(devclks));\n \n \ttegra_clk_apply_init_table = tegra114_clock_apply_init_table;\n", "prefixes": [ "v1", "1/1", "RESEND" ] }