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GET /api/1.2/patches/2234259/?format=api
{ "id": 2234259, "url": "http://patchwork.ozlabs.org/api/1.2/patches/2234259/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260507134709.70507-2-philmd@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.2/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260507134709.70507-2-philmd@linaro.org>", "list_archive_url": null, "date": "2026-05-07T13:47:08", "name": "[1/2] target/arm: Rename Aarch64-specific methods", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "75db4cbf7bbf82c77dfb70aedc2af59be2d6e421", "submitter": { "id": 85046, "url": "http://patchwork.ozlabs.org/api/1.2/people/85046/?format=api", "name": "Philippe Mathieu-Daudé", "email": "philmd@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260507134709.70507-2-philmd@linaro.org/mbox/", "series": [ { "id": 503185, "url": "http://patchwork.ozlabs.org/api/1.2/series/503185/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=503185", "date": "2026-05-07T13:47:07", "name": "target/arm: Extract IDAU interface to its own unit", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/503185/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2234259/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2234259/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=yC7eqW3l;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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charset=UTF-8", "Content-Transfer-Encoding": "8bit", "Received-SPF": "pass client-ip=2a00:1450:4864:20::336;\n envelope-from=philmd@linaro.org; helo=mail-wm1-x336.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "Various Aarch64 specific methods start with the 'aarch64_'\nprefix. Rename few more emphasizing Aarch64 specific features.\n\nSigned-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>\n---\n target/arm/internals.h | 8 ++++----\n target/arm/cpu.c | 8 ++++----\n target/arm/cpu32-stubs.c | 8 ++++----\n target/arm/cpu64.c | 12 ++++++------\n 4 files changed, 18 insertions(+), 18 deletions(-)", "diff": "diff --git a/target/arm/internals.h b/target/arm/internals.h\nindex a632584a4e0..27b284f17b9 100644\n--- a/target/arm/internals.h\n+++ b/target/arm/internals.h\n@@ -1746,10 +1746,10 @@ int aarch64_gdb_get_tag_ctl_reg(CPUState *cs, GByteArray *buf, int reg);\n int aarch64_gdb_set_tag_ctl_reg(CPUState *cs, uint8_t *buf, int reg);\n int aarch64_gdb_get_tls_reg(CPUState *cs, GByteArray *buf, int reg);\n int aarch64_gdb_set_tls_reg(CPUState *cs, uint8_t *buf, int reg);\n-void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp);\n-void arm_cpu_sme_finalize(ARMCPU *cpu, Error **errp);\n-void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp);\n-void arm_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp);\n+void aarch64_cpu_sve_finalize(ARMCPU *cpu, Error **errp);\n+void aarch64_cpu_sme_finalize(ARMCPU *cpu, Error **errp);\n+void aarch64_cpu_pauth_finalize(ARMCPU *cpu, Error **errp);\n+void aarch64_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp);\n void aarch64_max_tcg_initfn(Object *obj);\n void aarch64_add_pauth_properties(Object *obj);\n void aarch64_add_sve_properties(Object *obj);\ndiff --git a/target/arm/cpu.c b/target/arm/cpu.c\nindex 10feb639c4d..d670ffe4de0 100644\n--- a/target/arm/cpu.c\n+++ b/target/arm/cpu.c\n@@ -1682,25 +1682,25 @@ void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp)\n Error *local_err = NULL;\n \n if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {\n- arm_cpu_sve_finalize(cpu, &local_err);\n+ aarch64_cpu_sve_finalize(cpu, &local_err);\n if (local_err != NULL) {\n error_propagate(errp, local_err);\n return;\n }\n \n- arm_cpu_sme_finalize(cpu, &local_err);\n+ aarch64_cpu_sme_finalize(cpu, &local_err);\n if (local_err != NULL) {\n error_propagate(errp, local_err);\n return;\n }\n \n- arm_cpu_pauth_finalize(cpu, &local_err);\n+ aarch64_cpu_pauth_finalize(cpu, &local_err);\n if (local_err != NULL) {\n error_propagate(errp, local_err);\n return;\n }\n \n- arm_cpu_lpa2_finalize(cpu, &local_err);\n+ aarch64_cpu_lpa2_finalize(cpu, &local_err);\n if (local_err != NULL) {\n error_propagate(errp, local_err);\n return;\ndiff --git a/target/arm/cpu32-stubs.c b/target/arm/cpu32-stubs.c\nindex 9e50bb1b0b5..d42b1a5d6a6 100644\n--- a/target/arm/cpu32-stubs.c\n+++ b/target/arm/cpu32-stubs.c\n@@ -4,22 +4,22 @@\n #include \"target/arm/cpu.h\"\n #include \"target/arm/internals.h\"\n \n-void arm_cpu_sme_finalize(ARMCPU *cpu, Error **errp)\n+void aarch64_cpu_sme_finalize(ARMCPU *cpu, Error **errp)\n {\n g_assert_not_reached();\n }\n \n-void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp)\n+void aarch64_cpu_sve_finalize(ARMCPU *cpu, Error **errp)\n {\n g_assert_not_reached();\n }\n \n-void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp)\n+void aarch64_cpu_pauth_finalize(ARMCPU *cpu, Error **errp)\n {\n g_assert_not_reached();\n }\n \n-void arm_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp)\n+void aarch64_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp)\n {\n g_assert_not_reached();\n }\ndiff --git a/target/arm/cpu64.c b/target/arm/cpu64.c\nindex a93ad2da5ad..b38a78aac3f 100644\n--- a/target/arm/cpu64.c\n+++ b/target/arm/cpu64.c\n@@ -60,7 +60,7 @@ int get_sysreg_idx(ARMSysRegs sysreg)\n \n #undef DEF\n \n-void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp)\n+void aarch64_cpu_sve_finalize(ARMCPU *cpu, Error **errp)\n {\n /*\n * If any vector lengths are explicitly enabled with sve<N> properties,\n@@ -121,7 +121,7 @@ void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp)\n * Disable all SVE extensions as well. Note that some ZFR0\n * fields are used also by SME so must not be wiped in\n * an SME-no-SVE config. We will clear the rest in\n- * arm_cpu_sme_finalize() if necessary.\n+ * aarch_cpu_sme_finalize() if necessary.\n */\n FIELD_DP64_IDREG(&cpu->isar, ID_AA64ZFR0, F64MM, 0);\n FIELD_DP64_IDREG(&cpu->isar, ID_AA64ZFR0, F32MM, 0);\n@@ -336,7 +336,7 @@ static void cpu_arm_set_sve(Object *obj, bool value, Error **errp)\n FIELD_DP64_IDREG(&cpu->isar, ID_AA64PFR0, SVE, value);\n }\n \n-void arm_cpu_sme_finalize(ARMCPU *cpu, Error **errp)\n+void aarch64_cpu_sme_finalize(ARMCPU *cpu, Error **errp)\n {\n uint32_t vq_map = cpu->sme_vq.map;\n uint32_t vq_init = cpu->sme_vq.init;\n@@ -408,7 +408,7 @@ static void cpu_arm_set_sme(Object *obj, bool value, Error **errp)\n /*\n * For now, write 0 for \"off\" and 1 for \"on\" into the PFR1 field.\n * We will correct this value to report the right SME\n- * level (SME vs SME2) in arm_cpu_sme_finalize() later.\n+ * level (SME vs SME2) in aarch_cpu_sme_finalize() later.\n */\n FIELD_DP64_IDREG(&cpu->isar, ID_AA64PFR1, SME, value);\n }\n@@ -548,7 +548,7 @@ void aarch64_add_sme_properties(Object *obj)\n #endif\n }\n \n-void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp)\n+void aarch64_cpu_pauth_finalize(ARMCPU *cpu, Error **errp)\n {\n ARMPauthFeature features = cpu_isar_feature(pauth_feature, cpu);\n ARMISARegisters *isar = &cpu->isar;\n@@ -666,7 +666,7 @@ void aarch64_add_pauth_properties(Object *obj)\n }\n }\n \n-void arm_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp)\n+void aarch64_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp)\n {\n uint64_t t;\n \n", "prefixes": [ "1/2" ] }