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GET /api/1.2/patches/2233282/?format=api
{ "id": 2233282, "url": "http://patchwork.ozlabs.org/api/1.2/patches/2233282/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260506033642.3641390-5-jim.shu@sifive.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.2/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260506033642.3641390-5-jim.shu@sifive.com>", "list_archive_url": null, "date": "2026-05-06T03:36:41", "name": "[v3,4/5] accel/tcg: Add IOMMU lazy translation function", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "fef0c9308bfc9801f136974a53149b9235df6e77", "submitter": { "id": 83153, "url": "http://patchwork.ozlabs.org/api/1.2/people/83153/?format=api", "name": "Jim Shu", "email": "jim.shu@sifive.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260506033642.3641390-5-jim.shu@sifive.com/mbox/", "series": [ { "id": 502923, "url": "http://patchwork.ozlabs.org/api/1.2/series/502923/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=502923", "date": "2026-05-06T03:36:39", "name": "Defer the IOMMU translation in the CPU path and support access_type", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/502923/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2233282/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2233282/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=sifive.com header.i=@sifive.com header.a=rsa-sha256\n header.s=google header.b=noQsmFbV;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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Iglesias\" <edgar.iglesias@gmail.com>,\n Aurelien Jarno <aurelien@aurel32.net>, Jiaxun Yang <jiaxun.yang@flygoat.com>,\n Aleksandar Rikalo <arikalo@gmail.com>, Stafford Horne <shorne@gmail.com>,\n Nicholas Piggin <npiggin@gmail.com>, Chinmay Rath <rathc@linux.ibm.com>,\n Glenn Miles <milesg@linux.ibm.com>, Palmer Dabbelt <palmer@dabbelt.com>,\n Alistair Francis <alistair.francis@wdc.com>, Weiwei Li <liwei1518@gmail.com>,\n Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>,\n Liu Zhiwei <zhiwei_liu@linux.alibaba.com>,\n Chao Liu <chao.liu.zevorn@gmail.com>,\n Yoshinori Sato <yoshinori.sato@nifty.com>,\n Ilya Leoshkevich <iii@linux.ibm.com>, David Hildenbrand <david@kernel.org>,\n Cornelia Huck <cohuck@redhat.com>, Eric Farman <farman@linux.ibm.com>,\n Matthew Rosato <mjrosato@linux.ibm.com>,\n Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>,\n Artyom Tarasenko <atar4qemu@gmail.com>, Max Filippov <jcmvbkbc@gmail.com>,\n qemu-ppc@nongnu.org (open list:PowerPC TCG CPUs),\n qemu-s390x@nongnu.org (open list:S390 TCG CPUs),\n Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>,\n Mark Burton <mburton@qti.qualcomm.com>,\n Peter Maydell <peter.maydell@linaro.org>, Jim Shu <jim.shu@sifive.com>", "Subject": "[PATCH v3 4/5] accel/tcg: Add IOMMU lazy translation function", "Date": "Wed, 6 May 2026 11:36:41 +0800", "Message-ID": "<20260506033642.3641390-5-jim.shu@sifive.com>", "X-Mailer": "git-send-email 2.43.0", "In-Reply-To": "<20260506033642.3641390-1-jim.shu@sifive.com>", "References": "<20260506033642.3641390-1-jim.shu@sifive.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Received-SPF": "pass client-ip=2607:f8b0:4864:20::62a;\n envelope-from=jim.shu@sifive.com; helo=mail-pl1-x62a.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "The lazy translation will translate IOMMU regions of the specific\naccess_type and store the result into the CPUTLBEntryFull.\n\nFor CPUTLBEntry, lazy translation may update 'addend' and 'addr_idx'\narray. We restrict IOMMU region to have a single non-zero 'addend'\nacross all permissions. Also, lazy translation only updates the\n'addr_idx' for the permissions specified in @prot.\n\nSigned-off-by: Jim Shu <jim.shu@sifive.com>\nAcked-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>\n---\n accel/tcg/cputlb.c | 168 ++++++++++++++++++++++++++++++++++++++++++\n include/hw/core/cpu.h | 15 ++++\n 2 files changed, 183 insertions(+)", "diff": "diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c\nindex f0c049e1551..5735f632896 100644\n--- a/accel/tcg/cputlb.c\n+++ b/accel/tcg/cputlb.c\n@@ -1272,6 +1272,174 @@ static inline void cpu_unaligned_access(CPUState *cpu, vaddr addr,\n mmu_idx, retaddr);\n }\n \n+/*\n+ * Perform lazy IOMMU translation for a CPUTLBEntry/CPUTLBEntryFull.\n+ * This is called when CPU utilize the TLB entry in the slow path.\n+ * Updates both entry and full entry to IOMMU translated data for the\n+ * specific access type.\n+ */\n+static void\n+tlb_translate_iommu(CPUState *cpu, int mmu_idx,\n+ vaddr addr, MMUAccessType access_type,\n+ CPUTLBEntryFull *full)\n+{\n+ CPUTLB *tlb = &cpu->neg.tlb;\n+ MemoryRegionSection *section;\n+ unsigned int read_flags, write_flags;\n+ uintptr_t addend;\n+ CPUTLBEntry *te;\n+ hwaddr iotlb, xlat, sz, paddr_page;\n+ vaddr addr_page;\n+ int asidx, wp_flags, prot;\n+ bool is_ram, is_romd;\n+\n+ if (!full->is_iommu || (full->iommu_last_at == access_type)) {\n+ return;\n+ }\n+\n+ assert_cpu_is_self(cpu);\n+\n+ if (full->lg_page_size <= TARGET_PAGE_BITS) {\n+ sz = TARGET_PAGE_SIZE;\n+ } else {\n+ sz = (hwaddr)1 << full->lg_page_size;\n+ tlb_add_large_page(cpu, mmu_idx, addr, sz);\n+ }\n+ addr_page = addr & TARGET_PAGE_MASK;\n+ paddr_page = full->phys_addr & TARGET_PAGE_MASK;\n+\n+ prot = full->prot;\n+ asidx = cpu_asidx_from_attrs(cpu, full->attrs);\n+\n+ section = address_space_translate_for_iotlb_late(cpu, asidx, paddr_page,\n+ &xlat, &sz, full->attrs,\n+ &prot, access_type);\n+\n+ assert(sz >= TARGET_PAGE_SIZE);\n+\n+ tlb_debug(\"vaddr=%016\" VADDR_PRIx \" paddr=0x\" HWADDR_FMT_plx\n+ \" prot=%x idx=%d\\n\",\n+ addr, full->phys_addr, prot, mmu_idx);\n+\n+ is_ram = memory_region_is_ram(section->mr);\n+ is_romd = memory_region_is_romd(section->mr);\n+\n+ read_flags = full->tlb_fill_flags;\n+ if (full->lg_page_size < TARGET_PAGE_BITS) {\n+ /* Repeat the MMU check and TLB fill on every access. */\n+ read_flags |= TLB_INVALID_MASK;\n+ }\n+\n+ if (is_ram || is_romd) {\n+ /* RAM and ROMD both have associated host memory. */\n+ addend = (uintptr_t)memory_region_get_ram_ptr(section->mr) + xlat;\n+ } else {\n+ /* I/O and IOMMU does not; force the host address to NULL. */\n+ addend = 0;\n+ }\n+\n+ write_flags = read_flags;\n+\n+ if (is_ram) {\n+ iotlb = memory_region_get_ram_addr(section->mr) + xlat;\n+ assert(!(iotlb & ~TARGET_PAGE_MASK));\n+ /*\n+ * Computing is_clean is expensive; avoid all that unless\n+ * the page is actually writable.\n+ */\n+ if (prot & PAGE_WRITE) {\n+ if (section->readonly) {\n+ write_flags |= TLB_DISCARD_WRITE;\n+ } else if (physical_memory_is_clean(iotlb)) {\n+ write_flags |= TLB_NOTDIRTY;\n+ }\n+ }\n+ } else {\n+ /* I/O or ROMD */\n+ iotlb = xlat;\n+ /*\n+ * Writes to romd devices must go through MMIO to enable write.\n+ * Reads to romd devices go through the ram_ptr found above,\n+ * but of course reads to I/O must go through MMIO.\n+ */\n+ write_flags |= TLB_MMIO;\n+ if (!is_romd) {\n+ read_flags = write_flags;\n+ }\n+ }\n+\n+ wp_flags = cpu_watchpoint_address_matches(cpu, addr_page,\n+ TARGET_PAGE_SIZE);\n+\n+ /* Update the CPUTLBEntryFull for this access type. */\n+ full->iommu_last_at = access_type;\n+ full->xlat_offset = iotlb - addr_page;\n+ full->section = section;\n+ full->phys_addr = paddr_page;\n+\n+ /* Update the CPUTLBEntry: addend and addr_idx */\n+ tlb = &cpu->neg.tlb;\n+ te = tlb_entry(cpu, mmu_idx, addr_page);\n+\n+ qemu_spin_lock(&tlb->c.lock);\n+\n+ /*\n+ * If IOMMU region is translated to the memories (has associated\n+ * host memory), it will update the 'addend' to access memories in the\n+ * fast path. Otherwise, IO region do not update the 'addend' because\n+ * it might be already used by memory region from the other permissions.\n+ * It is fine since IO region do not use addend.\n+ */\n+ if (is_ram || is_romd) {\n+ if (te->addend + addr_page) {\n+ /* addend of untranslated IOMMU region is 0 - addr_page. */\n+\n+ /*\n+ * CPUTLBEntry only has 1 addend across all permissions.\n+ * We don't support the IOMMUMemoryRegion to be translated to\n+ * 2 different host memories from the different permissions.\n+ * QEMU will trigger an assertion for such case.\n+ */\n+ g_assert(addend == te->addend + addr_page);\n+ } else {\n+ te->addend = addend - addr_page;\n+ }\n+ }\n+\n+ /*\n+ * In the IOMMU lazy translation, we only update TLB flags for the\n+ * permissions specified in @prot. For other permissions, we still\n+ * keep the original TLB flags (e.g. TLB_IOMMU if not translated).\n+ */\n+ if (prot & PAGE_EXEC) {\n+ tlb_set_compare(full, te, addr_page, read_flags,\n+ MMU_INST_FETCH, prot & PAGE_EXEC);\n+ }\n+\n+ if (wp_flags & BP_MEM_READ) {\n+ read_flags |= TLB_WATCHPOINT;\n+ }\n+ if (prot & PAGE_READ) {\n+ tlb_set_compare(full, te, addr_page, read_flags,\n+ MMU_DATA_LOAD, prot & PAGE_READ);\n+ }\n+\n+ if (prot & PAGE_WRITE_INV) {\n+ write_flags |= TLB_INVALID_MASK;\n+ }\n+ if (wp_flags & BP_MEM_WRITE) {\n+ write_flags |= TLB_WATCHPOINT;\n+ }\n+ if (prot & PAGE_WRITE) {\n+ tlb_set_compare(full, te, addr_page, write_flags,\n+ MMU_DATA_STORE, prot & PAGE_WRITE);\n+ }\n+\n+ qemu_spin_unlock(&tlb->c.lock);\n+\n+ return;\n+}\n+\n static MemoryRegionSection *\n io_prepare(hwaddr *out_offset, CPUState *cpu, CPUTLBEntryFull *full,\n vaddr addr, uintptr_t retaddr)\ndiff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h\nindex 207a7a1becb..cfbce50d1c5 100644\n--- a/include/hw/core/cpu.h\n+++ b/include/hw/core/cpu.h\n@@ -254,6 +254,21 @@ struct CPUTLBEntryFull {\n */\n uint8_t slow_flags[MMU_ACCESS_COUNT];\n \n+ /*\n+ * @is_iommu indicates if the MemoryRegion is an IOMMU.\n+ * When true, IOMMU translation is deferred until the entry is used.\n+ */\n+ bool is_iommu;\n+\n+ /*\n+ * @iommu_last_at contains the access_type of last IOMMU translation.\n+ * It means that this entry currently stores the translated data of\n+ * IOMMU region with this access_type.\n+ * When it is MMU_ACCESS_COUNT, the entry stores untranslated data of\n+ * IOMMU region.\n+ */\n+ MMUAccessType iommu_last_at;\n+\n /*\n * Allow target-specific additions to this structure.\n * This may be used to cache items from the guest cpu\n", "prefixes": [ "v3", "4/5" ] }