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GET /api/1.2/patches/2233143/?format=api
{ "id": 2233143, "url": "http://patchwork.ozlabs.org/api/1.2/patches/2233143/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260505185028.237207-6-dblanzeanu@linux.microsoft.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.2/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260505185028.237207-6-dblanzeanu@linux.microsoft.com>", "list_archive_url": null, "date": "2026-05-05T18:50:26", "name": "[v2,5/7] target/i386/mshv: use the register page to get registers", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "960630f87a09fa21c92250c176ae801e552a4c3d", "submitter": { "id": 93106, "url": "http://patchwork.ozlabs.org/api/1.2/people/93106/?format=api", "name": "Doru Blânzeanu", "email": "dblanzeanu@linux.microsoft.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260505185028.237207-6-dblanzeanu@linux.microsoft.com/mbox/", "series": [ { "id": 502882, "url": "http://patchwork.ozlabs.org/api/1.2/series/502882/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=502882", "date": "2026-05-05T18:50:22", "name": "target/i386/mshv: use hv_vp_register_page for fast register access", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/502882/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2233143/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2233143/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=linux.microsoft.com header.i=@linux.microsoft.com\n header.a=rsa-sha256 header.s=default header.b=JQMjRLm4;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g97045X8Vz1yJx\n\tfor <incoming@patchwork.ozlabs.org>; Wed, 06 May 2026 04:51:32 +1000 (AEST)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1wKKr7-0000gZ-2y; Tue, 05 May 2026 14:50:53 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <dblanzeanu@linux.microsoft.com>)\n id 1wKKr5-0000fp-Le\n for qemu-devel@nongnu.org; Tue, 05 May 2026 14:50:51 -0400", "from linux.microsoft.com ([13.77.154.182])\n by eggs.gnu.org with esmtp (Exim 4.90_1)\n (envelope-from <dblanzeanu@linux.microsoft.com>) id 1wKKr2-0006jT-OO\n for qemu-devel@nongnu.org; Tue, 05 May 2026 14:50:51 -0400", "from laptop.localdomain (unknown [86.121.140.248])\n by linux.microsoft.com (Postfix) with ESMTPSA id 4B23120B7168;\n Tue, 5 May 2026 11:50:43 -0700 (PDT)" ], "DKIM-Filter": "OpenDKIM Filter v2.11.0 linux.microsoft.com 4B23120B7168", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.microsoft.com;\n s=default; t=1778007044;\n bh=hJxydqpkaxAkHgGCUh/fsgKB/bQh6BDju7BvGawDrFA=;\n h=From:To:Cc:Subject:Date:In-Reply-To:References:From;\n b=JQMjRLm4xmFoZenodmwBneojEJoWS9XVrugZBK6hLPl0+bIIA6Tm1hx7eGrq0Mi7g\n 0o55AQ7pNJVIb0uZGMsEtcLCrDYmR8fYu4wTg3hKOzoVeVtVEH5os7OlmXtHsnOoZc\n 4WNd5oeJ9mbihetNaSTb8Q+bBFNdrHf65oWHpra0=", "From": "=?utf-8?q?Doru_Bl=C3=A2nzeanu?= <dblanzeanu@linux.microsoft.com>", "To": "qemu-devel@nongnu.org", "Cc": "=?utf-8?q?Doru_Bl=C3=A2nzeanu?= <dblanzeanu@linux.microsoft.com>,\n Magnus Kulke <magnuskulke@linux.microsoft.com>,\n Zhao Liu <zhao1.liu@intel.com>, Wei Liu <wei.liu@kernel.org>,\n Paolo Bonzini <pbonzini@redhat.com>", "Subject": "[PATCH v2 5/7] target/i386/mshv: use the register page to get\n registers", "Date": "Tue, 5 May 2026 21:50:26 +0300", "Message-ID": "<20260505185028.237207-6-dblanzeanu@linux.microsoft.com>", "X-Mailer": "git-send-email 2.53.0", "In-Reply-To": "<20260505185028.237207-1-dblanzeanu@linux.microsoft.com>", "References": "<20260505185028.237207-1-dblanzeanu@linux.microsoft.com>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=UTF-8", "Content-Transfer-Encoding": "8bit", "Received-SPF": "pass client-ip=13.77.154.182;\n envelope-from=dblanzeanu@linux.microsoft.com; helo=linux.microsoft.com", "X-Spam_score_int": "-19", "X-Spam_score": "-2.0", "X-Spam_bar": "--", "X-Spam_report": "(-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, RCVD_IN_DNSWL_NONE=-0.0001,\n SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "Change the mshv_load_regs to use the register page when it is mmapped\nand is valid.\nOtherwise use the existing logic that uses ioctls to fetch registers.\n\nWhen retrieving the special registers, there are some registers that are\nnot present in the register page: TR, LDTR, GDTR, IDTR, CR2, APIC_BASE.\nAs this registers are not likely to be used in an MMIO/PIO operation,\nand to avoid a hypercall overhead we do not retrieve them.\n\nLocal testing showed no regression when using this logic. To properly\nretrieve all the necessary registers for each decoded operation implies\nhaving a mechanism that tracks the state of each register, which is\nbeyond the scope of this patch series.\n\nSigned-off-by: Doru Blânzeanu <dblanzeanu@linux.microsoft.com>\n---\n target/i386/mshv/mshv-cpu.c | 99 +++++++++++++++++++++++++++++++++----\n 1 file changed, 90 insertions(+), 9 deletions(-)", "diff": "diff --git a/target/i386/mshv/mshv-cpu.c b/target/i386/mshv/mshv-cpu.c\nindex 3a3c269c33..c84d3f76de 100644\n--- a/target/i386/mshv/mshv-cpu.c\n+++ b/target/i386/mshv/mshv-cpu.c\n@@ -401,6 +401,80 @@ static void populate_special_regs(const hv_register_assoc *assocs,\n cpu_set_apic_base(x86cpu->apic_state, assocs[16].value.reg64);\n }\n \n+static void mshv_get_standard_regs_vp_page(CPUState *cpu)\n+{\n+ X86CPU *x86cpu = X86_CPU(cpu);\n+ CPUX86State *env = &x86cpu->env;\n+\n+ /* General Purpose Registers */\n+ env->regs[R_EAX] = env->regs_page->rax;\n+ env->regs[R_EBX] = env->regs_page->rbx;\n+ env->regs[R_ECX] = env->regs_page->rcx;\n+ env->regs[R_EDX] = env->regs_page->rdx;\n+ env->regs[R_ESI] = env->regs_page->rsi;\n+ env->regs[R_EDI] = env->regs_page->rdi;\n+ env->regs[R_ESP] = env->regs_page->rsp;\n+ env->regs[R_EBP] = env->regs_page->rbp;\n+ env->regs[R_R8] = env->regs_page->r8;\n+ env->regs[R_R9] = env->regs_page->r9;\n+ env->regs[R_R10] = env->regs_page->r10;\n+ env->regs[R_R11] = env->regs_page->r11;\n+ env->regs[R_R12] = env->regs_page->r12;\n+ env->regs[R_R13] = env->regs_page->r13;\n+ env->regs[R_R14] = env->regs_page->r14;\n+ env->regs[R_R15] = env->regs_page->r15;\n+\n+ env->eip = env->regs_page->rip;\n+ env->eflags = env->regs_page->rflags;\n+ rflags_to_lflags(env);\n+}\n+\n+/*\n+ * This function synchronizes the special registers present in the\n+ * register vp page, which are not all the special registers.\n+ * The rest of the special registers (LD, TR, GDT, IDT, CR2, APIC_BASE)\n+ * are not synchronized to avoid the overhead of a hypercall.\n+ *\n+ * These special registers are not normally used by the guest,\n+ * and are only used in some specific cases.\n+ */\n+static void mshv_get_special_regs_vp_page(CPUState *cpu)\n+{\n+ X86CPU *x86cpu = X86_CPU(cpu);\n+ CPUX86State *env = &x86cpu->env;\n+ hv_x64_segment_register seg;\n+\n+ /* Populate special registers that are in the VP register page */\n+ env->cr[0] = env->regs_page->cr0;\n+ env->cr[3] = env->regs_page->cr3;\n+ env->cr[4] = env->regs_page->cr4;\n+ env->efer = env->regs_page->efer;\n+ cpu_set_apic_tpr(x86cpu->apic_state, env->regs_page->cr8);\n+\n+ /* Segment Registers - copy from packed struct to avoid unaligned access */\n+ memcpy(&seg, &env->regs_page->es, sizeof(hv_x64_segment_register));\n+ populate_segment_reg(&seg, &env->segs[R_ES]);\n+ memcpy(&seg, &env->regs_page->cs, sizeof(hv_x64_segment_register));\n+ populate_segment_reg(&seg, &env->segs[R_CS]);\n+ memcpy(&seg, &env->regs_page->ss, sizeof(hv_x64_segment_register));\n+ populate_segment_reg(&seg, &env->segs[R_SS]);\n+ memcpy(&seg, &env->regs_page->ds, sizeof(hv_x64_segment_register));\n+ populate_segment_reg(&seg, &env->segs[R_DS]);\n+ memcpy(&seg, &env->regs_page->fs, sizeof(hv_x64_segment_register));\n+ populate_segment_reg(&seg, &env->segs[R_FS]);\n+ memcpy(&seg, &env->regs_page->gs, sizeof(hv_x64_segment_register));\n+ populate_segment_reg(&seg, &env->segs[R_GS]);\n+}\n+\n+static void mshv_get_registers_vp_page(CPUState *cpu)\n+{\n+ /* General Purpose Registers */\n+ mshv_get_standard_regs_vp_page(cpu);\n+\n+ /* Special Registers */\n+ mshv_get_special_regs_vp_page(cpu);\n+}\n+\n \n int mshv_get_special_regs(CPUState *cpu)\n {\n@@ -424,18 +498,25 @@ int mshv_get_special_regs(CPUState *cpu)\n \n int mshv_load_regs(CPUState *cpu)\n {\n+ X86CPU *x86_cpu = X86_CPU(cpu);\n+ CPUX86State *env = &x86_cpu->env;\n int ret;\n \n- ret = mshv_get_standard_regs(cpu);\n- if (ret < 0) {\n- error_report(\"Failed to load standard registers\");\n- return -1;\n- }\n+ /* Use register vp page to optimize registers access */\n+ if (env->regs_page && env->regs_page->isvalid != 0) {\n+ mshv_get_registers_vp_page(cpu);\n+ } else {\n+ ret = mshv_get_standard_regs(cpu);\n+ if (ret < 0) {\n+ error_report(\"Failed to load standard registers\");\n+ return -1;\n+ }\n \n- ret = mshv_get_special_regs(cpu);\n- if (ret < 0) {\n- error_report(\"Failed to load special registers\");\n- return -1;\n+ ret = mshv_get_special_regs(cpu);\n+ if (ret < 0) {\n+ error_report(\"Failed to load special registers\");\n+ return -1;\n+ }\n }\n \n return 0;\n", "prefixes": [ "v2", "5/7" ] }