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GET /api/1.2/patches/2233062/?format=api
{ "id": 2233062, "url": "http://patchwork.ozlabs.org/api/1.2/patches/2233062/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260505154410.230969-4-alexander.hansen@9elements.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.2/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260505154410.230969-4-alexander.hansen@9elements.com>", "list_archive_url": null, "date": "2026-05-05T15:42:57", "name": "[v2,3/4] hw/sensor: support Texas Instruments ADC128D818", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "5b66f65c7caf07f70dc36ffb95c687c86f1fcb50", "submitter": { "id": 87518, "url": "http://patchwork.ozlabs.org/api/1.2/people/87518/?format=api", "name": "Alexander Hansen", "email": "alexander.hansen@9elements.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260505154410.230969-4-alexander.hansen@9elements.com/mbox/", "series": [ { "id": 502857, "url": "http://patchwork.ozlabs.org/api/1.2/series/502857/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=502857", "date": "2026-05-05T15:42:54", "name": "initial support for yosemite v4", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/502857/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2233062/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2233062/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit 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"<20260505154410.230969-1-alexander.hansen@9elements.com>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=UTF-8", "Content-Transfer-Encoding": "8bit", "Received-SPF": "pass client-ip=2a00:1450:4864:20::42f;\n envelope-from=alexander.hansen@9elements.com; helo=mail-wr1-x42f.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "Product: [1]\nDatasheet: [2]\n\nADC128D818 Support:\n- channel readings from pre-set values\n- driver can read and write most configuration registers\n\nADC128D818 currently unsupported:\n- slave address restriction\n- startup sequence and realistic busy register emulation\n- external VREF\n- conversion rate\n- interrupts\n- deep shutdown mode\n- individual channel shutdown\n- selection between Mode 0,1,2,3\n- pseudo-differential input\n\nAnyone could expand it in the future for more accurate emulation.\n\nThe reason for adding this device is to support Yosemite V4 emulation.\n\nTested: on yosemite v4 qemu\n\ninitialize the device:\n```\n// ti,adc128d818 @ 0x1f (adc)\n// the driver will throw away the last 4 bits, set them 0\nuint16_t adc_values1[8] = {\n 0b011110000000, 0b010100010000,\n 0b001000110000, 0b100000100000,\n 0b011110000000, 0b010100010000,\n 0b001000110000, 0b100000100000};\nadc128d818_init_with_values(bus, 0x1f, adc_values1, 8);\n```\n\nTrace outputs directly after initialization:\n```\nadc128d818_realize i2c_addr: 0x1f\nadc128d818_realize i2c_addr: 0x1f\nadc128d818_event i2c_addr: 0x1f, event: 0x01\nadc128d818_send i2c_addr: 0x1f, data: 0x00\nadc128d818_send i2c_addr: 0x1f, data: 0x80\nadc128d818_write i2c_addr: 0x1f, reg: 0x00 data: 0x80\nadc128d818_event i2c_addr: 0x1f, event: 0x03\nadc128d818_event i2c_addr: 0x1f, event: 0x01\n...\n```\n\nread the values\n```\nroot@yosemite4:/sys/bus/i2c/devices/30-001f# cat hwmon/hwmon0/in0_min\n0\nroot@yosemite4:/sys/bus/i2c/devices/30-001f# cat hwmon/hwmon0/in0_max\n0\nroot@yosemite4:/sys/bus/i2c/devices/30-001f# cat hwmon/hwmon0/in0_input\n75\nroot@yosemite4:/sys/bus/i2c/devices/30-001f# cat hwmon/hwmon0/name\nadc128d818\n```\n\nWe initially configured 0b011110000000 for the first channel.\nThe driver throws away the last 4 bits and does calculation similar to\nbelow:\n```\nval = DIV_ROUND_CLOSEST(data->in[index][nr] * data->vref, 4095);\n```\nWe can check that the calculation is as expected given our configured\nvalue.\n```\n((0b011110000000 >> 4) * 2560) / 4095\n75.01831501831502\n```\n\nReferences:\n[1] https://www.ti.com/product/ADC128D818\n[2] https://www.ti.com/lit/gpn/adc128d818\n\nCc: Paolo Bonzini <pbonzini@redhat.com> (maintainer:Kconfig)\nCc: Peter Maydell <peter.maydell@linaro.org> (supporter:ARM TCG CPUs)\nCc: \"Philippe Mathieu-Daudé\" <philmd@linaro.org> (odd fixer:Overall sensors)\nCc: qemu-arm@nongnu.org (open list:ARM TCG CPUs)\nCc: qemu-devel@nongnu.org (open list:All patches CC here)\nSigned-off-by: Alexander Hansen <alexander.hansen@9elements.com>\n---\n hw/arm/Kconfig | 1 +\n hw/sensor/Kconfig | 4 +\n hw/sensor/adc128d818.c | 414 +++++++++++++++++++++++++++++++++\n hw/sensor/meson.build | 1 +\n hw/sensor/trace-events | 8 +\n include/hw/sensor/adc128d818.h | 20 ++\n 6 files changed, 448 insertions(+)\n create mode 100644 hw/sensor/adc128d818.c\n create mode 100644 include/hw/sensor/adc128d818.h", "diff": "diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig\nindex decbc8b0d8..c1693325a1 100644\n--- a/hw/arm/Kconfig\n+++ b/hw/arm/Kconfig\n@@ -553,6 +553,7 @@ config ASPEED_SOC\n select MAX31785\n select MAX31790\n select MAX11615\n+ select ADC128D818\n select FSI_APB2OPB_ASPEED\n select AT24C\n select PCI_EXPRESS\ndiff --git a/hw/sensor/Kconfig b/hw/sensor/Kconfig\nindex 84eede9d84..c9190ff780 100644\n--- a/hw/sensor/Kconfig\n+++ b/hw/sensor/Kconfig\n@@ -51,3 +51,7 @@ config MAX31790\n config MAX11615\n bool\n depends on I2C\n+\n+config ADC128D818\n+ bool\n+ depends on I2C\ndiff --git a/hw/sensor/adc128d818.c b/hw/sensor/adc128d818.c\nnew file mode 100644\nindex 0000000000..83a4d43846\n--- /dev/null\n+++ b/hw/sensor/adc128d818.c\n@@ -0,0 +1,414 @@\n+/*\n+ * Texas Instruments ADC128D818 12 bit ADC with temperature sensor\n+ * Models ADC128D818\n+ *\n+ * Product: https://www.ti.com/product/ADC128D818\n+ * Datasheet: https://www.ti.com/lit/gpn/adc128d818\n+ *\n+ * Copyright 2026 9elements\n+ *\n+ * SPDX-License-Identifier: GPL-2.0-or-later\n+ */\n+\n+#include \"qemu/osdep.h\"\n+#include \"hw/i2c/i2c.h\"\n+#include \"migration/vmstate.h\"\n+#include \"qapi/error.h\"\n+#include \"qapi/visitor.h\"\n+#include \"qemu/log.h\"\n+#include \"qemu/module.h\"\n+#include \"trace.h\"\n+#include \"hw/sensor/adc128d818.h\"\n+\n+/* 8 bit, r/w */\n+#define REG_CONFIG 0x00\n+\n+/* 8 bit, readonly */\n+#define REG_INTERRUPT_STATUS 0x01\n+\n+/* 8 bit, r/w */\n+#define REG_INTERRUPT_MASK 0x03\n+\n+/* 8 bit, r/w */\n+#define REG_CONVERSION_RATE 0x07\n+\n+/* 8 bit, r/w */\n+#define REG_CHANNEL_DISABLE 0x08\n+\n+/* 8 bit, write-only */\n+#define REG_ONE_SHOT 0x09\n+\n+/* 8 bit, r/w */\n+#define REG_DEEP_SHUTDOWN 0x0a\n+\n+/* 8 bit, r/w */\n+#define REG_ADVANCED_CONFIG 0x0b\n+\n+/* 8 bit, readonly */\n+#define REG_BUSY_STATUS 0x0c\n+\n+/* 16 bit registers, N = 0..7, readonly */\n+#define REG_CHANNEL_READING(N) (0x20 + N)\n+\n+/* 8 bit registers N = 0..15, r/w */\n+#define REG_LIMIT(N) (0x2a + N)\n+\n+/* 8 bit register, readonly */\n+#define REG_MANUFACTURER_ID 0x3e\n+\n+/* 8 bit register, readonly */\n+#define REG_REVISION_ID 0x3f\n+\n+#define ADC128D818_NUM_CHANNELS 8\n+\n+struct ADC128D818State {\n+ I2CSlave i2c;\n+\n+ uint8_t config;\n+ uint8_t interrupt_mask;\n+ uint8_t conversion_rate;\n+ uint8_t channel_disable;\n+ bool deep_shutdown;\n+ uint8_t advanced_config;\n+\n+ /* channel reading registers, 2 bytes each */\n+ uint16_t channels[ADC128D818_NUM_CHANNELS];\n+\n+ /* high and low limit registers 0x2a - 0x39, one byte each */\n+ uint8_t limit[ADC128D818_NUM_CHANNELS * 2];\n+\n+ /* input buffer */\n+ uint8_t len;\n+ uint8_t buf[2];\n+\n+ /* output buffer */\n+ uint8_t outlen;\n+ uint8_t outbuf[2];\n+\n+ /* selected channel for read/write operation */\n+ uint8_t pointer;\n+};\n+\n+struct ADC128D818Class {\n+ I2CSlaveClass parent_class;\n+};\n+\n+OBJECT_DECLARE_TYPE(ADC128D818State, ADC128D818Class, ADC128D818)\n+\n+static void adc128d818_read(ADC128D818State *s)\n+{\n+ uint8_t ch_num = 0;\n+ switch (s->pointer) {\n+ case REG_CONFIG:\n+ s->outbuf[0] = s->config;\n+ break;\n+ case REG_INTERRUPT_STATUS:\n+ s->outbuf[0] = 0x0; /* POR State */\n+ break;\n+ case REG_INTERRUPT_MASK:\n+ s->outbuf[0] = s->interrupt_mask;\n+ break;\n+ case REG_CONVERSION_RATE:\n+ s->outbuf[0] = s->conversion_rate;\n+ break;\n+ case REG_CHANNEL_DISABLE:\n+ s->outbuf[0] = s->channel_disable;\n+ break;\n+ case REG_ONE_SHOT:\n+ /* not marked as readable */\n+ qemu_log_mask(LOG_GUEST_ERROR, \"%s: read of register 0x%02x\\n\",\n+ __func__, s->pointer);\n+ s->outbuf[0] = 0x0;\n+ break;\n+ case REG_DEEP_SHUTDOWN:\n+ s->outbuf[0] = s->deep_shutdown ? 0x1 : 0x0;\n+ break;\n+ case REG_ADVANCED_CONFIG:\n+ s->outbuf[0] = s->advanced_config & 0b111;\n+ break;\n+ case REG_BUSY_STATUS:\n+ /* not implemented */\n+ s->outbuf[0] = 0b00000010; /* POR State */\n+ break;\n+ case REG_CHANNEL_READING(0):\n+ case REG_CHANNEL_READING(1):\n+ case REG_CHANNEL_READING(2):\n+ case REG_CHANNEL_READING(3):\n+ case REG_CHANNEL_READING(4):\n+ case REG_CHANNEL_READING(5):\n+ case REG_CHANNEL_READING(6):\n+ case REG_CHANNEL_READING(7):\n+ ch_num = s->pointer - REG_CHANNEL_READING(0);\n+ /* high byte comes first, driver reads swapped */\n+ s->outbuf[0] = (s->channels[ch_num] >> 8) & 0xff;\n+ s->outbuf[1] = s->channels[ch_num] & 0xff;\n+ break;\n+ case REG_LIMIT(0):\n+ case REG_LIMIT(1):\n+ case REG_LIMIT(2):\n+ case REG_LIMIT(3):\n+ case REG_LIMIT(4):\n+ case REG_LIMIT(5):\n+ case REG_LIMIT(6):\n+ case REG_LIMIT(7):\n+ case REG_LIMIT(8):\n+ case REG_LIMIT(9):\n+ case REG_LIMIT(10):\n+ case REG_LIMIT(11):\n+ case REG_LIMIT(12):\n+ case REG_LIMIT(13):\n+ case REG_LIMIT(14):\n+ case REG_LIMIT(15):\n+ s->outbuf[0] = s->limit[s->pointer - REG_LIMIT(0)];\n+ break;\n+ case REG_MANUFACTURER_ID:\n+ s->outbuf[0] = 0x1; /* readonly */\n+ break;\n+ case REG_REVISION_ID:\n+ s->outbuf[0] = 0b00001001; /* readonly */\n+ break;\n+ default:\n+ qemu_log_mask(LOG_GUEST_ERROR, \"%s: read of register 0x%02x\\n\",\n+ __func__, s->pointer);\n+ break;\n+ }\n+}\n+\n+static void adc128d818_write_advanced_config(ADC128D818State *s, uint8_t data)\n+{\n+ /*\n+ * Note: Whenever the Advanced Configuration Register is programmed,\n+ * all of the values in the Channel Reading Registers and\n+ * Interrupt Status Registers will return to their default values.\n+ */\n+\n+ s->advanced_config = (data & 0b111);\n+}\n+\n+static void adc128d818_write(ADC128D818State *s, uint8_t data)\n+{\n+ trace_adc128d818_write(s->i2c.address, s->pointer, data);\n+\n+ /* which bits in config register are writable */\n+ const uint8_t config_w_mask = 0b10001011;\n+ const uint8_t config_ro_mask = (uint8_t)~config_w_mask;\n+\n+ switch (s->pointer) {\n+ case REG_CONFIG:\n+ s->config = (s->config & config_ro_mask) | (data & config_w_mask);\n+ break;\n+ case REG_INTERRUPT_MASK:\n+ s->interrupt_mask = data;\n+ break;\n+ case REG_CONVERSION_RATE:\n+ s->conversion_rate = data;\n+ break;\n+ case REG_CHANNEL_DISABLE:\n+ s->channel_disable = data;\n+ break;\n+ case REG_ONE_SHOT:\n+ /*\n+ * Initiate a single conversion and comparison cycle when\n+ * the device is in shutdown mode or deep shutdown mode, after\n+ * which the device returns to the respective mode that it was in\n+ *\n+ */\n+ break;\n+ case REG_DEEP_SHUTDOWN:\n+ s->deep_shutdown = (data & 0x1) != 0;\n+ break;\n+ case REG_ADVANCED_CONFIG:\n+ adc128d818_write_advanced_config(s, data);\n+ break;\n+ case REG_LIMIT(0):\n+ case REG_LIMIT(1):\n+ case REG_LIMIT(2):\n+ case REG_LIMIT(3):\n+ case REG_LIMIT(4):\n+ case REG_LIMIT(5):\n+ case REG_LIMIT(6):\n+ case REG_LIMIT(7):\n+ case REG_LIMIT(8):\n+ case REG_LIMIT(9):\n+ case REG_LIMIT(10):\n+ case REG_LIMIT(11):\n+ case REG_LIMIT(12):\n+ case REG_LIMIT(13):\n+ case REG_LIMIT(14):\n+ case REG_LIMIT(15):\n+ s->limit[s->pointer - REG_LIMIT(0)] = data;\n+ break;\n+ default:\n+ qemu_log_mask(LOG_GUEST_ERROR, \"%s: write of register 0x%02x\\n\",\n+ __func__, s->pointer);\n+ break;\n+ }\n+}\n+\n+static int adc128d818_send(I2CSlave *i2c, uint8_t data)\n+{\n+ ADC128D818State *s = ADC128D818(i2c);\n+ trace_adc128d818_send(s->i2c.address, data);\n+\n+ s->outlen = 0;\n+ s->buf[s->len] = data;\n+\n+ if (s->len == 0) {\n+ s->pointer = data;\n+ } else if (s->len == 1) {\n+ adc128d818_write(s, data);\n+ }\n+\n+ s->len++;\n+ return 0;\n+}\n+\n+static uint8_t adc128d818_recv(I2CSlave *i2c)\n+{\n+ ADC128D818State *s = ADC128D818(i2c);\n+ trace_adc128d818_recv(s->i2c.address, s->pointer);\n+\n+ adc128d818_read(s);\n+\n+ if (s->outlen >= 2) {\n+ qemu_log_mask(LOG_GUEST_ERROR, \"%s: too many bytes read\\n\", __func__);\n+ s->outlen = 0;\n+ }\n+\n+ const uint8_t data = s->outbuf[s->outlen++];\n+\n+ trace_adc128d818_recv_return(s->i2c.address, data);\n+ return data;\n+}\n+\n+static int adc128d818_event(I2CSlave *i2c, enum i2c_event event)\n+{\n+ ADC128D818State *s = ADC128D818(i2c);\n+\n+ trace_adc128d818_event(s->i2c.address, event);\n+\n+ switch (event) {\n+ case I2C_START_RECV:\n+ s->outlen = 0;\n+ break;\n+ case I2C_START_SEND:\n+ s->len = 0;\n+ break;\n+ default:\n+ break;\n+ }\n+\n+ return 0;\n+}\n+\n+static const VMStateDescription vmstate_adc128d818 = {\n+ .name = TYPE_ADC128D818,\n+ .version_id = 0,\n+ .minimum_version_id = 0,\n+ .fields = (const VMStateField[]){\n+ VMSTATE_UINT8(config, ADC128D818State),\n+ VMSTATE_UINT8(interrupt_mask, ADC128D818State),\n+ VMSTATE_UINT8(conversion_rate, ADC128D818State),\n+ VMSTATE_UINT8(channel_disable, ADC128D818State),\n+ VMSTATE_BOOL(deep_shutdown, ADC128D818State),\n+ VMSTATE_UINT8(advanced_config, ADC128D818State),\n+ VMSTATE_UINT16_ARRAY(channels, ADC128D818State,\n+ ADC128D818_NUM_CHANNELS),\n+ VMSTATE_UINT8_ARRAY(limit, ADC128D818State,\n+ ADC128D818_NUM_CHANNELS * 2),\n+ VMSTATE_UINT8(len, ADC128D818State),\n+ VMSTATE_UINT8_ARRAY(buf, ADC128D818State, 2),\n+ VMSTATE_UINT8(outlen, ADC128D818State),\n+ VMSTATE_UINT8_ARRAY(outbuf, ADC128D818State, 2),\n+ VMSTATE_UINT8(pointer, ADC128D818State),\n+ VMSTATE_I2C_SLAVE(i2c, ADC128D818State),\n+ VMSTATE_END_OF_LIST()\n+ }\n+};\n+\n+static void adc128d818_init(Object *obj)\n+{\n+ /* Nothing to do */\n+}\n+\n+I2CSlave *adc128d818_init_with_values(I2CBus *bus, uint8_t address,\n+ const uint16_t *init_values, uint32_t init_values_size)\n+{\n+ ADC128D818State *s;\n+\n+ s = ADC128D818(i2c_slave_new(TYPE_ADC128D818, address));\n+\n+ for (int i = 0; i < ADC128D818_NUM_CHANNELS; i++) {\n+\n+ /* arbitrary value */\n+ uint16_t value = 0b0000101011010010;\n+\n+ if (i < init_values_size) {\n+ value = init_values[i];\n+ }\n+ s->channels[i] = value;\n+ }\n+\n+ i2c_slave_realize_and_unref(I2C_SLAVE(s), bus, &error_abort);\n+\n+ return I2C_SLAVE(s);\n+}\n+\n+static void adc128d818_reset(I2CSlave *i2c)\n+{\n+ ADC128D818State *s = ADC128D818(i2c);\n+\n+ s->pointer = 0;\n+ s->outlen = 0;\n+\n+ /* POR-State */\n+ s->config = 0b00001000;\n+ s->interrupt_mask = 0;\n+ s->conversion_rate = 0;\n+ s->channel_disable = 0;\n+ s->deep_shutdown = 0;\n+ s->advanced_config = 0;\n+\n+ /* No POR-State defined in datasheet */\n+ for (int i = 0; i < ADC128D818_NUM_CHANNELS * 2; i++) {\n+ s->limit[i] = 0;\n+ }\n+}\n+\n+static void adc128d818_realize(DeviceState *dev, Error **errp)\n+{\n+ ADC128D818State *s = ADC128D818(dev);\n+\n+ trace_adc128d818_realize(s->i2c.address);\n+\n+ adc128d818_reset(&s->i2c);\n+}\n+\n+static void adc128d818_class_init(ObjectClass *klass, const void *data)\n+{\n+ DeviceClass *dc = DEVICE_CLASS(klass);\n+ I2CSlaveClass *k = I2C_SLAVE_CLASS(klass);\n+\n+ dc->realize = adc128d818_realize;\n+ dc->desc = \"Texas Intstruments ADC128D818 12-bit ADC with temp sensor\";\n+ dc->vmsd = &vmstate_adc128d818;\n+ k->event = adc128d818_event;\n+ k->recv = adc128d818_recv;\n+ k->send = adc128d818_send;\n+}\n+\n+static const TypeInfo adc128d818_info = {\n+ .name = TYPE_ADC128D818,\n+ .parent = TYPE_I2C_SLAVE,\n+ .instance_size = sizeof(ADC128D818State),\n+ .class_size = sizeof(ADC128D818Class),\n+ .instance_init = adc128d818_init,\n+ .class_init = adc128d818_class_init,\n+};\n+\n+static void adc128d818_register_types(void)\n+{\n+ type_register_static(&adc128d818_info);\n+}\n+\n+type_init(adc128d818_register_types)\ndiff --git a/hw/sensor/meson.build b/hw/sensor/meson.build\nindex a1e26604fa..defd7647e7 100644\n--- a/hw/sensor/meson.build\n+++ b/hw/sensor/meson.build\n@@ -10,3 +10,4 @@ system_ss.add(when: 'CONFIG_ISL_PMBUS_VR', if_true: files('isl_pmbus_vr.c'))\n system_ss.add(when: 'CONFIG_MAX31785', if_true: files('max31785.c'))\n system_ss.add(when: 'CONFIG_MAX31790', if_true: files('max31790.c'))\n system_ss.add(when: 'CONFIG_MAX11615', if_true: files('max11615.c'))\n+system_ss.add(when: 'CONFIG_ADC128D818', if_true: files('adc128d818.c'))\ndiff --git a/hw/sensor/trace-events b/hw/sensor/trace-events\nindex 3fed979e85..4853f1944d 100644\n--- a/hw/sensor/trace-events\n+++ b/hw/sensor/trace-events\n@@ -20,3 +20,11 @@ max11615_recv(uint8_t i2c_addr, uint8_t reg_addr) \"i2c_addr: 0x%02x, reg_addr: 0\n max11615_recv_return(uint8_t i2c_addr, uint8_t data) \"i2c_addr: 0x%02x, returns: 0x%02x\"\n max11615_event(uint8_t i2c_addr, uint8_t event) \"i2c_addr: 0x%02x, event: 0x%02x\"\n max11615_realize(uint8_t i2c_addr) \"i2c_addr: 0x%02x\"\n+\n+# adc128d818.c\n+adc128d818_send(uint8_t i2c_addr, uint8_t data) \"i2c_addr: 0x%02x, data: 0x%02x\"\n+adc128d818_write(uint8_t i2c_addr, uint8_t reg, uint8_t data) \"i2c_addr: 0x%02x, reg: 0x%02x data: 0x%02x\"\n+adc128d818_recv(uint8_t i2c_addr, uint8_t reg) \"i2c_addr: 0x%02x, reg: 0x%02x\"\n+adc128d818_recv_return(uint8_t i2c_addr, uint8_t data) \"i2c_addr: 0x%02x, returns: 0x%02x\"\n+adc128d818_event(uint8_t i2c_addr, uint8_t event) \"i2c_addr: 0x%02x, event: 0x%02x\"\n+adc128d818_realize(uint8_t i2c_addr) \"i2c_addr: 0x%02x\"\ndiff --git a/include/hw/sensor/adc128d818.h b/include/hw/sensor/adc128d818.h\nnew file mode 100644\nindex 0000000000..e2bdc47590\n--- /dev/null\n+++ b/include/hw/sensor/adc128d818.h\n@@ -0,0 +1,20 @@\n+// SPDX-License-Identifier: GPL-2.0-or-later\n+#ifndef QEMU_ADC128D818_H\n+#define QEMU_ADC128D818_H\n+\n+#include <stdint.h>\n+#include \"hw/i2c/i2c.h\"\n+\n+#define TYPE_ADC128D818 \"adc128d818\"\n+\n+/*\n+ * Create and realize a adc128d818 ADC with constant caller-supplied readings\n+ * @bus: I2C bus to put it on\n+ * @address: I2C address\n+ * @init_values: array of readings for each ADC channel\n+ * @init_values_size: Size of @init_values, can be less than the number of channels\n+ */\n+I2CSlave *adc128d818_init_with_values(I2CBus *bus, uint8_t address,\n+ const uint16_t *init_values, uint32_t init_values_size);\n+\n+#endif\n", "prefixes": [ "v2", "3/4" ] }