Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/1.2/patches/2232954/?format=api
{ "id": 2232954, "url": "http://patchwork.ozlabs.org/api/1.2/patches/2232954/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/patch/20260505105928.38457-2-akhilrajeev@nvidia.com/", "project": { "id": 21, "url": "http://patchwork.ozlabs.org/api/1.2/projects/21/?format=api", "name": "Linux Tegra Development", "link_name": "linux-tegra", "list_id": "linux-tegra.vger.kernel.org", "list_email": "linux-tegra@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260505105928.38457-2-akhilrajeev@nvidia.com>", "list_archive_url": null, "date": "2026-05-05T10:59:25", "name": "[1/4] i2c: tegra: use dmaengine_get_dma_device() for DMA buffer allocation", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "9ee681c1d6fe41f61ffb490157d22e8876423501", "submitter": { "id": 81965, "url": "http://patchwork.ozlabs.org/api/1.2/people/81965/?format=api", "name": "Akhil R", "email": "akhilrajeev@nvidia.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-tegra/patch/20260505105928.38457-2-akhilrajeev@nvidia.com/mbox/", "series": [ { "id": 502821, "url": "http://patchwork.ozlabs.org/api/1.2/series/502821/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/list/?series=502821", "date": "2026-05-05T10:59:25", "name": "i2c: tegra: Improve DMA mapping, latency, and power management", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/502821/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2232954/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2232954/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-tegra+bounces-14213-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-tegra@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=WOvyus6+;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c04:e001:36c::12fc:5321; helo=tor.lore.kernel.org;\n envelope-from=linux-tegra+bounces-14213-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)", "smtp.subspace.kernel.org;\n\tdkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com\n header.b=\"WOvyus6+\"", "smtp.subspace.kernel.org;\n arc=fail smtp.client-ip=40.93.195.33", "smtp.subspace.kernel.org;\n dmarc=pass (p=reject dis=none) header.from=nvidia.com", "smtp.subspace.kernel.org;\n spf=fail smtp.mailfrom=nvidia.com" ], "Received": [ "from tor.lore.kernel.org (tor.lore.kernel.org\n [IPv6:2600:3c04:e001:36c::12fc:5321])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g8x0C1d1Rz1yJV\n\tfor <incoming@patchwork.ozlabs.org>; Tue, 05 May 2026 21:20:59 +1000 (AEST)", "from smtp.subspace.kernel.org (conduit.subspace.kernel.org\n [100.90.174.1])\n\tby tor.lore.kernel.org (Postfix) with ESMTP id 66FB430B5F58\n\tfor <incoming@patchwork.ozlabs.org>; Tue, 5 May 2026 11:00:12 +0000 (UTC)", "from localhost.localdomain (localhost.localdomain [127.0.0.1])\n\tby smtp.subspace.kernel.org (Postfix) with ESMTP id 1CBAD37BE80;\n\tTue, 5 May 2026 11:00:12 +0000 (UTC)", "from SN4PR2101CU001.outbound.protection.outlook.com\n (mail-southcentralusazon11012033.outbound.protection.outlook.com\n [40.93.195.33])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby smtp.subspace.kernel.org (Postfix) with ESMTPS id 70A283233F4;\n\tTue, 5 May 2026 11:00:10 +0000 (UTC)", "from BL1PR13CA0109.namprd13.prod.outlook.com (2603:10b6:208:2b9::24)\n by CH1PR12MB9599.namprd12.prod.outlook.com (2603:10b6:610:2ae::14) with\n Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9870.25; Tue, 5 May\n 2026 11:00:04 +0000", "from BL02EPF00021F6C.namprd02.prod.outlook.com\n (2603:10b6:208:2b9:cafe::2e) by BL1PR13CA0109.outlook.office365.com\n (2603:10b6:208:2b9::24) with Microsoft SMTP Server (version=TLS1_3,\n cipher=TLS_AES_256_GCM_SHA384) id 15.20.9891.15 via Frontend Transport; Tue,\n 5 May 2026 11:00:03 +0000", "from mail.nvidia.com (216.228.117.160) by\n BL02EPF00021F6C.mail.protection.outlook.com (10.167.249.8) with Microsoft\n SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id\n 15.20.9891.9 via Frontend Transport; Tue, 5 May 2026 11:00:03 +0000", "from rnnvmail204.nvidia.com (10.129.68.6) by mail.nvidia.com\n (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Tue, 5 May\n 2026 03:59:52 -0700", "from rnnvmail205.nvidia.com (10.129.68.10) by rnnvmail204.nvidia.com\n (10.129.68.6) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Tue, 5 May\n 2026 03:59:51 -0700", "from BUILDSERVER-IO-L4T.nvidia.com (10.127.8.9) by mail.nvidia.com\n (10.129.68.10) with Microsoft SMTP Server id 15.2.2562.20 via Frontend\n Transport; Tue, 5 May 2026 03:59:48 -0700" ], "ARC-Seal": [ "i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116;\n\tt=1777978811; cv=fail;\n b=U+YAbYjX9Ih8Q1qcCeUSbCzAvRFf8hsyhW74ml8VudRqdI7L9c3SI+qlLJ+XaZ/IcMG+ndppWtRipf+t9/BFlCFYiyVk98ZsIWS6QY8WM3WF5wv/ypGYH8MM0YMUyVckeyMUEm+ksvqzdzDUFcWbD6TUGSxZDct2FZ4CjqL/DDg=", "i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none;\n b=wP6jXtEyiZzk/cZJQDUdUK/TEiit81pwpy8TKrOFVGBjrx6WJzX5hfviR4sa2iyU8mPlFyH6Va3mmKIc9/8uOsHz3BFwmOKeYw88XitDlltr/kOjHehQunOvpruTILuF764vwL8zeN6DKWv8JUdisUJwvpNigmcsz5Hq0W3VYpz9lvm/IxYba3xbeB68gtzyvV++wO4d2X7/IOdo/85yGZx3ClMsFiH0pghvLWqWihUg/Bs5mRVItersmjRsgo1pV1J4uE1rGz3R9PDs12ntbzwCbdUCK/ptsxR4D06ynfubdgQ+QlLkLmOKHANP41sGDPZoBAQlt8RZf+hk9MuHSQ==" ], "ARC-Message-Signature": [ "i=2; a=rsa-sha256; d=subspace.kernel.org;\n\ts=arc-20240116; t=1777978811; c=relaxed/simple;\n\tbh=HPWGWlsFfwdc6MvcwXq0L3X9HTVL2k1U8wL5kV80skU=;\n\th=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References:\n\t MIME-Version:Content-Type;\n b=Lrtglwkdzb61Yaw3IL8iLKTwB/zsHRRulohyRVBNhK2InFgsCXLAJ/Xk2JPAJN1jw9jA92jS6jvhb2KmmhLWcj550bPZlQknlSgWLPcojmmKZyHkso81VJqUPsrBn6SFaa0vkbJXymsv9QDO5pSJX0boWHeNFWV5pQSOLRKNEy0=", "i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com;\n s=arcselector10001;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1;\n bh=wrmZ+/NqaBsAR2MciiHWHkdVel9TH/N9izq65UnUjwU=;\n b=NCX9U4EQn2sCSJ6kPIsd3OLipTcBCH4w7fDMZ978Z6ESsxlGfRYEdlX2/j/ZCgYe7bResN4F7r6DX/qrPRKN525qL6PCENMk8AIOJrzKVcWtkB250Ebo2sHrDHzduhB6rsLpIqKXjniAyNbtgQdMXeqgHGaqH69tXlPM4K2Tn11a/0pMSPw3d6SyBmJs++0rJbdidluqYfxF8hkY/YbyuIs7xfyFRYKh/jyLjulxKC5Rg9yF0qxiz5mhYU2OeivoiGcU4EhCktcK5Tv/P2hKcivzXNEc4GM2G5u7hyR8jklJFMpzL8Z8dBHvfMLV7sIbj2+DLIp6xRPfxs147B8uPw==" ], "ARC-Authentication-Results": [ "i=2; smtp.subspace.kernel.org;\n dmarc=pass (p=reject dis=none) header.from=nvidia.com;\n spf=fail smtp.mailfrom=nvidia.com;\n dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com\n header.b=WOvyus6+; arc=fail smtp.client-ip=40.93.195.33", "i=1; mx.microsoft.com 1; spf=pass (sender ip is\n 216.228.117.160) smtp.rcpttodomain=gmail.com smtp.mailfrom=nvidia.com;\n dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com;\n dkim=none (message not signed); arc=none (0)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com;\n s=selector2;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=wrmZ+/NqaBsAR2MciiHWHkdVel9TH/N9izq65UnUjwU=;\n b=WOvyus6+tltG0oIgRlhWc8ngvA8IEAl99hXPuxjYjnnlkVmdohU+aG8JdjxF5wprJVFh+5f1uqGJ2JvcsnGpo+IgHAVD28tRHxuwTRdtsCYEzzwHy8jlnA7+ixcBGao3454haNqmtSTAgywrTrXAScMIHJWYePBFTBP9uCu5LtNnCrsrOnbIFR9CxHOUpWmxKp5tz5o74eQDERz6z7LPMCvnZG4rzT72a2+ekixzD1uOHzEV9X9oTGzi4Ptj4w2+opr+RDssTtbH3xa5Lty3o1qlOgxIx30IbtPS3yLSCZftFkHcod2M9gszDzuncC+hDXbcg2Tl6a+GSlPwrFalug==", "X-MS-Exchange-Authentication-Results": "spf=pass (sender IP is 216.228.117.160)\n smtp.mailfrom=nvidia.com; dkim=none (message not signed)\n header.d=none;dmarc=pass action=none header.from=nvidia.com;", "Received-SPF": "Pass (protection.outlook.com: domain of nvidia.com designates\n 216.228.117.160 as permitted sender) receiver=protection.outlook.com;\n client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C", "From": "Akhil R <akhilrajeev@nvidia.com>", "To": "Laxman Dewangan <ldewangan@nvidia.com>, Dmitry Osipenko\n\t<digetx@gmail.com>, Andi Shyti <andi.shyti@kernel.org>, Thierry Reding\n\t<thierry.reding@kernel.org>, Jonathan Hunter <jonathanh@nvidia.com>, \"Kartik\n Rajput\" <kkartik@nvidia.com>, Wolfram Sang <wsa@kernel.org>,\n\t<linux-i2c@vger.kernel.org>, <linux-tegra@vger.kernel.org>,\n\t<linux-kernel@vger.kernel.org>", "CC": "<mochs@nvidia.com>, Akhil R <akhilrajeev@nvidia.com>", "Subject": "[PATCH 1/4] i2c: tegra: use dmaengine_get_dma_device() for DMA buffer\n allocation", "Date": "Tue, 5 May 2026 16:29:25 +0530", "Message-ID": "<20260505105928.38457-2-akhilrajeev@nvidia.com>", "X-Mailer": "git-send-email 2.50.1", "In-Reply-To": "<20260505105928.38457-1-akhilrajeev@nvidia.com>", "References": "<20260505105928.38457-1-akhilrajeev@nvidia.com>", "Precedence": "bulk", "X-Mailing-List": "linux-tegra@vger.kernel.org", "List-Id": "<linux-tegra.vger.kernel.org>", "List-Subscribe": "<mailto:linux-tegra+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-tegra+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "X-NVConfidentiality": "public", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-NV-OnPremToCloud": "ExternallySecured", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "BL02EPF00021F6C:EE_|CH1PR12MB9599:EE_", "X-MS-Office365-Filtering-Correlation-Id": "d65fc1e0-e36a-452a-4e3e-08deaa9575fb", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "\n\tBCL:0;ARA:13230040|82310400026|36860700016|1800799024|376014|921020|56012099003|22082099003|18002099003;", "X-Microsoft-Antispam-Message-Info": "\n\tZTU/JK+wFwNgYEK+CN417z7iMZJLOFItDpmlE6UrRnRrFNwGCRXh67UCB/cAw/wATSPIbB61kCJ2RGfChamoLhr0ME4QzrPrK9ovYY2mBvUjrsD1SvGxlapXheNFCjWNkMPEcm/KQe7g9TyNvI7yjkxEDvA6NvSM4qVvlK4VftbcOqsFCoBWQpDSjjOWCY8QY7gr80jOyFtyeyI8n+HHkjW9PqwgibxYsxjKxM8En1gO1ROhoIMEpivCfMfpehLCfAgKUIRkPPIl4p5Zk+34i/GwsSeuQKgUwu07i/DpufymAMmMGPgJxG4peM/jvU8bTVrjQa6/IkFP/cSIKVcl7k8gAC+DxyDKOqg4NeaZ41mrXPgRNre0ax7PEyX9dt2FucUTQ8hEQJwLfZ9jydFScU4l4uj6eQh6xUWggHI4sUV3YTD1idgLN7sN3K3IjktXT0LK3EEh7rOaQesIBgh3lwE6ay+Eqy4N98Q22K73T9WM/LOUeqbRUJ+qQS7kZw5eSwLmt9ENeQ8M3xP9yVKs5yMDCS0yyRDmZVQsQmkWcxCScJyhqQPhHjQelgpHugxa+Fnyx8AVI6knUTzjxX9JP1pIEogmBaXBgo1iiV9DdXUDphPtojiSgusbLSUProowKHp6fN501tqxoXBu6deO8G2LtWc3lAXDyhMdXaTbL38Ga5y1m056DxOQxdyIgeW6BUeCJyN1Lp8RgvBKPbpjprhMhGg6Xg9JwBHyf7L9Ks6gW1zZ629+6bzTDl0pnToVxNb7tL9WCIMGcQdSCaS14g==", "X-Forefront-Antispam-Report": "\n\tCIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(36860700016)(1800799024)(376014)(921020)(56012099003)(22082099003)(18002099003);DIR:OUT;SFP:1101;", "X-MS-Exchange-AntiSpam-MessageData-ChunkCount": "1", "X-MS-Exchange-AntiSpam-MessageData-0": "\n\tjuVmsdPOlRCaYQ1o2JL7ANkmkjKWhCk3/45R2FVkc1wTJRmaqXOcDLUqxBfent6iWLC7UaaYf9Cgv+R1nwV9Pzq32X4myw4LjfZs8/Cg+Jxb9BmPiVQvIzpyFezhfyZcXb6yNKwDfqfjcGBHGRPa4Ens1cGBsUz3Q2qWyDgasL3ReuBR4AzhQs/V9lWWmpPT/pN3k/xM8awT5ykA5m+OYjdkUrLT66X8qfAR0MHTbK3V6kQmm4Cz+amxloyxG+h9rPI0M6aCQWFi1DSSF6SWSuasryKGwVACz1rAVkGMsKGUX8XBQgaAllLPIQzdijQmg5xQ2dlM2984NF5irfUyI9Du5aREDij8POX44Dphe4rcB8aHj9U4wvyA1bewPG866pZJf6ayGeeUtIX/OGfkeUv+LN/5sHyaYmEeU9ui9LXNISPh68IdrBSQJktA29qX", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "05 May 2026 11:00:03.7572\n (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n d65fc1e0-e36a-452a-4e3e-08deaa9575fb", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n\tBL02EPF00021F6C.namprd02.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "CH1PR12MB9599" }, "content": "Use dmaengine_get_dma_device() to obtain the correct struct device\npointer for dma_alloc_coherent() instead of directly dereferencing\nchan->device->dev.\n\nThe dmaengine_get_dma_device() helper checks whether the DMA channel\nhas a per-channel DMA device (chan->dev->chan_dma_dev) and returns it\nwhen available, falling back to the controller device otherwise. On\nplatforms where the DMA controller sits behind an IOMMU with\nper-channel IOVA spaces (e.g. Tegra264 GPC DMA), the per-channel\ndevice carries the correct DMA mapping context. Using the controller\ndevice directly would allocate DMA buffers against the wrong IOMMU\ndomain, leading to SMMU faults at runtime.\n\nOn platforms without per-channel DMA devices the helper returns the\nsame pointer as before, so there is no change in behavior for existing\nhardware.\n\nSigned-off-by: Akhil R <akhilrajeev@nvidia.com>\nAssisted-by: Cursor:claude-4.6-opus\n---\n drivers/i2c/busses/i2c-tegra.c | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)", "diff": "diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c\nindex 9fd5ade774a0..a21f6457d41b 100644\n--- a/drivers/i2c/busses/i2c-tegra.c\n+++ b/drivers/i2c/busses/i2c-tegra.c\n@@ -712,7 +712,7 @@ static int tegra_i2c_init_dma(struct tegra_i2c_dev *i2c_dev)\n \t\tgoto err_out;\n \t}\n \n-\ti2c_dev->dma_dev = i2c_dev->dma_chan->device->dev;\n+\ti2c_dev->dma_dev = dmaengine_get_dma_device(i2c_dev->dma_chan);\n \ti2c_dev->dma_buf_size = i2c_dev->hw->quirks->max_write_len +\n \t\t\t\tI2C_PACKET_HEADER_SIZE;\n \n", "prefixes": [ "1/4" ] }