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GET /api/1.2/patches/2232953/?format=api
{ "id": 2232953, "url": "http://patchwork.ozlabs.org/api/1.2/patches/2232953/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260505112014.102993-3-alex.bennee@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.2/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260505112014.102993-3-alex.bennee@linaro.org>", "list_archive_url": null, "date": "2026-05-05T11:20:08", "name": "[v5,2/7] target/arm: redefine event stream fields", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "2d2d112c144c23fd5bcb0db2a2be699772b724af", "submitter": { "id": 39532, "url": "http://patchwork.ozlabs.org/api/1.2/people/39532/?format=api", "name": "Alex Bennée", "email": "alex.bennee@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260505112014.102993-3-alex.bennee@linaro.org/mbox/", "series": [ { "id": 502820, "url": "http://patchwork.ozlabs.org/api/1.2/series/502820/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=502820", "date": "2026-05-05T11:20:06", "name": "target/arm: fully model WFxT instructions for A-profile", "version": 5, "mbox": "http://patchwork.ozlabs.org/series/502820/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2232953/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2232953/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=zdRSeKTd;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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charset=UTF-8", "Content-Transfer-Encoding": "8bit", "Received-SPF": "pass client-ip=2a00:1450:4864:20::32f;\n envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x32f.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "The event stream control bits are the same for both CNTHCTL and\nCNTKCTL so rather than duplicating the definitions rename them to be\nuseful in both cases.\n\nWe will need these in a later commit when we start implementing event\nstreams.\n\nReviewed-by: Richard Henderson <richard.henderson@linaro.org>\nSigned-off-by: Alex Bennée <alex.bennee@linaro.org>\n---\n target/arm/internals.h | 11 +++++++----\n target/arm/helper.c | 8 ++++----\n 2 files changed, 11 insertions(+), 8 deletions(-)", "diff": "diff --git a/target/arm/internals.h b/target/arm/internals.h\nindex 4a1ea5465d7..24423a200ff 100644\n--- a/target/arm/internals.h\n+++ b/target/arm/internals.h\n@@ -269,14 +269,17 @@ FIELD(VSTCR, SA, 30, 1)\n * have different bit definitions, and EL1PCTEN might be\n * bit 0 or bit 10. We use _E2H1 and _E2H0 suffixes to\n * disambiguate if necessary.\n+ *\n+ * The event stream bits (EVN*) are in the same position for\n+ * CNTKCTL_EL1/CTNKCTL.\n */\n FIELD(CNTHCTL, EL0PCTEN_E2H1, 0, 1)\n FIELD(CNTHCTL, EL0VCTEN_E2H1, 1, 1)\n FIELD(CNTHCTL, EL1PCTEN_E2H0, 0, 1)\n FIELD(CNTHCTL, EL1PCEN_E2H0, 1, 1)\n-FIELD(CNTHCTL, EVNTEN, 2, 1)\n-FIELD(CNTHCTL, EVNTDIR, 3, 1)\n-FIELD(CNTHCTL, EVNTI, 4, 4)\n+FIELD(CNTxCTL, EVNTEN, 2, 1)\n+FIELD(CNTxCTL, EVNTDIR, 3, 1)\n+FIELD(CNTxCTL, EVNTI, 4, 4)\n FIELD(CNTHCTL, EL0VTEN, 8, 1)\n FIELD(CNTHCTL, EL0PTEN, 9, 1)\n FIELD(CNTHCTL, EL1PCTEN_E2H1, 10, 1)\n@@ -286,7 +289,7 @@ FIELD(CNTHCTL, EL1TVT, 13, 1)\n FIELD(CNTHCTL, EL1TVCT, 14, 1)\n FIELD(CNTHCTL, EL1NVPCT, 15, 1)\n FIELD(CNTHCTL, EL1NVVCT, 16, 1)\n-FIELD(CNTHCTL, EVNTIS, 17, 1)\n+FIELD(CNTxCTL, EVNTIS, 17, 1)\n FIELD(CNTHCTL, CNTVMASK, 18, 1)\n FIELD(CNTHCTL, CNTPMASK, 19, 1)\n \ndiff --git a/target/arm/helper.c b/target/arm/helper.c\nindex 7e7677a584d..dfdb77a9fe2 100644\n--- a/target/arm/helper.c\n+++ b/target/arm/helper.c\n@@ -1746,9 +1746,9 @@ static void gt_cnthctl_write(CPUARMState *env, const ARMCPRegInfo *ri,\n uint32_t valid_mask =\n R_CNTHCTL_EL0PCTEN_E2H1_MASK |\n R_CNTHCTL_EL0VCTEN_E2H1_MASK |\n- R_CNTHCTL_EVNTEN_MASK |\n- R_CNTHCTL_EVNTDIR_MASK |\n- R_CNTHCTL_EVNTI_MASK |\n+ R_CNTxCTL_EVNTEN_MASK |\n+ R_CNTxCTL_EVNTDIR_MASK |\n+ R_CNTxCTL_EVNTI_MASK |\n R_CNTHCTL_EL0VTEN_MASK |\n R_CNTHCTL_EL0PTEN_MASK |\n R_CNTHCTL_EL1PCTEN_E2H1_MASK |\n@@ -1763,7 +1763,7 @@ static void gt_cnthctl_write(CPUARMState *env, const ARMCPRegInfo *ri,\n R_CNTHCTL_EL1TVCT_MASK |\n R_CNTHCTL_EL1NVPCT_MASK |\n R_CNTHCTL_EL1NVVCT_MASK |\n- R_CNTHCTL_EVNTIS_MASK;\n+ R_CNTxCTL_EVNTIS_MASK;\n }\n if (cpu_isar_feature(aa64_ecv, cpu)) {\n valid_mask |= R_CNTHCTL_ECV_MASK;\n", "prefixes": [ "v5", "2/7" ] }