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GET /api/1.2/patches/2232243/?format=api
{ "id": 2232243, "url": "http://patchwork.ozlabs.org/api/1.2/patches/2232243/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260504025342.1452605-5-jamin_lin@aspeedtech.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.2/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260504025342.1452605-5-jamin_lin@aspeedtech.com>", "list_archive_url": null, "date": "2026-05-04T02:53:47", "name": "[v6,04/11] hw/usb/hcd-ehci: Implement 64-bit QH descriptor addressing", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "ad1cdfe66c2b9fe2450f08a9bb80cca6f59504ed", "submitter": { "id": 81768, "url": "http://patchwork.ozlabs.org/api/1.2/people/81768/?format=api", "name": "Jamin Lin", "email": "jamin_lin@aspeedtech.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260504025342.1452605-5-jamin_lin@aspeedtech.com/mbox/", "series": [ { "id": 502603, "url": "http://patchwork.ozlabs.org/api/1.2/series/502603/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=502603", "date": "2026-05-04T02:53:55", "name": "hw/usb/ehci: Add 64-bit descriptor addressing support", "version": 6, "mbox": "http://patchwork.ozlabs.org/series/502603/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2232243/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2232243/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=aspeedtech.com header.i=@aspeedtech.com\n header.a=rsa-sha256 header.s=selector1 header.b=O8KBV53p;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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Sun, 03 May 2026 22:53:55 -0400", "from TYPPR06MB8206.apcprd06.prod.outlook.com (2603:1096:405:383::19)\n by OSNPR06MB8442.apcprd06.prod.outlook.com (2603:1096:604:486::11)\n with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9870.25; Mon, 4 May\n 2026 02:53:48 +0000", "from TYPPR06MB8206.apcprd06.prod.outlook.com\n ([fe80::e659:1ead:77cb:f6d3]) by TYPPR06MB8206.apcprd06.prod.outlook.com\n ([fe80::e659:1ead:77cb:f6d3%2]) with mapi id 15.20.9870.023; Mon, 4 May 2026\n 02:53:47 +0000" ], "ARC-Seal": "i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none;\n b=sTxb9NWgndVGtE+b3jJ7bL9sgJulxjh4cyu7Bw1zWimCBVVp+aZLm7vz/OF7atbhM3bdQ4lPE520LNmVHuYnOMGyb12+lX4X28/I2wSPIPDNc2SoJ4VhKeKVgJKsJmiXC3I/JtOLM5sre7SvXJpvyezU0oz7NlTeeeUsqqlEYdyojQu9BEcDz6hmLuzTbNRLwPKW5Nfsru87zUN+ypTu9/AkLDN1c9A7MUo+cijwsL/3Oq3fNB/T+G8EtGXm3veyyd1ReFptVtCtOuYyajOCLtQx3Qj4po00JhwmNJseCQ1/kdwkbPEZ/Gz1G9elWZcBgdA0V/z82wfNwId+50DM3g==", "ARC-Message-Signature": "i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com;\n s=arcselector10001;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1;\n bh=8WSgMOQpGNOHC2DBPlWhfJj0J3VxElXrHXPibtMafH8=;\n b=HxYfzUeKDVwNQlot8IgMNYnT/Ow/Lo+48fpyXhc+2JfEF/O886vNBUd9A6AE60GmDm+1N7G61bO8k5GKVWILYoDuHbJxbKqN3BpbI7H8SFcVojzvOQa1jCbcVUZo9kbmEsw1P2RIOj33rwib8vUxBuihtXMgb2Ng7SgLp46gb5OsTV3aFlL2ZmWv8peRC/a7UJZX26xZ2gFdmpGsQtdpNiJU86+3eJxlgszK0f+qGmJE0r5Kz1QzAdPde0HvPFCyKnqM7D7krp6BrGw2H/NB+mG+F4J335RyihJpWHaEF76yAge+ASFS01or3RWdhotlQoFBP2K7EkdydIdto3o4Dw==", "ARC-Authentication-Results": "i=1; mx.microsoft.com 1; spf=pass\n smtp.mailfrom=aspeedtech.com; dmarc=pass action=none\n header.from=aspeedtech.com; dkim=pass header.d=aspeedtech.com; arc=none", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=aspeedtech.com;\n s=selector1;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=8WSgMOQpGNOHC2DBPlWhfJj0J3VxElXrHXPibtMafH8=;\n b=O8KBV53pR0k3CzubmYWwCnveh8ECIg0zhfbLVMqD0ERSTwSQwZZn33lSrTDvg178Wd5bEpY+Pbk2vwcCp8h+sQDb3Mycz/5wwUz4UkNf/H/rOjrKjuCOieGICwrX2Veu6uoUQl0cZ7R/ExIh93ASppJZqkpD94FnHz3NkfXRIVDss7BQekm3c1Xx8DamOOlEiUsRwQPXNXRO2qXr04eKCIg6rhhzhfjV0LYNj7oLHt7HyCNmJ2h77K2WWerFA1z3I6uHLTV43MOK0octz/B+Oktpwzlsm1OfihcIvmwdYGhA5QHK1bLiUV6vIef/CIDbqN2oiAQQb17GZjxIihbu3w==", "From": "Jamin Lin <jamin_lin@aspeedtech.com>", "To": "\"philmd@linaro.org\" <philmd@linaro.org>,\n \"peterx@redhat.com\" <peterx@redhat.com>,\n =?iso-8859-1?q?C=E9dric_Le_Goater?= <clg@kaod.org>,\n Peter Maydell <peter.maydell@linaro.org>,\n Steven Lee <steven_lee@aspeedtech.com>, Troy Lee <leetroy@gmail.com>,\n Kane Chen <kane_chen@aspeedtech.com>,\n Andrew Jeffery <andrew@codeconstruct.com.au>, Joel Stanley <joel@jms.id.au>,\n Zhao Liu <zhao1.liu@intel.com>,\n \"open list:ASPEED BMCs\" <qemu-arm@nongnu.org>,\n \"open list:All patches CC here\" <qemu-devel@nongnu.org>", "CC": "Jamin Lin <jamin_lin@aspeedtech.com>, Troy Lee <troy_lee@aspeedtech.com>,\n \"farosas@suse.de\" <farosas@suse.de>, \"flwu@google.com\" <flwu@google.com>,\n \"nabihestefan@google.com\" <nabihestefan@google.com>", "Subject": "[PATCH v6 04/11] hw/usb/hcd-ehci: Implement 64-bit QH descriptor\n addressing", "Thread-Topic": "[PATCH v6 04/11] hw/usb/hcd-ehci: Implement 64-bit QH descriptor\n addressing", "Thread-Index": "AQHc23E6EmTdcjXkvkO41MSGG3nK9w==", "Date": "Mon, 4 May 2026 02:53:47 +0000", "Message-ID": "<20260504025342.1452605-5-jamin_lin@aspeedtech.com>", "References": "<20260504025342.1452605-1-jamin_lin@aspeedtech.com>", "In-Reply-To": "<20260504025342.1452605-1-jamin_lin@aspeedtech.com>", "Accept-Language": "zh-TW, en-US", "Content-Language": "en-US", "X-MS-Has-Attach": "", "X-MS-TNEF-Correlator": "", "authentication-results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=aspeedtech.com header.i=@aspeedtech.com\n header.a=rsa-sha256 header.s=selector1 header.b=O8KBV53p;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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charset=\"iso-8859-1\"", "Content-Transfer-Encoding": "quoted-printable", "MIME-Version": "1.0", "X-Exchange-RoutingPolicyChecked": "\n lNolUV+kX5Yl+4F06PdDwkktcqy1dM/JIZJsa09PaQmoQnGXTlZ2knia3BwO9P2YFcEEJ8W90rZSUzX5ukr9OuwILdmT9rrD5GSUsvMXc9kM9Bl7SNr1GoABjqZ9UKCa4mRde8+ifn0C98KaM5cnDJq1fTmgZRHi/Gtprxc0EMEKe9b50L5pduPJLeV7fjeQPNe1vaNvnwdLwZJZIIaK1c0UbRAXa4YLUATaKJwnADWGkmabTW5KnOSs71AqCUx/XKBpW+BvEY3nilCLTRs+T05/1AMX7CxL1lNoOeHisLk2bvTqNC8JEBEOopESXb9glFLSeSWkiLFK3C6ObbPhPg==", "X-OriginatorOrg": "aspeedtech.com", "X-MS-Exchange-CrossTenant-AuthAs": "Internal", "X-MS-Exchange-CrossTenant-AuthSource": "TYPPR06MB8206.apcprd06.prod.outlook.com", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 8cfafa79-5921-4cce-40b5-08dea9885d3e", "X-MS-Exchange-CrossTenant-originalarrivaltime": "04 May 2026 02:53:47.8075 (UTC)", "X-MS-Exchange-CrossTenant-fromentityheader": "Hosted", "X-MS-Exchange-CrossTenant-id": "43d4aa98-e35b-4575-8939-080e90d5a249", "X-MS-Exchange-CrossTenant-mailboxtype": "HOSTED", "X-MS-Exchange-CrossTenant-userprincipalname": "\n 254b1S1eXTuLOujV4F3YA9JmJL9pzw6N+LGOn5gQpNty+p5eIOFeqhmriErYPEvJQ6eRjjqMrH8wwMeNNqULnGE3YCVorLR8K6pnMKNU/Cs=", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "OSNPR06MB8442", "Received-SPF": "pass client-ip=2a01:111:f403:c405::7;\n envelope-from=jamin_lin@aspeedtech.com;\n helo=TYDPR03CU002.outbound.protection.outlook.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "EHCI supports 64-bit control data structure addressing when the\n64-bit Addressing Capability bit in HCCPARAMS is set. In that mode,\nthe CTRLDSSEGMENT register supplies the upper 32 bits which are\nconcatenated with 32-bit link pointer fields to form full 64-bit\ndescriptor addresses (EHCI 1.0, section 2.3.5 and Appendix B).\n\nThe current implementation assumes 32-bit QH descriptor addresses\nand directly uses link pointer values without applying the\nCTRLDSSEGMENT upper dword.\n\nIntroduce a helper, ehci_get_desc_addr(), to construct full 64-bit\ndescriptor addresses when 64-bit capability is enabled. Update QH\ntraversal paths (async list walk, horizontal QH link, and periodic\nschedule entry handling) to use the translated 64-bit addresses.\n\nEHCI 64-bit buffer pointer fields are defined in Appendix B as\nsplit 32-bit low/high parts located at separate offsets, rather\nthan a single contiguous 64-bit field. Therefore, the buffer\npointers cannot be represented as uint64_t bufptr[5] without\nviolating the descriptor layout defined by the specification.\n\nIntroduce ehci_get_buf_addr() to construct full 64-bit buffer\naddresses from bufptr[] and bufptr_hi[] fields. Use this helper\nwhen calculating transfer buffer addresses so that data buffers\nabove 4GB are correctly handled.\n\nAlso add bufptr_hi[5] to EHCIqh to support 64-bit buffer pointer\nfields as defined in Appendix B.\n\nWhen 64-bit capability is disabled, descriptor addresses remain\n32-bit and existing behaviour is unchanged.\n\nNote: Similar split 64-bit buffer pointer handling is required for\nqTD, iTD and siTD descriptors, which will be addressed in follow-up\nchanges.\n\nSigned-off-by: Jamin Lin <jamin_lin@aspeedtech.com>\nReviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>\n---\n hw/usb/hcd-ehci.h | 4 ++++\n hw/usb/hcd-ehci.c | 47 ++++++++++++++++++++++++++++++++++-----------\n hw/usb/trace-events | 2 +-\n 3 files changed, 41 insertions(+), 12 deletions(-)", "diff": "diff --git a/hw/usb/hcd-ehci.h b/hw/usb/hcd-ehci.h\nindex f1f2fde578..3428839ec6 100644\n--- a/hw/usb/hcd-ehci.h\n+++ b/hw/usb/hcd-ehci.h\n@@ -141,6 +141,9 @@ typedef struct EHCIqtd {\n #define QTD_BUFPTR_SH 12\n } EHCIqtd;\n \n+/* QH overlay: altnext_qtd, token, bufptr[5], bufptr_hi[5] */\n+#define EHCI_QH_OVERLAY_COUNT 12\n+\n /*\n * EHCI spec version 1.0 Section 3.6\n */\n@@ -194,6 +197,7 @@ typedef struct EHCIqh {\n #define BUFPTR_FRAMETAG_MASK 0x0000001f\n #define BUFPTR_SBYTES_MASK 0x00000fe0\n #define BUFPTR_SBYTES_SH 5\n+ uint32_t bufptr_hi[5];\n } EHCIqh;\n \n enum async_state {\ndiff --git a/hw/usb/hcd-ehci.c b/hw/usb/hcd-ehci.c\nindex 7166a93fd2..e770f0a7fa 100644\n--- a/hw/usb/hcd-ehci.c\n+++ b/hw/usb/hcd-ehci.c\n@@ -147,6 +147,23 @@ static const char *addr2str(hwaddr addr)\n return nr2str(ehci_mmio_names, ARRAY_SIZE(ehci_mmio_names), addr);\n }\n \n+static uint64_t ehci_get_buf_addr(const EHCIState *s, uint32_t hi,\n+ uint32_t lo, uint32_t lo_mask)\n+{\n+ uint64_t addr = lo & lo_mask;\n+\n+ if (s->caps_64bit_addr) {\n+ addr = deposit64(addr, 32, 32, hi);\n+ }\n+\n+ return addr;\n+}\n+\n+static uint64_t ehci_get_desc_addr(const EHCIState *s, uint32_t lo)\n+{\n+ return ehci_get_buf_addr(s, s->ctrldssegment, lo, UINT32_MAX);\n+}\n+\n static void ehci_trace_usbsts(uint32_t mask, int state)\n {\n /* interrupts */\n@@ -440,7 +457,7 @@ static bool ehci_verify_qh(EHCIQueue *q, EHCIqh *qh)\n (qh->current_qtd != q->qh.current_qtd) ||\n (q->async && qh->next_qtd != q->qh.next_qtd) ||\n (memcmp(&qh->altnext_qtd, &q->qh.altnext_qtd,\n- 7 * sizeof(uint32_t)) != 0) ||\n+ EHCI_QH_OVERLAY_COUNT * sizeof(uint32_t)) != 0) ||\n (q->dev != NULL && q->dev->addr != devaddr)) {\n return false;\n } else {\n@@ -1538,7 +1555,9 @@ static int ehci_state_waitlisthead(EHCIState *ehci, int async)\n EHCIqh qh;\n int i = 0;\n int again = 0;\n- uint64_t entry = ehci->asynclistaddr;\n+ uint64_t entry = 0;\n+\n+ entry = ehci_get_desc_addr(ehci, ehci->asynclistaddr);\n \n /* set reclamation flag at start event (4.8.6) */\n if (async) {\n@@ -1566,8 +1585,8 @@ static int ehci_state_waitlisthead(EHCIState *ehci, int async)\n goto out;\n }\n \n- entry = qh.next;\n- if (entry == ehci->asynclistaddr) {\n+ entry = ehci_get_desc_addr(ehci, qh.next);\n+ if (entry == ehci_get_desc_addr(ehci, ehci->asynclistaddr)) {\n break;\n }\n }\n@@ -1693,7 +1712,7 @@ static EHCIQueue *ehci_state_fetchqh(EHCIState *ehci, int async)\n }\n \n if (trace_event_get_state_backends(TRACE_USB_EHCI_FETCHQH_DBG)) {\n- if (q->qhaddr != q->qh.next) {\n+ if (q->qhaddr != ehci_get_desc_addr(ehci, q->qh.next)) {\n trace_usb_ehci_fetchqh_dbg(q->qhaddr,\n q->qh.epchar & QH_EPCHAR_H,\n q->qh.token & QTD_TOKEN_HALT,\n@@ -1876,10 +1895,12 @@ static int ehci_state_fetchqtd(EHCIQueue *q)\n \n static int ehci_state_horizqh(EHCIQueue *q)\n {\n+ uint64_t addr;\n int again = 0;\n \n- if (ehci_get_fetch_addr(q->ehci, q->async) != q->qh.next) {\n- ehci_set_fetch_addr(q->ehci, q->async, q->qh.next);\n+ addr = ehci_get_desc_addr(q->ehci, q->qh.next);\n+ if (ehci_get_fetch_addr(q->ehci, q->async) != addr) {\n+ ehci_set_fetch_addr(q->ehci, q->async, addr);\n ehci_set_state(q->ehci, q->async, EST_FETCHENTRY);\n again = 1;\n } else {\n@@ -2205,6 +2226,8 @@ static void ehci_advance_periodic_state(EHCIState *ehci)\n uint32_t entry;\n uint32_t list;\n const int async = 0;\n+ uint64_t entry64;\n+ uint64_t list64;\n \n /* 4.6 */\n \n@@ -2229,12 +2252,14 @@ static void ehci_advance_periodic_state(EHCIState *ehci)\n break;\n }\n list |= ((ehci->frindex & 0x1ff8) >> 1);\n-\n- if (get_dwords(ehci, list, &entry, 1) < 0) {\n+ list64 = ehci_get_desc_addr(ehci, list);\n+ if (get_dwords(ehci, list64, &entry, 1) < 0) {\n break;\n }\n- trace_usb_ehci_periodic_state_advance(ehci->frindex / 8, list, entry);\n- ehci_set_fetch_addr(ehci, async, entry);\n+ entry64 = ehci_get_desc_addr(ehci, entry);\n+ trace_usb_ehci_periodic_state_advance(ehci->frindex / 8,\n+ list64, entry64);\n+ ehci_set_fetch_addr(ehci, async, entry64);\n ehci_set_state(ehci, async, EST_FETCHENTRY);\n ehci_advance_state(ehci, async);\n ehci_queues_rip_unused(ehci, async);\ndiff --git a/hw/usb/trace-events b/hw/usb/trace-events\nindex 8c90688bb3..67249d69c2 100644\n--- a/hw/usb/trace-events\n+++ b/hw/usb/trace-events\n@@ -113,7 +113,7 @@ usb_ehci_dma_error(void) \"\"\n usb_ehci_execute_complete(uint64_t qhaddr, uint32_t next, uint64_t qtdaddr, int status, int actual_length) \"qhaddr=0x%\" PRIx64 \", next=0x%x, qtdaddr=0x%\" PRIx64 \", status=%d, actual_length=%d\"\n usb_ehci_fetchqh_reclaim_done(uint64_t qhaddr) \"QH 0x%\" PRIx64 \" H-bit set, reclamation status reset - done processing\"\n usb_ehci_fetchqh_dbg(uint64_t qhaddr, uint32_t h, uint32_t halt, uint32_t active, uint32_t next) \"QH 0x%\" PRIx64 \" (h 0x%x halt 0x%x active 0x%x) next 0x%08x\"\n-usb_ehci_periodic_state_advance(uint32_t frame, uint32_t list, uint32_t entry) \"frame=%d, list=0x%x, entry=0x%x\"\n+usb_ehci_periodic_state_advance(uint32_t frame, uint64_t list, uint64_t entry) \"frame=%d, list=0x%\" PRIx64 \", entry=0x%\" PRIx64\n usb_ehci_skipped_uframes(uint64_t skipped_uframes) \"skipped %\" PRIu64 \" uframes\"\n usb_ehci_log(const char *msg) \"%s\"\n \n", "prefixes": [ "v6", "04/11" ] }