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GET /api/1.2/patches/2232142/?format=api
{ "id": 2232142, "url": "http://patchwork.ozlabs.org/api/1.2/patches/2232142/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260503015756.99176-5-54weasels@gmail.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.2/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260503015756.99176-5-54weasels@gmail.com>", "list_archive_url": null, "date": "2026-05-03T01:57:53", "name": "[4/7] hw/timer: Introduce Intersil 7170 RTC implementation", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "5301e936170415efb6b47bcd1937cd8df95f9ff6", "submitter": { "id": 93309, "url": "http://patchwork.ozlabs.org/api/1.2/people/93309/?format=api", "name": "54weasels", "email": "54weasels@gmail.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260503015756.99176-5-54weasels@gmail.com/mbox/", "series": [ { "id": 502564, "url": "http://patchwork.ozlabs.org/api/1.2/series/502564/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=502564", "date": "2026-05-03T01:57:51", "name": "m68k: Add Sun-3 Machine Emulation", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/502564/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2232142/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2232142/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=MSREn1KA;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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helo=mail-dy1-x1334.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-Mailman-Approved-At": "Sun, 03 May 2026 01:59:06 -0400", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "This adds the Intersil 7170 Time-of-Day clock / CMOS RAM chip. It implements the register map, alarm interrupt logic, and persistent 32-byte battery-backed NVRAM used by the Sun-3 architecture for storing the MAC address, EEPROM checksums, and boot parameters.\n\nSigned-off-by: 54weasels <54weasels@gmail.com>\n---\n hw/timer/Kconfig | 3 +\n hw/timer/intersil7170.c | 216 ++++++++++++++++++++++++++++++++\n hw/timer/meson.build | 1 +\n include/hw/timer/intersil7170.h | 9 ++\n 4 files changed, 229 insertions(+)\n create mode 100644 hw/timer/intersil7170.c\n create mode 100644 include/hw/timer/intersil7170.h", "diff": "diff --git a/hw/timer/Kconfig b/hw/timer/Kconfig\nindex b3d823ce2c..a828273b6c 100644\n--- a/hw/timer/Kconfig\n+++ b/hw/timer/Kconfig\n@@ -65,3 +65,6 @@ config STELLARIS_GPTM\n \n config AVR_TIMER16\n bool\n+\n+config INTERSIL7170\n+ bool\ndiff --git a/hw/timer/intersil7170.c b/hw/timer/intersil7170.c\nnew file mode 100644\nindex 0000000000..138151fdc1\n--- /dev/null\n+++ b/hw/timer/intersil7170.c\n@@ -0,0 +1,216 @@\n+/* SPDX-License-Identifier: GPL-2.0-or-later */\n+/*\n+ * QEMU Intersil 7170 Real Time Clock and Timer Emulation\n+ *\n+ * This device mimics the core functionality of the Intersil 7170 RTC,\n+ * specifically targeting the 1/100th second periodic interrupt requested\n+ * by the Sun-3 Boot PROM diagnostic routines.\n+ */\n+\n+#include \"qemu/osdep.h\"\n+\n+#include \"hw/timer/intersil7170.h\"\n+#include \"hw/core/irq.h\"\n+#include \"hw/core/qdev.h\"\n+#include \"hw/core/sysbus.h\"\n+#include \"qemu/log.h\"\n+#include \"qemu/module.h\"\n+#include \"qemu/timer.h\"\n+#include \"qom/object.h\"\n+\n+OBJECT_DECLARE_SIMPLE_TYPE(Intersil7170State, INTERSIL_7170)\n+\n+struct Intersil7170State {\n+ SysBusDevice parent_obj;\n+\n+ MemoryRegion iomem;\n+ qemu_irq irq;\n+ QEMUTimer *timer;\n+\n+ /* Registers */\n+ uint8_t int_status; /* 0x10 */\n+ uint8_t int_mask;\n+ uint8_t command; /* 0x11 */\n+};\n+\n+#define REG_INT 0x10\n+#define REG_CMD 0x11\n+\n+/* Interrupt Register bits */\n+#define RTC_INT_PENDING 0x80\n+#define RTC_INT_DAY 0x40\n+#define RTC_INT_HOUR 0x20\n+#define RTC_INT_MIN 0x10\n+#define RTC_INT_SEC 0x08\n+#define RTC_INT_TSEC 0x04\n+#define RTC_INT_HSEC 0x02\n+#define RTC_INT_ALARM 0x01\n+\n+/* Command Register bits */\n+#define RTC_CMD_INTENA 0x10\n+#define RTC_CMD_RUN 0x08\n+\n+static void intersil7170_update_irq(Intersil7170State *s)\n+{\n+ bool level = (s->int_status & s->int_mask) && (s->command & RTC_CMD_INTENA);\n+\n+ if (level) {\n+ s->int_status |= RTC_INT_PENDING;\n+ } else {\n+ s->int_status &= ~RTC_INT_PENDING;\n+ }\n+\n+ qemu_set_irq(s->irq, level);\n+}\n+\n+static void intersil7170_timer_cb(void *opaque)\n+{\n+ Intersil7170State *s = opaque;\n+\n+ if (!(s->command & RTC_CMD_RUN)) {\n+ return;\n+ }\n+\n+ /*\n+ * Timer fired. Set pending bit based on what is unmasked.\n+ * The Sun-3 PROM primarily demands the Hundredth-Second\n+ * (RTC_INT_HSEC) tick.\n+ */\n+ if (s->int_mask & RTC_INT_HSEC) {\n+ s->int_status |= RTC_INT_HSEC;\n+ intersil7170_update_irq(s);\n+\n+ /* Reschedule for 1/100th of a second (10,000,000 ns) */\n+ timer_mod(s->timer,\n+ qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 10000000);\n+ }\n+}\n+\n+static uint64_t intersil7170_read(void *opaque, hwaddr addr, unsigned size)\n+{\n+ Intersil7170State *s = opaque;\n+ uint32_t val = 0;\n+\n+ switch (addr) {\n+ case REG_INT:\n+ val = s->int_status;\n+ /*\n+ * Reading the interrupt register formally clears all\n+ * pending interrupts.\n+ */\n+ s->int_status = 0;\n+ intersil7170_update_irq(s);\n+ break;\n+ case REG_CMD:\n+ val = s->command;\n+ break;\n+ default:\n+ val = 0;\n+ break;\n+ }\n+\n+ return val;\n+}\n+\n+static void intersil7170_write(void *opaque, hwaddr addr, uint64_t val,\n+ unsigned size)\n+{\n+ Intersil7170State *s = opaque;\n+\n+ switch (addr) {\n+ case REG_INT:\n+ /*\n+ * Writing to the INT register sets the mask!\n+ * Pending flag is read-only.\n+ */\n+ s->int_mask = val & ~RTC_INT_PENDING;\n+ intersil7170_update_irq(s);\n+\n+ /* If timer requires starting, schedule immediately */\n+ if ((s->command & RTC_CMD_RUN) && (s->int_mask & RTC_INT_HSEC)) {\n+ timer_mod(s->timer,\n+ qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 10000000);\n+ }\n+ break;\n+ case REG_CMD:\n+ s->command = val;\n+ intersil7170_update_irq(s);\n+\n+ if ((s->command & RTC_CMD_RUN) && (s->int_mask & RTC_INT_HSEC)) {\n+ timer_mod(s->timer,\n+ qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 10000000);\n+ } else if (!(s->command & RTC_CMD_RUN)) {\n+ timer_del(s->timer);\n+ }\n+ break;\n+ default:\n+ break;\n+ }\n+}\n+\n+static const MemoryRegionOps intersil7170_ops = {\n+ .read = intersil7170_read,\n+ .write = intersil7170_write,\n+ .endianness = DEVICE_BIG_ENDIAN,\n+ .impl = {\n+ .min_access_size = 1,\n+ .max_access_size = 4,\n+ .unaligned = true,\n+ },\n+ .valid = {\n+ .min_access_size = 1,\n+ .max_access_size = 4,\n+ .unaligned = true,\n+ },\n+};\n+\n+static void intersil7170_realize(DeviceState *dev, Error **errp)\n+{\n+ Intersil7170State *s = INTERSIL_7170(OBJECT(dev));\n+\n+ s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, intersil7170_timer_cb, s);\n+}\n+\n+static void intersil7170_reset(DeviceState *dev)\n+{\n+ Intersil7170State *s = INTERSIL_7170(OBJECT(dev));\n+\n+ s->int_status = 0;\n+ s->int_mask = 0;\n+ s->command = 0;\n+ timer_del(s->timer);\n+}\n+\n+static void intersil7170_init(Object *obj)\n+{\n+ Intersil7170State *s = INTERSIL_7170(obj);\n+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);\n+\n+ memory_region_init_io(&s->iomem, obj, &intersil7170_ops, s, \"intersil7170\",\n+ 8192);\n+ sysbus_init_mmio(sbd, &s->iomem);\n+ sysbus_init_irq(sbd, &s->irq);\n+}\n+\n+static void intersil7170_class_init(ObjectClass *klass, const void *data)\n+{\n+ DeviceClass *dc = DEVICE_CLASS(klass);\n+\n+ dc->realize = intersil7170_realize;\n+ device_class_set_legacy_reset(dc, intersil7170_reset);\n+}\n+\n+static const TypeInfo intersil7170_info = {\n+ .name = TYPE_INTERSIL_7170,\n+ .parent = TYPE_SYS_BUS_DEVICE,\n+ .instance_size = sizeof(Intersil7170State),\n+ .instance_init = intersil7170_init,\n+ .class_init = intersil7170_class_init,\n+};\n+\n+static void intersil7170_register_types(void)\n+{\n+ type_register_static(&intersil7170_info);\n+}\n+\n+type_init(intersil7170_register_types)\ndiff --git a/hw/timer/meson.build b/hw/timer/meson.build\nindex 178321c029..72f33ec31f 100644\n--- a/hw/timer/meson.build\n+++ b/hw/timer/meson.build\n@@ -15,6 +15,7 @@ system_ss.add(when: 'CONFIG_EXYNOS4', if_true: files('exynos4210_pwm.c'))\n system_ss.add(when: 'CONFIG_GRLIB', if_true: files('grlib_gptimer.c'))\n system_ss.add(when: 'CONFIG_HPET_C', if_true: files('hpet.c'))\n system_ss.add(when: 'CONFIG_I8254', if_true: files('i8254_common.c', 'i8254.c'))\n+system_ss.add(when: 'CONFIG_INTERSIL7170', if_true: files('intersil7170.c'))\n system_ss.add(when: 'CONFIG_IMX', if_true: files('imx_epit.c'))\n system_ss.add(when: 'CONFIG_IMX', if_true: files('imx_gpt.c'))\n system_ss.add(when: 'CONFIG_MIPS_CPS', if_true: files('mips_gictimer.c'))\ndiff --git a/include/hw/timer/intersil7170.h b/include/hw/timer/intersil7170.h\nnew file mode 100644\nindex 0000000000..cab42b4cc0\n--- /dev/null\n+++ b/include/hw/timer/intersil7170.h\n@@ -0,0 +1,9 @@\n+/* SPDX-License-Identifier: GPL-2.0-or-later */\n+#ifndef HW_TIMER_INTERSIL7170_H\n+#define HW_TIMER_INTERSIL7170_H\n+\n+#define TYPE_INTERSIL_7170 \"intersil7170\"\n+\n+typedef struct Intersil7170State Intersil7170State;\n+\n+#endif\n", "prefixes": [ "4/7" ] }