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GET /api/1.2/patches/2231939/?format=api
{ "id": 2231939, "url": "http://patchwork.ozlabs.org/api/1.2/patches/2231939/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-gpio/patch/20260501155421.3329862-7-elder@riscstar.com/", "project": { "id": 42, "url": "http://patchwork.ozlabs.org/api/1.2/projects/42/?format=api", "name": "Linux GPIO development", "link_name": "linux-gpio", "list_id": "linux-gpio.vger.kernel.org", "list_email": "linux-gpio@vger.kernel.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260501155421.3329862-7-elder@riscstar.com>", "list_archive_url": null, "date": "2026-05-01T15:54:14", "name": "[net-next,06/12] net: stmmac: dwxgmac2: Add XGMAC 3.01a support", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "f805423d886ad5e52f370117500503882892a44c", "submitter": { "id": 89551, "url": "http://patchwork.ozlabs.org/api/1.2/people/89551/?format=api", "name": "Alex Elder", "email": "elder@riscstar.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-gpio/patch/20260501155421.3329862-7-elder@riscstar.com/mbox/", "series": [ { "id": 502478, "url": "http://patchwork.ozlabs.org/api/1.2/series/502478/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-gpio/list/?series=502478", "date": "2026-05-01T15:54:09", "name": "net: enable TC956x support", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/502478/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2231939/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2231939/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-gpio+bounces-35958-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-gpio@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=riscstar-com.20251104.gappssmtp.com\n header.i=@riscstar-com.20251104.gappssmtp.com header.a=rsa-sha256\n header.s=20251104 header.b=OrjKZ4BA;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c09:e001:a7::12fc:5321; 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That means that\nfor everything except one erratum we can simply use the XGMAC 2.x\ncallback functions in the stmmac_dma_ops structure.\n\nOnly the set_rx_ring_len callback is specific to XGMAC 3.01. It\nlimits the number of outstanding write requests that can be serviced\nper DMA.\n\nThe other erratum addressed in this patch is simply a comment to\nensure that a feature that stmmac doesn't currently use is not enabled\nwithout contemplating the errata.\n\nSigned-off-by: Daniel Thompson <daniel@riscstar.com>\nSigned-off-by: Alex Elder <elder@riscstar.com>\n---\n .../net/ethernet/stmicro/stmmac/dwxgmac2.h | 3 ++\n .../ethernet/stmicro/stmmac/dwxgmac2_dma.c | 52 +++++++++++++++++++\n 2 files changed, 55 insertions(+)", "diff": "diff --git a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h\nindex 9b0b5cc619556..bcf59ad8a1939 100644\n--- a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h\n+++ b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h\n@@ -374,6 +374,8 @@\n #define XGMAC_DMA_CH_RxDESC_TAIL_LPTR(x)\t(0x0000312c + (0x80 * (x)))\n #define XGMAC_DMA_CH_TxDESC_RING_LEN(x)\t\t(0x00003130 + (0x80 * (x)))\n #define XGMAC_DMA_CH_RxDESC_RING_LEN(x)\t\t(0x00003134 + (0x80 * (x)))\n+#define XGMAC_OWRQ\t\t\tGENMASK(25, 24)\n+#define XGMAC_RDRL\t\t\tGENMASK(15, 0)\n #define XGMAC_DMA_CH_INT_EN(x)\t\t(0x00003138 + (0x80 * (x)))\n #define XGMAC_NIE\t\t\tBIT(15)\n #define XGMAC_AIE\t\t\tBIT(14)\n@@ -463,6 +465,7 @@\n extern const struct stmmac_ops dwxgmac210_ops;\n extern const struct stmmac_ops dwxlgmac2_ops;\n extern const struct stmmac_dma_ops dwxgmac210_dma_ops;\n+extern const struct stmmac_dma_ops dwxgmac301_dma_ops;\n extern const struct stmmac_desc_ops dwxgmac210_desc_ops;\n \n #endif /* __STMMAC_DWXGMAC2_H__ */\ndiff --git a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c\nindex a84601ac32153..dc2897e9931d1 100644\n--- a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c\n+++ b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c\n@@ -38,6 +38,14 @@ static void dwxgmac2_dma_init(void __iomem *ioaddr,\n \t\tvalue = u32_replace_bits(value, XGMAC_INTM_MODE1,\n \t\t\t\t\t XGMAC_INTM_MASK);\n \n+\t/*\n+\t * A friendly warning to future adventurers. If Descriptor Posted\n+\t * Write support, which is off by default, is ever enabled then be sure\n+\t * to make it optional. This is required by errata for at least XGMAC\n+\t * 3.01A... and the XGMAC 2.x and 3.x are architecturally similar so we\n+\t * use dwxgmac2 support for the 3.x family as well.\n+\t */\n+\n \twritel(value, ioaddr + XGMAC_DMA_MODE);\n }\n \n@@ -490,6 +498,20 @@ static void dwxgmac2_set_rx_ring_len(struct stmmac_priv *priv,\n \twritel(len, ioaddr + XGMAC_DMA_CH_RxDESC_RING_LEN(chan));\n }\n \n+static void dwxgmac301_set_rx_ring_len(struct stmmac_priv *priv,\n+\t\t\t\t void __iomem *ioaddr, u32 len, u32 chan)\n+{\n+\tu32 val = FIELD_PREP(XGMAC_RDRL, len);\n+\n+\t/*\n+\t * Reduce the number of outstanding write requests to 3 (from default\n+\t * of 4). This is an errata workaround for XGMAC 3.01a.\n+\t */\n+\tval |= FIELD_PREP(XGMAC_OWRQ, 3);\n+\n+\twritel(val, ioaddr + XGMAC_DMA_CH_RxDESC_RING_LEN(chan));\n+}\n+\n static void dwxgmac2_set_tx_ring_len(struct stmmac_priv *priv,\n \t\t\t\t void __iomem *ioaddr, u32 len, u32 chan)\n {\n@@ -619,3 +641,33 @@ const struct stmmac_dma_ops dwxgmac210_dma_ops = {\n \t.enable_sph = dwxgmac2_enable_sph,\n \t.enable_tbs = dwxgmac2_enable_tbs,\n };\n+\n+const struct stmmac_dma_ops dwxgmac301_dma_ops = {\n+\t.reset = dwxgmac2_dma_reset,\n+\t.init = dwxgmac2_dma_init,\n+\t.init_chan = dwxgmac2_dma_init_chan,\n+\t.init_rx_chan = dwxgmac2_dma_init_rx_chan,\n+\t.init_tx_chan = dwxgmac2_dma_init_tx_chan,\n+\t.axi = dwxgmac2_dma_axi,\n+\t.dump_regs = dwxgmac2_dma_dump_regs,\n+\t.dma_rx_mode = dwxgmac2_dma_rx_mode,\n+\t.dma_tx_mode = dwxgmac2_dma_tx_mode,\n+\t.enable_dma_irq = dwxgmac2_enable_dma_irq,\n+\t.disable_dma_irq = dwxgmac2_disable_dma_irq,\n+\t.start_tx = dwxgmac2_dma_start_tx,\n+\t.stop_tx = dwxgmac2_dma_stop_tx,\n+\t.start_rx = dwxgmac2_dma_start_rx,\n+\t.stop_rx = dwxgmac2_dma_stop_rx,\n+\t.dma_interrupt = dwxgmac2_dma_interrupt,\n+\t.get_hw_feature = dwxgmac2_get_hw_feature,\n+\t.rx_watchdog = dwxgmac2_rx_watchdog,\n+\t.set_rx_ring_len = dwxgmac301_set_rx_ring_len,\n+\t.set_tx_ring_len = dwxgmac2_set_tx_ring_len,\n+\t.set_rx_tail_ptr = dwxgmac2_set_rx_tail_ptr,\n+\t.set_tx_tail_ptr = dwxgmac2_set_tx_tail_ptr,\n+\t.enable_tso = dwxgmac2_enable_tso,\n+\t.qmode = dwxgmac2_qmode,\n+\t.set_bfsize = dwxgmac2_set_bfsize,\n+\t.enable_sph = dwxgmac2_enable_sph,\n+\t.enable_tbs = dwxgmac2_enable_tbs,\n+};\n", "prefixes": [ "net-next", "06/12" ] }