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put:
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GET /api/1.2/patches/2231932/?format=api
HTTP 200 OK
Allow: GET, PUT, PATCH, HEAD, OPTIONS
Content-Type: application/json
Vary: Accept

{
    "id": 2231932,
    "url": "http://patchwork.ozlabs.org/api/1.2/patches/2231932/?format=api",
    "web_url": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260501153553.66382-3-18255117159@163.com/",
    "project": {
        "id": 28,
        "url": "http://patchwork.ozlabs.org/api/1.2/projects/28/?format=api",
        "name": "Linux PCI development",
        "link_name": "linux-pci",
        "list_id": "linux-pci.vger.kernel.org",
        "list_email": "linux-pci@vger.kernel.org",
        "web_url": null,
        "scm_url": null,
        "webscm_url": null,
        "list_archive_url": "",
        "list_archive_url_format": "",
        "commit_url_format": ""
    },
    "msgid": "<20260501153553.66382-3-18255117159@163.com>",
    "list_archive_url": null,
    "date": "2026-05-01T15:35:53",
    "name": "[2/2] PCI: j721e: Set max_link_speed to enable 100 ms delay after link up",
    "commit_ref": null,
    "pull_url": null,
    "state": "new",
    "archived": false,
    "hash": "2d996c4331c269a6c509bb75160cb0a0c44cbf92",
    "submitter": {
        "id": 89937,
        "url": "http://patchwork.ozlabs.org/api/1.2/people/89937/?format=api",
        "name": "Hans Zhang",
        "email": "18255117159@163.com"
    },
    "delegate": null,
    "mbox": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260501153553.66382-3-18255117159@163.com/mbox/",
    "series": [
        {
            "id": 502476,
            "url": "http://patchwork.ozlabs.org/api/1.2/series/502476/?format=api",
            "web_url": "http://patchwork.ozlabs.org/project/linux-pci/list/?series=502476",
            "date": "2026-05-01T15:35:53",
            "name": "PCI: cadence: Add 100 ms delay after link up for speeds > 5 GT/s",
            "version": 1,
            "mbox": "http://patchwork.ozlabs.org/series/502476/mbox/"
        }
    ],
    "comments": "http://patchwork.ozlabs.org/api/patches/2231932/comments/",
    "check": "pending",
    "checks": "http://patchwork.ozlabs.org/api/patches/2231932/checks/",
    "tags": {},
    "related": [],
    "headers": {
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        "From": "Hans Zhang <18255117159@163.com>",
        "To": "bhelgaas@google.com,\n\tlpieralisi@kernel.org,\n\tkwilczynski@kernel.org,\n\tmani@kernel.org,\n\tvigneshr@ti.com",
        "Cc": "robh@kernel.org,\n\ts-vadapalli@ti.com,\n\tlinux-omap@vger.kernel.org,\n\tlinux-arm-kernel@lists.infradead.org,\n\tlinux-pci@vger.kernel.org,\n\tlinux-kernel@vger.kernel.org,\n\tHans Zhang <18255117159@163.com>",
        "Subject": "[PATCH 2/2] PCI: j721e: Set max_link_speed to enable 100 ms delay\n after link up",
        "Date": "Fri,  1 May 2026 23:35:53 +0800",
        "Message-Id": "<20260501153553.66382-3-18255117159@163.com>",
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        "In-Reply-To": "<20260501153553.66382-1-18255117159@163.com>",
        "References": "<20260501153553.66382-1-18255117159@163.com>",
        "Precedence": "bulk",
        "X-Mailing-List": "linux-pci@vger.kernel.org",
        "List-Id": "<linux-pci.vger.kernel.org>",
        "List-Subscribe": "<mailto:linux-pci+subscribe@vger.kernel.org>",
        "List-Unsubscribe": "<mailto:linux-pci+unsubscribe@vger.kernel.org>",
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    },
    "content": "Set cdns_pcie.max_link_speed to the maximum supported link speed\n(obtained from the device tree property \"max-link-speed\") in\nj721e_pcie_set_link_speed(). This activates the post-link delay logic\nadded in cdns_pcie_host_wait_for_link() when the controller supports\nspeeds greater than 5 GT/s.\n\nAs required by PCIe r6.0 sec 6.6.1, and following the same approach as\ncommit 80dc18a0cba8d (\"PCI: dwc: Ensure that dw_pcie_wait_for_link()\nwaits 100 ms after link up\"), this ensures a 100 ms delay after link\ntraining completes before any Configuration Request is sent.\n\nSigned-off-by: Hans Zhang <18255117159@163.com>\n---\n drivers/pci/controller/cadence/pci-j721e.c | 1 +\n 1 file changed, 1 insertion(+)",
    "diff": "diff --git a/drivers/pci/controller/cadence/pci-j721e.c b/drivers/pci/controller/cadence/pci-j721e.c\nindex bfdfe98d5aba..ee85b8e04f5b 100644\n--- a/drivers/pci/controller/cadence/pci-j721e.c\n+++ b/drivers/pci/controller/cadence/pci-j721e.c\n@@ -206,6 +206,7 @@ static int j721e_pcie_set_link_speed(struct j721e_pcie *pcie,\n \t    (pcie_get_link_speed(link_speed) == PCI_SPEED_UNKNOWN))\n \t\tlink_speed = 2;\n \n+\tpcie->cdns_pcie.max_link_speed = link_speed;\n \tval = link_speed - 1;\n \tret = regmap_update_bits(syscon, offset, GENERATION_SEL_MASK, val);\n \tif (ret)\n",
    "prefixes": [
        "2/2"
    ]
}